[PATCH 0/6] Add RIIC support for RZ/T2H and RZ/N2H SoCs

[PATCH 0/6] Add RIIC support for RZ/T2H and RZ/N2H SoCs

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series adds support for I2C Bus Interface (RIIC) found on
the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. The RIIC
IP on these SoCs is similar to that on the RZ/V2H(P) SoC but has some
differences in interrupt handling and does not require resets.

Cheers,
Prabhakar

Lad Prabhakar (6):
  dt-bindings: i2c: renesas,riic: Move ref for i2c-controller.yaml to
    the end
  dt-bindings: i2c: renesas,riic: Document RZ/T2H support
  dt-bindings: i2c: renesas,riic: Document RZ/N2H support
  i2c: riic: Pass IRQ desc array as part of OF data
  i2c: riic: Move generic compatible string to end of array
  i2c: riic: Add support for RZ/T2H SoC

 .../devicetree/bindings/i2c/renesas,riic.yaml | 105 ++++++++++++------
 drivers/i2c/busses/i2c-riic.c                 |  54 +++++++--
 2 files changed, 117 insertions(+), 42 deletions(-)

-- 
2.49.0

[PATCH 1/6] dt-bindings: i2c: renesas,riic: Move ref for i2c-controller.yaml to the end

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

In preparation for adding more validation checks, move the `$ref` for
'i2c-controller.yaml' to the end of the file. Also, relocate the
conditional check for 'resets' into the 'allOf' block.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../devicetree/bindings/i2c/renesas,riic.yaml | 30 +++++++++----------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
index cc39511a49d6..bfcc400655dc 100644
--- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
+++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
@@ -10,9 +10,6 @@ maintainers:
   - Chris Brandt <chris.brandt@renesas.com>
   - Wolfram Sang <wsa+renesas@sang-engineering.com>
 
-allOf:
-  - $ref: /schemas/i2c/i2c-controller.yaml#
-
 properties:
   compatible:
     oneOf:
@@ -84,18 +81,21 @@ required:
   - '#address-cells'
   - '#size-cells'
 
-if:
-  properties:
-    compatible:
-      contains:
-        enum:
-          - renesas,riic-r9a07g043
-          - renesas,riic-r9a07g044
-          - renesas,riic-r9a07g054
-          - renesas,riic-r9a09g057
-then:
-  required:
-    - resets
+allOf:
+  - $ref: /schemas/i2c/i2c-controller.yaml#
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,riic-r9a07g043
+              - renesas,riic-r9a07g044
+              - renesas,riic-r9a07g054
+              - renesas,riic-r9a09g057
+    then:
+      required:
+        - resets
 
 unevaluatedProperties: false
 
-- 
2.49.0

[PATCH 2/6] dt-bindings: i2c: renesas,riic: Document RZ/T2H support

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Document support for the I2C Bus Interface (RIIC) found on the Renesas
RZ/T2H (R9A09G077) SoC. The RIIC IP on this SoC is similar to that on
the RZ/V2H(P) SoC but supports fewer interrupts, lacks FM+ support and
does not require resets. Due to these differences, add a new compatible
string `renesas,riic-r9a09g077` for the RZ/T2H SoC.

Unlike earlier SoCs that use eight distinct interrupts, the RZ/T2H uses
only four, including a combined error/event interrupt. Update the binding
schema to reflect this interrupt layout and skip the `resets` property
check, as it is not required on these SoCs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../devicetree/bindings/i2c/renesas,riic.yaml | 71 ++++++++++++++-----
 1 file changed, 52 insertions(+), 19 deletions(-)

diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
index bfcc400655dc..d2b11a702be0 100644
--- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
+++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
@@ -29,32 +29,46 @@ properties:
               - renesas,riic-r9a09g056   # RZ/V2N
           - const: renesas,riic-r9a09g057   # RZ/V2H(P)
 
-      - const: renesas,riic-r9a09g057   # RZ/V2H(P)
+      - enum:
+          - renesas,riic-r9a09g057   # RZ/V2H(P)
+          - renesas,riic-r9a09g077   # RZ/T2H
 
   reg:
     maxItems: 1
 
   interrupts:
-    items:
-      - description: Transmit End Interrupt
-      - description: Receive Data Full Interrupt
-      - description: Transmit Data Empty Interrupt
-      - description: Stop Condition Detection Interrupt
-      - description: Start Condition Detection Interrupt
-      - description: NACK Reception Interrupt
-      - description: Arbitration-Lost Interrupt
-      - description: Timeout Interrupt
+    oneOf:
+      - items:
+          - description: Transmit End Interrupt
+          - description: Receive Data Full Interrupt
+          - description: Transmit Data Empty Interrupt
+          - description: Stop Condition Detection Interrupt
+          - description: Start Condition Detection Interrupt
+          - description: NACK Reception Interrupt
+          - description: Arbitration-Lost Interrupt
+          - description: Timeout Interrupt
+      - items:
+          - description: Transmit End Interrupt
+          - description: Receive Data Full Interrupt
+          - description: Transmit Data Empty Interrupt
+          - description: Transmit error or event Interrupt
 
   interrupt-names:
-    items:
-      - const: tei
-      - const: ri
-      - const: ti
-      - const: spi
-      - const: sti
-      - const: naki
-      - const: ali
-      - const: tmoi
+    oneOf:
+      - items:
+          - const: tei
+          - const: ri
+          - const: ti
+          - const: spi
+          - const: sti
+          - const: naki
+          - const: ali
+          - const: tmoi
+      - items:
+          - const: tei
+          - const: ri
+          - const: ti
+          - const: eei
 
   clock-frequency:
     description:
@@ -84,6 +98,25 @@ required:
 allOf:
   - $ref: /schemas/i2c/i2c-controller.yaml#
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,riic-r9a09g077
+    then:
+      properties:
+        interrupts:
+          maxItems: 4
+        interrupt-names:
+          maxItems: 4
+        resets: false
+    else:
+      properties:
+        interrupts:
+          minItems: 8
+        interrupt-names:
+          minItems: 8
+
   - if:
       properties:
         compatible:
-- 
2.49.0

[PATCH 3/6] dt-bindings: i2c: renesas,riic: Document RZ/N2H support

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Document support for the I2C Bus Interface (RIIC) found on the Renesas
RZ/N2H (R9A09G087) SoC. The RIIC IP on this SoC is identical to that on
the RZ/T2H SoC so `renesas,riic-r9a09g077` will be used as a fallback
compatible.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 Documentation/devicetree/bindings/i2c/renesas,riic.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
index d2b11a702be0..6d4713e384a7 100644
--- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
+++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
@@ -33,6 +33,10 @@ properties:
           - renesas,riic-r9a09g057   # RZ/V2H(P)
           - renesas,riic-r9a09g077   # RZ/T2H
 
+      - items:
+          - const: renesas,riic-r9a09g087  # RZ/N2H
+          - const: renesas,riic-r9a09g077  # RZ/T2H
+
   reg:
     maxItems: 1
 
-- 
2.49.0

[PATCH 4/6] i2c: riic: Pass IRQ desc array as part of OF data

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

In preparation for adding support for Renesas RZ/T2H and RZ/N2H SoCs,
which feature a combined error interrupt instead of individual error
interrupts per condition, update the driver to support configurable IRQ
layouts via OF data.

Introduce a new `irqs` field and `num_irqs` count in `riic_of_data` to
allow future SoCs to provide a custom IRQ layout. This patch is a
non-functional change for existing SoCs and maintains compatibility with
the current `riic_irqs` array.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/i2c/busses/i2c-riic.c | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index 23375f7fe3ad..4950b790cfe7 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -102,6 +102,8 @@ enum riic_reg_list {
 
 struct riic_of_data {
 	const u8 *regs;
+	const struct riic_irq_desc *irqs;
+	u8 num_irqs;
 	bool fast_mode_plus;
 };
 
@@ -520,21 +522,23 @@ static int riic_i2c_probe(struct platform_device *pdev)
 		return dev_err_probe(dev, PTR_ERR(riic->rstc),
 				     "failed to acquire deasserted reset\n");
 
-	for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
+	riic->info = of_device_get_match_data(dev);
+
+	for (i = 0; i < riic->info->num_irqs; i++) {
+		const struct riic_irq_desc *irq_desc;
 		int irq;
 
-		irq = platform_get_irq(pdev, riic_irqs[i].res_num);
+		irq_desc = &riic->info->irqs[i];
+		irq = platform_get_irq(pdev, irq_desc->res_num);
 		if (irq < 0)
 			return irq;
 
-		ret = devm_request_irq(dev, irq, riic_irqs[i].isr,
-				       0, riic_irqs[i].name, riic);
+		ret = devm_request_irq(dev, irq, irq_desc->isr, 0, irq_desc->name, riic);
 		if (ret)
 			return dev_err_probe(dev, ret, "failed to request irq %s\n",
-					     riic_irqs[i].name);
+					     irq_desc->name);
 	}
 
-	riic->info = of_device_get_match_data(dev);
 
 	adap = &riic->adapter;
 	i2c_set_adapdata(adap, riic);
@@ -607,10 +611,14 @@ static const u8 riic_rz_a_regs[RIIC_REG_END] = {
 static const struct riic_of_data riic_rz_a_info = {
 	.regs = riic_rz_a_regs,
 	.fast_mode_plus = true,
+	.irqs = riic_irqs,
+	.num_irqs = ARRAY_SIZE(riic_irqs),
 };
 
 static const struct riic_of_data riic_rz_a1h_info = {
 	.regs = riic_rz_a_regs,
+	.irqs = riic_irqs,
+	.num_irqs = ARRAY_SIZE(riic_irqs),
 };
 
 static const u8 riic_rz_v2h_regs[RIIC_REG_END] = {
@@ -631,6 +639,8 @@ static const u8 riic_rz_v2h_regs[RIIC_REG_END] = {
 static const struct riic_of_data riic_rz_v2h_info = {
 	.regs = riic_rz_v2h_regs,
 	.fast_mode_plus = true,
+	.irqs = riic_irqs,
+	.num_irqs = ARRAY_SIZE(riic_irqs),
 };
 
 static int riic_i2c_suspend(struct device *dev)
-- 
2.49.0

[PATCH 5/6] i2c: riic: Move generic compatible string to end of array

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reorder the entry in `riic_i2c_dt_ids` to place the generic compatible
string `renesas,riic-rz` at the end of the array, following the
convention used in other Renesas drivers.

Also, drop the unnecessary comma after the sentinel entry, as it is
not needed.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/i2c/busses/i2c-riic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index 4950b790cfe7..a4df00cb470c 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -693,10 +693,10 @@ static const struct dev_pm_ops riic_i2c_pm_ops = {
 };
 
 static const struct of_device_id riic_i2c_dt_ids[] = {
-	{ .compatible = "renesas,riic-rz", .data = &riic_rz_a_info },
 	{ .compatible = "renesas,riic-r7s72100", .data =  &riic_rz_a1h_info, },
 	{ .compatible = "renesas,riic-r9a09g057", .data = &riic_rz_v2h_info },
-	{ /* Sentinel */ },
+	{ .compatible = "renesas,riic-rz", .data = &riic_rz_a_info },
+	{ /* Sentinel */ }
 };
 
 static struct platform_driver riic_i2c_driver = {
-- 
2.49.0

[PATCH 6/6] i2c: riic: Add support for RZ/T2H SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add support for the Renesas RZ/T2H (R9A09G077) SoC, which features a
different interrupt layout for the RIIC controller. Unlike other SoCs
with individual error interrupts, RZ/T2H uses a combined error interrupt
(EEI).

Introduce a new IRQ descriptor table for RZ/T2H, along with a custom
ISR (`riic_eei_isr`) to handle STOP and NACK detection from the shared
interrupt.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/i2c/busses/i2c-riic.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
index a4df00cb470c..1f9299f5effa 100644
--- a/drivers/i2c/busses/i2c-riic.c
+++ b/drivers/i2c/busses/i2c-riic.c
@@ -79,6 +79,7 @@
 #define ICIER_SPIE	BIT(3)
 
 #define ICSR2_NACKF	BIT(4)
+#define ICSR2_STOP	BIT(3)
 
 #define ICBR_RESERVED	GENMASK(7, 5) /* Should be 1 on writes */
 
@@ -326,6 +327,19 @@ static irqreturn_t riic_stop_isr(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
+static irqreturn_t riic_eei_isr(int irq, void *data)
+{
+	u8 icsr2 = riic_readb(data, RIIC_ICSR2);
+
+	if (icsr2 & ICSR2_NACKF)
+		return riic_tend_isr(irq, data);
+
+	if (icsr2 & ICSR2_STOP)
+		return riic_stop_isr(irq, data);
+
+	return IRQ_NONE;
+}
+
 static u32 riic_func(struct i2c_adapter *adap)
 {
 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
@@ -497,6 +511,13 @@ static const struct riic_irq_desc riic_irqs[] = {
 	{ .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
 };
 
+static const struct riic_irq_desc riic_rzt2h_irqs[] = {
+	{ .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
+	{ .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
+	{ .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
+	{ .res_num = 3, .isr = riic_eei_isr,  .name = "riic-eei" },
+};
+
 static int riic_i2c_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -643,6 +664,12 @@ static const struct riic_of_data riic_rz_v2h_info = {
 	.num_irqs = ARRAY_SIZE(riic_irqs),
 };
 
+static const struct riic_of_data riic_rz_t2h_info = {
+	.regs = riic_rz_v2h_regs,
+	.irqs = riic_rzt2h_irqs,
+	.num_irqs = ARRAY_SIZE(riic_rzt2h_irqs),
+};
+
 static int riic_i2c_suspend(struct device *dev)
 {
 	struct riic_dev *riic = dev_get_drvdata(dev);
@@ -695,6 +722,7 @@ static const struct dev_pm_ops riic_i2c_pm_ops = {
 static const struct of_device_id riic_i2c_dt_ids[] = {
 	{ .compatible = "renesas,riic-r7s72100", .data =  &riic_rz_a1h_info, },
 	{ .compatible = "renesas,riic-r9a09g057", .data = &riic_rz_v2h_info },
+	{ .compatible = "renesas,riic-r9a09g077", .data = &riic_rz_t2h_info },
 	{ .compatible = "renesas,riic-rz", .data = &riic_rz_a_info },
 	{ /* Sentinel */ }
 };
-- 
2.49.0

Re: [PATCH 1/6] dt-bindings: i2c: renesas,riic: Move ref for i2c-controller.yaml to the end

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 461 bytes --]

On Fri, May 30, 2025 at 03:31:30PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> In preparation for adding more validation checks, move the `$ref` for
> 'i2c-controller.yaml' to the end of the file. Also, relocate the
> conditional check for 'resets' into the 'allOf' block.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 2/6] dt-bindings: i2c: renesas,riic: Document RZ/T2H support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 890 bytes --]

On Fri, May 30, 2025 at 03:31:31PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Document support for the I2C Bus Interface (RIIC) found on the Renesas
> RZ/T2H (R9A09G077) SoC. The RIIC IP on this SoC is similar to that on
> the RZ/V2H(P) SoC but supports fewer interrupts, lacks FM+ support and
> does not require resets. Due to these differences, add a new compatible
> string `renesas,riic-r9a09g077` for the RZ/T2H SoC.
> 
> Unlike earlier SoCs that use eight distinct interrupts, the RZ/T2H uses
> only four, including a combined error/event interrupt. Update the binding
> schema to reflect this interrupt layout and skip the `resets` property
> check, as it is not required on these SoCs.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 3/6] dt-bindings: i2c: renesas,riic: Document RZ/N2H support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 499 bytes --]

On Fri, May 30, 2025 at 03:31:32PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Document support for the I2C Bus Interface (RIIC) found on the Renesas
> RZ/N2H (R9A09G087) SoC. The RIIC IP on this SoC is identical to that on
> the RZ/T2H SoC so `renesas,riic-r9a09g077` will be used as a fallback
> compatible.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 0/6] Add RIIC support for RZ/T2H and RZ/N2H SoCs

[Andy Shevchenko]

On Fri, May 30, 2025 at 03:31:29PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Hi All,
> 
> This patch series adds support for I2C Bus Interface (RIIC) found on
> the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. The RIIC
> IP on these SoCs is similar to that on the RZ/V2H(P) SoC but has some
> differences in interrupt handling and does not require resets.

Patches 4, 5, and 6 LGTM, FWIW,
Reviewed-by: Andy Shevchenko <andy@kernel.org>

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 2/6] dt-bindings: i2c: renesas,riic: Document RZ/T2H support

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 901 bytes --]

On Fri, May 30, 2025 at 03:31:31PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Document support for the I2C Bus Interface (RIIC) found on the Renesas
> RZ/T2H (R9A09G077) SoC. The RIIC IP on this SoC is similar to that on
> the RZ/V2H(P) SoC but supports fewer interrupts, lacks FM+ support and
> does not require resets. Due to these differences, add a new compatible
> string `renesas,riic-r9a09g077` for the RZ/T2H SoC.
> 
> Unlike earlier SoCs that use eight distinct interrupts, the RZ/T2H uses
> only four, including a combined error/event interrupt. Update the binding
> schema to reflect this interrupt layout and skip the `resets` property
> check, as it is not required on these SoCs.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH 3/6] dt-bindings: i2c: renesas,riic: Document RZ/N2H support

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 510 bytes --]

On Fri, May 30, 2025 at 03:31:32PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Document support for the I2C Bus Interface (RIIC) found on the Renesas
> RZ/N2H (R9A09G087) SoC. The RIIC IP on this SoC is identical to that on
> the RZ/T2H SoC so `renesas,riic-r9a09g077` will be used as a fallback
> compatible.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH 4/6] i2c: riic: Pass IRQ desc array as part of OF data

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 830 bytes --]

On Fri, May 30, 2025 at 03:31:33PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> In preparation for adding support for Renesas RZ/T2H and RZ/N2H SoCs,
> which feature a combined error interrupt instead of individual error
> interrupts per condition, update the driver to support configurable IRQ
> layouts via OF data.
> 
> Introduce a new `irqs` field and `num_irqs` count in `riic_of_data` to
> allow future SoCs to provide a custom IRQ layout. This patch is a
> non-functional change for existing SoCs and maintains compatibility with
> the current `riic_irqs` array.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Did you test this on RZ/A1? I could do so next week?


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH 5/6] i2c: riic: Move generic compatible string to end of array

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 569 bytes --]

On Fri, May 30, 2025 at 03:31:34PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Reorder the entry in `riic_i2c_dt_ids` to place the generic compatible
> string `renesas,riic-rz` at the end of the array, following the
> convention used in other Renesas drivers.
> 
> Also, drop the unnecessary comma after the sentinel entry, as it is
> not needed.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Well, why not...

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH 6/6] i2c: riic: Add support for RZ/T2H SoC

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 668 bytes --]

On Fri, May 30, 2025 at 03:31:35PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add support for the Renesas RZ/T2H (R9A09G077) SoC, which features a
> different interrupt layout for the RIIC controller. Unlike other SoCs
> with individual error interrupts, RZ/T2H uses a combined error interrupt
> (EEI).
> 
> Introduce a new IRQ descriptor table for RZ/T2H, along with a custom
> ISR (`riic_eei_isr`) to handle STOP and NACK detection from the shared
> interrupt.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH 4/6] i2c: riic: Pass IRQ desc array as part of OF data

[Lad, Prabhakar]

Hi Wolfram,

Thank you for the review.

On Sat, May 31, 2025 at 1:12 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
>
> On Fri, May 30, 2025 at 03:31:33PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > In preparation for adding support for Renesas RZ/T2H and RZ/N2H SoCs,
> > which feature a combined error interrupt instead of individual error
> > interrupts per condition, update the driver to support configurable IRQ
> > layouts via OF data.
> >
> > Introduce a new `irqs` field and `num_irqs` count in `riic_of_data` to
> > allow future SoCs to provide a custom IRQ layout. This patch is a
> > non-functional change for existing SoCs and maintains compatibility with
> > the current `riic_irqs` array.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>
> Did you test this on RZ/A1? I could do so next week?
>
Unfortunately, I haven’t been able to test this on the RZ/A1 as I
don’t have access to the hardware. If you’re able to run it next week,
that would be really helpful.

Cheers,
Prabhakar

Re: [PATCH 4/6] i2c: riic: Pass IRQ desc array as part of OF data

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 783 bytes --]

On Fri, May 30, 2025 at 03:31:33PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> In preparation for adding support for Renesas RZ/T2H and RZ/N2H SoCs,
> which feature a combined error interrupt instead of individual error
> interrupts per condition, update the driver to support configurable IRQ
> layouts via OF data.
> 
> Introduce a new `irqs` field and `num_irqs` count in `riic_of_data` to
> allow future SoCs to provide a custom IRQ layout. This patch is a
> non-functional change for existing SoCs and maintains compatibility with
> the current `riic_irqs` array.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> # on RZ/A1


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH 5/6] i2c: riic: Move generic compatible string to end of array

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 558 bytes --]

On Fri, May 30, 2025 at 03:31:34PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Reorder the entry in `riic_i2c_dt_ids` to place the generic compatible
> string `renesas,riic-rz` at the end of the array, following the
> convention used in other Renesas drivers.
> 
> Also, drop the unnecessary comma after the sentinel entry, as it is
> not needed.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> # on RZ/A1


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH 6/6] i2c: riic: Add support for RZ/T2H SoC

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 677 bytes --]

On Fri, May 30, 2025 at 03:31:35PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add support for the Renesas RZ/T2H (R9A09G077) SoC, which features a
> different interrupt layout for the RIIC controller. Unlike other SoCs
> with individual error interrupts, RZ/T2H uses a combined error interrupt
> (EEI).
> 
> Introduce a new IRQ descriptor table for RZ/T2H, along with a custom
> ISR (`riic_eei_isr`) to handle STOP and NACK detection from the shared
> interrupt.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> # on RZ/A1


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH 1/6] dt-bindings: i2c: renesas,riic: Move ref for i2c-controller.yaml to the end

[Geert Uytterhoeven]

On Fri, 30 May 2025 at 16:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> In preparation for adding more validation checks, move the `$ref` for
> 'i2c-controller.yaml' to the end of the file. Also, relocate the
> conditional check for 'resets' into the 'allOf' block.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/6] dt-bindings: i2c: renesas,riic: Document RZ/T2H support

[Geert Uytterhoeven]

Hi Prabhakar,

On Fri, 30 May 2025 at 16:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Document support for the I2C Bus Interface (RIIC) found on the Renesas
> RZ/T2H (R9A09G077) SoC. The RIIC IP on this SoC is similar to that on
> the RZ/V2H(P) SoC but supports fewer interrupts, lacks FM+ support and
> does not require resets. Due to these differences, add a new compatible
> string `renesas,riic-r9a09g077` for the RZ/T2H SoC.
>
> Unlike earlier SoCs that use eight distinct interrupts, the RZ/T2H uses
> only four, including a combined error/event interrupt. Update the binding
> schema to reflect this interrupt layout and skip the `resets` property
> check, as it is not required on these SoCs.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> @@ -29,32 +29,46 @@ properties:
>                - renesas,riic-r9a09g056   # RZ/V2N
>            - const: renesas,riic-r9a09g057   # RZ/V2H(P)
>
> -      - const: renesas,riic-r9a09g057   # RZ/V2H(P)
> +      - enum:
> +          - renesas,riic-r9a09g057   # RZ/V2H(P)
> +          - renesas,riic-r9a09g077   # RZ/T2H
>
>    reg:
>      maxItems: 1
>
>    interrupts:
> -    items:
> -      - description: Transmit End Interrupt
> -      - description: Receive Data Full Interrupt
> -      - description: Transmit Data Empty Interrupt
> -      - description: Stop Condition Detection Interrupt
> -      - description: Start Condition Detection Interrupt
> -      - description: NACK Reception Interrupt
> -      - description: Arbitration-Lost Interrupt
> -      - description: Timeout Interrupt
> +    oneOf:
> +      - items:
> +          - description: Transmit End Interrupt
> +          - description: Receive Data Full Interrupt
> +          - description: Transmit Data Empty Interrupt
> +          - description: Stop Condition Detection Interrupt
> +          - description: Start Condition Detection Interrupt
> +          - description: NACK Reception Interrupt
> +          - description: Arbitration-Lost Interrupt
> +          - description: Timeout Interrupt
> +      - items:
> +          - description: Transmit End Interrupt
> +          - description: Receive Data Full Interrupt
> +          - description: Transmit Data Empty Interrupt
> +          - description: Transmit error or event Interrupt

Nit: the documentation calls it "Transfer error or event generation".

>
>    interrupt-names:
> -    items:
> -      - const: tei
> -      - const: ri
> -      - const: ti
> -      - const: spi
> -      - const: sti
> -      - const: naki
> -      - const: ali
> -      - const: tmoi
> +    oneOf:
> +      - items:
> +          - const: tei
> +          - const: ri
> +          - const: ti
> +          - const: spi
> +          - const: sti
> +          - const: naki
> +          - const: ali
> +          - const: tmoi
> +      - items:
> +          - const: tei
> +          - const: ri
> +          - const: ti

Given you have a new set of names, perhaps "rxi" and "txi",
to match the documentation?

> +          - const: eei

Perhaps use the order from the documentation: eei, rxi, txi, tei?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/6] dt-bindings: i2c: renesas,riic: Document RZ/N2H support

[Geert Uytterhoeven]

On Fri, 30 May 2025 at 16:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Document support for the I2C Bus Interface (RIIC) found on the Renesas
> RZ/N2H (R9A09G087) SoC. The RIIC IP on this SoC is identical to that on
> the RZ/T2H SoC so `renesas,riic-r9a09g077` will be used as a fallback
> compatible.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/6] i2c: riic: Pass IRQ desc array as part of OF data

[Geert Uytterhoeven]

On Fri, 30 May 2025 at 16:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> In preparation for adding support for Renesas RZ/T2H and RZ/N2H SoCs,
> which feature a combined error interrupt instead of individual error
> interrupts per condition, update the driver to support configurable IRQ
> layouts via OF data.
>
> Introduce a new `irqs` field and `num_irqs` count in `riic_of_data` to
> allow future SoCs to provide a custom IRQ layout. This patch is a
> non-functional change for existing SoCs and maintains compatibility with
> the current `riic_irqs` array.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

No regressions on RZ/A1H, RZ/A2M, and RZ/Five, so
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 5/6] i2c: riic: Move generic compatible string to end of array

[Geert Uytterhoeven]

On Fri, 30 May 2025 at 16:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Reorder the entry in `riic_i2c_dt_ids` to place the generic compatible
> string `renesas,riic-rz` at the end of the array, following the
> convention used in other Renesas drivers.
>
> Also, drop the unnecessary comma after the sentinel entry, as it is
> not needed.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/6] i2c: riic: Pass IRQ desc array as part of OF data

[Geert Uytterhoeven]

Hi Prabhakar,

On Fri, 30 May 2025 at 16:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> In preparation for adding support for Renesas RZ/T2H and RZ/N2H SoCs,
> which feature a combined error interrupt instead of individual error
> interrupts per condition, update the driver to support configurable IRQ
> layouts via OF data.
>
> Introduce a new `irqs` field and `num_irqs` count in `riic_of_data` to
> allow future SoCs to provide a custom IRQ layout. This patch is a
> non-functional change for existing SoCs and maintains compatibility with
> the current `riic_irqs` array.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  drivers/i2c/busses/i2c-riic.c | 22 ++++++++++++++++------
>  1 file changed, 16 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
> index 23375f7fe3ad..4950b790cfe7 100644
> --- a/drivers/i2c/busses/i2c-riic.c
> +++ b/drivers/i2c/busses/i2c-riic.c
> @@ -102,6 +102,8 @@ enum riic_reg_list {
>
>  struct riic_of_data {
>         const u8 *regs;
> +       const struct riic_irq_desc *irqs;
> +       u8 num_irqs;
>         bool fast_mode_plus;
>  };
>

> @@ -607,10 +611,14 @@ static const u8 riic_rz_a_regs[RIIC_REG_END] = {
>  static const struct riic_of_data riic_rz_a_info = {
>         .regs = riic_rz_a_regs,
>         .fast_mode_plus = true,
> +       .irqs = riic_irqs,
> +       .num_irqs = ARRAY_SIZE(riic_irqs),

Nit: Perhaps initialize the members in the order of declaration?

>  };
>
>  static const struct riic_of_data riic_rz_a1h_info = {
>         .regs = riic_rz_a_regs,
> +       .irqs = riic_irqs,
> +       .num_irqs = ARRAY_SIZE(riic_irqs),
>  };
>
>  static const u8 riic_rz_v2h_regs[RIIC_REG_END] = {
> @@ -631,6 +639,8 @@ static const u8 riic_rz_v2h_regs[RIIC_REG_END] = {
>  static const struct riic_of_data riic_rz_v2h_info = {
>         .regs = riic_rz_v2h_regs,
>         .fast_mode_plus = true,
> +       .irqs = riic_irqs,
> +       .num_irqs = ARRAY_SIZE(riic_irqs),

Likewise.

>  };
>
>  static int riic_i2c_suspend(struct device *dev)

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 6/6] i2c: riic: Add support for RZ/T2H SoC

[Geert Uytterhoeven]

Hi Prabhakar,

On Fri, 30 May 2025 at 16:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add support for the Renesas RZ/T2H (R9A09G077) SoC, which features a
> different interrupt layout for the RIIC controller. Unlike other SoCs
> with individual error interrupts, RZ/T2H uses a combined error interrupt
> (EEI).
>
> Introduce a new IRQ descriptor table for RZ/T2H, along with a custom
> ISR (`riic_eei_isr`) to handle STOP and NACK detection from the shared
> interrupt.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/i2c/busses/i2c-riic.c
> +++ b/drivers/i2c/busses/i2c-riic.c
> @@ -326,6 +327,19 @@ static irqreturn_t riic_stop_isr(int irq, void *data)
>         return IRQ_HANDLED;
>  }
>
> +static irqreturn_t riic_eei_isr(int irq, void *data)
> +{
> +       u8 icsr2 = riic_readb(data, RIIC_ICSR2);
> +
> +       if (icsr2 & ICSR2_NACKF)
> +               return riic_tend_isr(irq, data);
> +
> +       if (icsr2 & ICSR2_STOP)
> +               return riic_stop_isr(irq, data);

Just wondering: can both ICSR2_NACKF and ICSR2_STOP be set?
As riic_tend_isr() clears only ICSR2_NACKF, while riic_stop_isr()
clears all bits, the two calls could be chained, if needed.

> +
> +       return IRQ_NONE;
> +}
> +
>  static u32 riic_func(struct i2c_adapter *adap)
>  {
>         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/6] dt-bindings: i2c: renesas,riic: Document RZ/T2H support

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Fri, Jun 6, 2025 at 2:21 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Fri, 30 May 2025 at 16:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Document support for the I2C Bus Interface (RIIC) found on the Renesas
> > RZ/T2H (R9A09G077) SoC. The RIIC IP on this SoC is similar to that on
> > the RZ/V2H(P) SoC but supports fewer interrupts, lacks FM+ support and
> > does not require resets. Due to these differences, add a new compatible
> > string `renesas,riic-r9a09g077` for the RZ/T2H SoC.
> >
> > Unlike earlier SoCs that use eight distinct interrupts, the RZ/T2H uses
> > only four, including a combined error/event interrupt. Update the binding
> > schema to reflect this interrupt layout and skip the `resets` property
> > check, as it is not required on these SoCs.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> > +++ b/Documentation/devicetree/bindings/i2c/renesas,riic.yaml
> > @@ -29,32 +29,46 @@ properties:
> >                - renesas,riic-r9a09g056   # RZ/V2N
> >            - const: renesas,riic-r9a09g057   # RZ/V2H(P)
> >
> > -      - const: renesas,riic-r9a09g057   # RZ/V2H(P)
> > +      - enum:
> > +          - renesas,riic-r9a09g057   # RZ/V2H(P)
> > +          - renesas,riic-r9a09g077   # RZ/T2H
> >
> >    reg:
> >      maxItems: 1
> >
> >    interrupts:
> > -    items:
> > -      - description: Transmit End Interrupt
> > -      - description: Receive Data Full Interrupt
> > -      - description: Transmit Data Empty Interrupt
> > -      - description: Stop Condition Detection Interrupt
> > -      - description: Start Condition Detection Interrupt
> > -      - description: NACK Reception Interrupt
> > -      - description: Arbitration-Lost Interrupt
> > -      - description: Timeout Interrupt
> > +    oneOf:
> > +      - items:
> > +          - description: Transmit End Interrupt
> > +          - description: Receive Data Full Interrupt
> > +          - description: Transmit Data Empty Interrupt
> > +          - description: Stop Condition Detection Interrupt
> > +          - description: Start Condition Detection Interrupt
> > +          - description: NACK Reception Interrupt
> > +          - description: Arbitration-Lost Interrupt
> > +          - description: Timeout Interrupt
> > +      - items:
> > +          - description: Transmit End Interrupt
> > +          - description: Receive Data Full Interrupt
> > +          - description: Transmit Data Empty Interrupt
> > +          - description: Transmit error or event Interrupt
>
> Nit: the documentation calls it "Transfer error or event generation".
>
Agreed I will update it to `Transmit Error Or Event Generation`.

> >
> >    interrupt-names:
> > -    items:
> > -      - const: tei
> > -      - const: ri
> > -      - const: ti
> > -      - const: spi
> > -      - const: sti
> > -      - const: naki
> > -      - const: ali
> > -      - const: tmoi
> > +    oneOf:
> > +      - items:
> > +          - const: tei
> > +          - const: ri
> > +          - const: ti
> > +          - const: spi
> > +          - const: sti
> > +          - const: naki
> > +          - const: ali
> > +          - const: tmoi
> > +      - items:
> > +          - const: tei
> > +          - const: ri
> > +          - const: ti
>
> Given you have a new set of names, perhaps "rxi" and "txi",
> to match the documentation?
>
Ok.

> > +          - const: eei
>
> Perhaps use the order from the documentation: eei, rxi, txi, tei?
>
Agreed, I will update it as mentioned above,

- items:
- const: eei
- const: rxi
- const: txi
- const: tei

Cheers,
Prabhakar

Re: [PATCH 4/6] i2c: riic: Pass IRQ desc array as part of OF data

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Fri, Jun 6, 2025 at 2:26 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Fri, 30 May 2025 at 16:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > In preparation for adding support for Renesas RZ/T2H and RZ/N2H SoCs,
> > which feature a combined error interrupt instead of individual error
> > interrupts per condition, update the driver to support configurable IRQ
> > layouts via OF data.
> >
> > Introduce a new `irqs` field and `num_irqs` count in `riic_of_data` to
> > allow future SoCs to provide a custom IRQ layout. This patch is a
> > non-functional change for existing SoCs and maintains compatibility with
> > the current `riic_irqs` array.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> >  drivers/i2c/busses/i2c-riic.c | 22 ++++++++++++++++------
> >  1 file changed, 16 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c
> > index 23375f7fe3ad..4950b790cfe7 100644
> > --- a/drivers/i2c/busses/i2c-riic.c
> > +++ b/drivers/i2c/busses/i2c-riic.c
> > @@ -102,6 +102,8 @@ enum riic_reg_list {
> >
> >  struct riic_of_data {
> >         const u8 *regs;
> > +       const struct riic_irq_desc *irqs;
> > +       u8 num_irqs;
> >         bool fast_mode_plus;
> >  };
> >
>
> > @@ -607,10 +611,14 @@ static const u8 riic_rz_a_regs[RIIC_REG_END] = {
> >  static const struct riic_of_data riic_rz_a_info = {
> >         .regs = riic_rz_a_regs,
> >         .fast_mode_plus = true,
> > +       .irqs = riic_irqs,
> > +       .num_irqs = ARRAY_SIZE(riic_irqs),
>
> Nit: Perhaps initialize the members in the order of declaration?
>
Ok, I will fix this in the next version (and below too).

Cheers,
Prabhakar

Re: [PATCH 6/6] i2c: riic: Add support for RZ/T2H SoC

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Fri, Jun 6, 2025 at 2:37 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Fri, 30 May 2025 at 16:31, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add support for the Renesas RZ/T2H (R9A09G077) SoC, which features a
> > different interrupt layout for the RIIC controller. Unlike other SoCs
> > with individual error interrupts, RZ/T2H uses a combined error interrupt
> > (EEI).
> >
> > Introduce a new IRQ descriptor table for RZ/T2H, along with a custom
> > ISR (`riic_eei_isr`) to handle STOP and NACK detection from the shared
> > interrupt.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/i2c/busses/i2c-riic.c
> > +++ b/drivers/i2c/busses/i2c-riic.c
> > @@ -326,6 +327,19 @@ static irqreturn_t riic_stop_isr(int irq, void *data)
> >         return IRQ_HANDLED;
> >  }
> >
> > +static irqreturn_t riic_eei_isr(int irq, void *data)
> > +{
> > +       u8 icsr2 = riic_readb(data, RIIC_ICSR2);
> > +
> > +       if (icsr2 & ICSR2_NACKF)
> > +               return riic_tend_isr(irq, data);
> > +
> > +       if (icsr2 & ICSR2_STOP)
> > +               return riic_stop_isr(irq, data);
>
> Just wondering: can both ICSR2_NACKF and ICSR2_STOP be set?
> As riic_tend_isr() clears only ICSR2_NACKF, while riic_stop_isr()
> clears all bits, the two calls could be chained, if needed.
>
In the normal working scenario when verified both these bits were
never set together, hence I took this path.

Cheers,
Prabhakar