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From: Drew Fustini <drew@pdp7.com>
To: Yao Zi <ziyao@disroot.org>
Cc: Rick Chen <rick@andestech.com>, Leo <ycliang@andestech.com>,
	Tom Rini <trini@konsulko.com>, Wei Fu <wefu@redhat.com>,
	Yixun Lan <dlan@gentoo.org>,
	Maksim Kiselev <bigunclemax@gmail.com>,
	Jaehoon Chung <jh80.chung@samsung.com>,
	Simon Glass <sjg@chromium.org>,
	Heinrich Schuchardt <xypron.glpk@gmx.de>,
	Ilias Apalodimas <ilias.apalodimas@linaro.org>,
	Neha Malcom Francis <n-francis@ti.com>,
	Jayesh Choudhary <j-choudhary@ti.com>,
	Wadim Egorov <w.egorov@phytec.de>,
	Vaishnav Achath <vaishnav.a@ti.com>, Andrew Davis <afd@ti.com>,
	Chia-Wei Wang <chiawei_wang@aspeedtech.com>,
	u-boot@lists.denx.de, Han Gao <rabenda.cn@gmail.com>,
	Han Gao <gaohan@iscas.ac.cn>
Subject: Re: [PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520
Date: Sat, 24 May 2025 12:16:49 -0700	[thread overview]
Message-ID: <aDIbIRcPQpcVU95p@x1> (raw)
In-Reply-To: <20250426165704.35523-5-ziyao@disroot.org>

On Sat, Apr 26, 2025 at 04:56:58PM +0000, Yao Zi wrote:
> This patch cleans the vendor code of DDR initialization up, converts the
> driver to fit in DM framework and use a firmware[1] packaged by binman to
> ship PHY configuration.
> 
> Currently the driver is only capable of initializing the controller to
> work with dual-rank 3733MHz LPDDR4, which is shipped by 16GiB variants
> of LicheePi 4A boards and I could test with. Support for other
> configurations could be easily added later.

Thank you for this patch series. I only have the 8GB LPi4a. Do you have
any suggestions for how I can get that working?

Here is existing output at boot:

-----------------------------------------------
U-Boot SPL 2020.01-g55b713fa (Jan 12 2024 - 02:17:34 +0000)
FM[1] lpddr4x dualrank freq=3733 64bit dbi_off=n sdram init
ddr initialized, jump to uboot
it worksimage has no header

U-Boot 2020.01-g55b713fa (Jan 12 2024 - 02:17:34 +0000)

CPU:   rv64imafdcvsu
Model: T-HEAD c910 light
DRAM:  8 GiB
-----------------------------------------------

Thanks,
Drew

  parent reply	other threads:[~2025-05-24 21:59 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-26 16:56 [PATCH 00/10] Initial SPL support for T-Head TH1520 SoC Yao Zi
2025-04-26 16:56 ` [PATCH 01/10] riscv: lib: Split out support for T-Head cache management operations Yao Zi
2025-05-12  9:56   ` Leo Liang
2025-04-26 16:56 ` [PATCH 02/10] riscv: dts: th1520: Add clock-frequency for UART0 Yao Zi
2025-05-12  9:57   ` Leo Liang
2025-05-12 11:53     ` e
2025-05-13  4:06       ` Yao Zi
2025-04-26 16:56 ` [PATCH 03/10] riscv: cpu: Add TH1520 CPU support Yao Zi
2025-05-12  9:59   ` Leo Liang
2025-04-26 16:56 ` [PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520 Yao Zi
2025-04-26 17:09   ` Yao Zi
2025-05-12 17:55     ` Leo Liang
2025-05-12 17:47   ` Leo Liang
2025-05-24 19:16   ` Drew Fustini [this message]
2025-04-26 17:00 ` Yao Zi
2025-04-26 17:00 ` [PATCH 05/10] riscv: dts: th1520: Preserve necessary devices for SPL Yao Zi
2025-05-12 18:02   ` Leo Liang
2025-04-26 17:00 ` [PATCH 06/10] riscv: dts: lichee-module-4a: Preserve memory node " Yao Zi
2025-05-12 18:03   ` Leo Liang
2025-04-26 17:00 ` [PATCH 07/10] riscv: dts: th1520: Add DRAM controller Yao Zi
2025-05-12 18:04   ` Leo Liang
2025-04-26 17:00 ` [PATCH 08/10] riscv: dts: th1520: Add binman configuration Yao Zi
2025-05-12 18:04   ` Leo Liang
2025-04-26 17:03 ` [PATCH 09/10] board: thead: licheepi4a: Enable SPL support Yao Zi
2025-05-12 18:05   ` Leo Liang
2025-04-26 17:03 ` [PATCH 10/10] doc: thead: lpi4a: Update documentation Yao Zi
2025-05-12 18:06   ` Leo Liang

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