[PATCH i-g-t v3 00/11] Improve mem-copy/mem-set lib and tests

[PATCH i-g-t v3 00/11] Improve mem-copy/mem-set lib and tests

[Zbigniew Kempczyński]

There were missing page and matrix tests in mem-copy. Apart of
that batch emission code allowed to set invalid bits in the command.
Fix all of these.

Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Francois Dugast <francois.dugast@intel.com>

Zbigniew Kempczyński (11):
  lib/intel_cmds_info: rename M to TYPE in blt_memop_type
  lib/intel_blt: separate mem-copy and mem-set
  lib/intel_cmds_info: add blt_memop_mode (byte/page)
  lib/intel_blt: add emit batchbuffer end
  lib/intel_blt: use struct instead of inline coding
  tests/xe_copy_basic: replace size to rect which keeps objects geometry
  tests/xe_copy_basic: add testcase with large buffer size
  tests/xe_copy_basic: add subtest to verify mem-copy in pages
  lib/intel_blt: add support for matrix mem-copy
  tests/xe_copy_basic: add mem-copy matrix subtests
  lib/intel_blt: add mem-copy debug facility

 lib/intel_blt.c              | 267 +++++++++++++++++++++++++++++++----
 lib/intel_blt.h              |  27 +++-
 lib/intel_cmds_info.c        |   8 +-
 lib/intel_cmds_info.h        |  21 ++-
 tests/intel/xe_copy_basic.c  | 191 +++++++++++++++++++++----
 tests/intel/xe_render_copy.c |   4 +-
 tests/intel/xe_spin_batch.c  |   6 +-
 7 files changed, 445 insertions(+), 79 deletions(-)

-- 
2.43.0

[PATCH i-g-t v3 01/11] lib/intel_cmds_info: rename M to TYPE in blt_memop_type

[Zbigniew Kempczyński]

Documentation separates type and mode in mem-copy so rename prefix
to avoid ambiguity.

Cc: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Francois Dugast <francois.dugast@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_blt.c              |  2 +-
 lib/intel_cmds_info.c        |  8 ++++----
 lib/intel_cmds_info.h        | 10 ++++++++--
 tests/intel/xe_copy_basic.c  |  6 +++---
 tests/intel/xe_render_copy.c |  4 ++--
 tests/intel/xe_spin_batch.c  |  4 ++--
 6 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index 7010d3ff7d..33efbf1038 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -1827,7 +1827,7 @@ static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_data *
 					  0, mem->dst.pat_index);
 
 	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
-	optype = mem->src.type == M_MATRIX ? 1 << 17 : 0;
+	optype = mem->src.type == TYPE_MATRIX ? 1 << 17 : 0;
 
 	i = 0;
 	batch[i++] = MEM_COPY_CMD | optype;
diff --git a/lib/intel_cmds_info.c b/lib/intel_cmds_info.c
index d581edb6eb..3bd5eab653 100644
--- a/lib/intel_cmds_info.c
+++ b/lib/intel_cmds_info.c
@@ -74,13 +74,13 @@ static const struct blt_cmd_info
 
 static const struct blt_cmd_info
 		pvc_mem_copy = BLT_INFO(MEM_COPY,
-					BIT(M_LINEAR) |
-					BIT(M_MATRIX));
+					BIT(TYPE_LINEAR) |
+					BIT(TYPE_MATRIX));
 
 static const struct blt_cmd_info
 		pvc_mem_set = BLT_INFO(MEM_SET,
-				       BIT(M_LINEAR) |
-				       BIT(M_MATRIX));
+				       BIT(TYPE_LINEAR) |
+				       BIT(TYPE_MATRIX));
 
 static const struct blt_cmd_info
 		pre_gen6_xy_color_blt = BLT_INFO(XY_COLOR_BLT, TILE_L_X);
diff --git a/lib/intel_cmds_info.h b/lib/intel_cmds_info.h
index 7960e0412e..88ba892645 100644
--- a/lib/intel_cmds_info.h
+++ b/lib/intel_cmds_info.h
@@ -19,9 +19,15 @@ enum blt_tiling_type {
 	__BLT_MAX_TILING
 };
 
+/**
+ * enum blt_memop_type - memory operation type for mem-copy and mem-set.
+ *
+ * Mem-copy and mem-set support two types of object copy/fill -
+ * linear (1D buffer) and matrix (2D buffer).
+ */
 enum blt_memop_type {
-	M_LINEAR,
-	M_MATRIX,
+	TYPE_LINEAR,
+	TYPE_MATRIX,
 };
 
 enum blt_cmd_type {
diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
index d4300b85c0..a9e9bd2359 100644
--- a/tests/intel/xe_copy_basic.c
+++ b/tests/intel/xe_copy_basic.c
@@ -58,10 +58,10 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
 
 	blt_mem_init(fd, &mem);
 	blt_set_mem_object(&mem.src, src_handle, size, width, width, height,
-			   region, src_mocs, DEFAULT_PAT_INDEX, M_LINEAR,
+			   region, src_mocs, DEFAULT_PAT_INDEX, TYPE_LINEAR,
 			   COMPRESSION_DISABLED);
 	blt_set_mem_object(&mem.dst, dst_handle, size, width, width, height,
-			   region, dst_mocs, DEFAULT_PAT_INDEX, M_LINEAR,
+			   region, dst_mocs, DEFAULT_PAT_INDEX, TYPE_LINEAR,
 			   COMPRESSION_DISABLED);
 	mem.src.ptr = xe_bo_map(fd, src_handle, size);
 	mem.dst.ptr = xe_bo_map(fd, dst_handle, size);
@@ -109,7 +109,7 @@ mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx, uint32_t size,
 	bb = xe_bo_create(fd, 0, bb_size, region, 0);
 	blt_mem_init(fd, &mem);
 	blt_set_mem_object(&mem.dst, dst_handle, size, width, width, height, region,
-			   dst_mocs, DEFAULT_PAT_INDEX, M_LINEAR, COMPRESSION_DISABLED);
+			   dst_mocs, DEFAULT_PAT_INDEX, TYPE_LINEAR, COMPRESSION_DISABLED);
 	mem.dst.ptr = xe_bo_map(fd, dst_handle, size);
 	blt_set_batch(&mem.bb, bb, bb_size, region);
 	blt_mem_set(fd, ctx, NULL, ahnd, &mem, fill_data);
diff --git a/tests/intel/xe_render_copy.c b/tests/intel/xe_render_copy.c
index 60cd0fb457..7ebde01c44 100644
--- a/tests/intel/xe_render_copy.c
+++ b/tests/intel/xe_render_copy.c
@@ -470,10 +470,10 @@ static void mem_copy_busy(int fd, struct drm_xe_engine_class_instance *hwe, uint
 	dst_handle = xe_bo_create(fd, 0, copy_size, region, 0);
 	blt_set_mem_object(mem_copy.src, src_handle, copy_size, width, width, height, region,
 			   intel_get_uc_mocs_index(fd), DEFAULT_PAT_INDEX,
-			   M_LINEAR, COMPRESSION_DISABLED);
+			   TYPE_LINEAR, COMPRESSION_DISABLED);
 	blt_set_mem_object(mem_copy.dst, dst_handle, copy_size, width, width, height, region,
 			   intel_get_uc_mocs_index(fd), DEFAULT_PAT_INDEX,
-			   M_LINEAR, COMPRESSION_DISABLED);
+			   TYPE_LINEAR, COMPRESSION_DISABLED);
 	mem_copy.src->ptr = xe_bo_map(fd, src_handle, copy_size);
 	mem_copy.dst->ptr = xe_bo_map(fd, dst_handle, copy_size);
 	mem_copy.src_offset = get_offset_pat_index(ahnd, mem_copy.src->handle,
diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c
index 4fff34a092..06c5f9d3f9 100644
--- a/tests/intel/xe_spin_batch.c
+++ b/tests/intel/xe_spin_batch.c
@@ -351,10 +351,10 @@ static void xe_spin_mem_copy_region(int fd, struct drm_xe_engine_class_instance
 	dst_handle = xe_bo_create(fd, 0, copy_size, region, 0);
 	blt_set_mem_object(mem_copy.src, src_handle, copy_size, width, width, height, region,
 			   intel_get_uc_mocs_index(fd), DEFAULT_PAT_INDEX,
-			   M_LINEAR, COMPRESSION_DISABLED);
+			   TYPE_LINEAR, COMPRESSION_DISABLED);
 	blt_set_mem_object(mem_copy.dst, dst_handle, copy_size, width, width, height, region,
 			   intel_get_uc_mocs_index(fd), DEFAULT_PAT_INDEX,
-			   M_LINEAR, COMPRESSION_DISABLED);
+			   TYPE_LINEAR, COMPRESSION_DISABLED);
 	mem_copy.src->ptr = xe_bo_map(fd, src_handle, copy_size);
 	mem_copy.dst->ptr = xe_bo_map(fd, dst_handle, copy_size);
 	mem_copy.src_offset = get_offset_pat_index(ahnd, mem_copy.src->handle,
-- 
2.43.0

[PATCH i-g-t v3 02/11] lib/intel_blt: separate mem-copy and mem-set

[Zbigniew Kempczyński]

Move operation type (linear or matrix) from buffer to command part.
Mem-copy additionally uses mode (byte or page) so separate them
for extending them independently.

Cc: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Francois Dugast <francois.dugast@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_blt.c              | 39 +++++++++++++++++++++++++++---------
 lib/intel_blt.h              | 24 ++++++++++++++++------
 tests/intel/xe_copy_basic.c  | 16 +++++++--------
 tests/intel/xe_render_copy.c |  4 ++--
 tests/intel/xe_spin_batch.c  |  6 ++----
 5 files changed, 59 insertions(+), 30 deletions(-)

diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index 33efbf1038..4c90d157c9 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -1799,22 +1799,25 @@ int blt_fast_copy(int fd,
 }
 
 /**
- * blt_mem_init:
+ * blt_mem_copy_init:
  * @fd: drm fd
  * @mem: structure for initialization
+ * @copy_type: linear or matrix
  *
  * Function is zeroing @mem and sets fd and driver fields (INTEL_DRIVER_I915 or
  * INTEL_DRIVER_XE).
  */
-void blt_mem_init(int fd, struct blt_mem_data *mem)
+void blt_mem_copy_init(int fd, struct blt_mem_copy_data *mem,
+		       enum blt_memop_type copy_type)
 {
 	memset(mem, 0, sizeof(*mem));
 
 	mem->fd = fd;
 	mem->driver = get_intel_driver(fd);
+	mem->copy_type = copy_type;
 }
 
-static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_data *mem)
+static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_copy_data *mem)
 {
 	uint64_t dst_offset, src_offset;
 	int i;
@@ -1827,7 +1830,7 @@ static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_data *
 					  0, mem->dst.pat_index);
 
 	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
-	optype = mem->src.type == TYPE_MATRIX ? 1 << 17 : 0;
+	optype = mem->copy_type == TYPE_MATRIX ? 1 << 17 : 0;
 
 	i = 0;
 	batch[i++] = MEM_COPY_CMD | optype;
@@ -1861,7 +1864,7 @@ static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_data *
 int blt_mem_copy(int fd, const intel_ctx_t *ctx,
 		 const struct intel_execution_engine2 *e,
 		 uint64_t ahnd,
-		 const struct blt_mem_data *mem)
+		 const struct blt_mem_copy_data *mem)
 {
 	struct drm_i915_gem_execbuffer2 execbuf = {};
 	struct drm_i915_gem_exec_object2 obj[3] = {};
@@ -1902,7 +1905,26 @@ int blt_mem_copy(int fd, const intel_ctx_t *ctx,
 	return ret;
 }
 
-static void emit_blt_mem_set(int fd, uint64_t ahnd, const struct blt_mem_data *mem,
+/**
+ * blt_mem_set_init:
+ * @fd: drm fd
+ * @mem: structure for initialization
+ *
+ * Function is zeroing @mem and sets fd and driver fields (INTEL_DRIVER_I915 or
+ * INTEL_DRIVER_XE).
+ */
+void blt_mem_set_init(int fd, struct blt_mem_set_data *mem,
+		      enum blt_memop_type fill_type)
+{
+	memset(mem, 0, sizeof(*mem));
+
+	mem->fd = fd;
+	mem->driver = get_intel_driver(fd);
+	mem->fill_type = fill_type;
+}
+
+static void emit_blt_mem_set(int fd, uint64_t ahnd,
+			     const struct blt_mem_set_data *mem,
 			     uint8_t fill_data)
 {
 	uint64_t dst_offset;
@@ -1945,7 +1967,7 @@ static void emit_blt_mem_set(int fd, uint64_t ahnd, const struct blt_mem_data *m
 int blt_mem_set(int fd, const intel_ctx_t *ctx,
 		const struct intel_execution_engine2 *e,
 		uint64_t ahnd,
-		const struct blt_mem_data *mem,
+		const struct blt_mem_set_data *mem,
 		uint8_t fill_data)
 {
 	struct drm_i915_gem_execbuffer2 execbuf = {};
@@ -2101,14 +2123,13 @@ void blt_set_mem_object(struct blt_mem_object *obj,
 			uint32_t handle, uint64_t size, uint32_t pitch,
 			uint32_t width, uint32_t height, uint32_t region,
 			uint8_t mocs_index, uint8_t pat_index,
-			enum blt_memop_type type, enum blt_compression compression)
+			enum blt_compression compression)
 {
 	obj->handle = handle;
 	obj->region = region;
 	obj->size = size;
 	obj->mocs_index = mocs_index;
 	obj->pat_index = pat_index;
-	obj->type = type;
 	obj->compression = compression;
 	obj->width = width;
 	obj->height = height;
diff --git a/lib/intel_blt.h b/lib/intel_blt.h
index 4bae0b47b3..9efa799881 100644
--- a/lib/intel_blt.h
+++ b/lib/intel_blt.h
@@ -101,7 +101,6 @@ struct blt_mem_object {
 	uint64_t size;
 	uint8_t mocs_index;
 	uint8_t pat_index;
-	enum blt_memop_type type;
 	enum blt_compression compression;
 	uint32_t width;
 	uint32_t height;
@@ -128,14 +127,23 @@ struct blt_copy_data {
 	bool print_bb;
 };
 
-struct blt_mem_data {
+struct blt_mem_copy_data {
 	int fd;
 	enum intel_driver driver;
+	enum blt_memop_type copy_type;
 	struct blt_mem_object src;
 	struct blt_mem_object dst;
 	struct blt_copy_batch bb;
 };
 
+struct blt_mem_set_data {
+	int fd;
+	enum intel_driver driver;
+	enum blt_memop_type fill_type;
+	struct blt_mem_object dst;
+	struct blt_copy_batch bb;
+};
+
 enum blt_surface_type {
 	SURFACE_TYPE_1D,
 	SURFACE_TYPE_2D,
@@ -265,16 +273,20 @@ int blt_fast_copy(int fd,
 		  uint64_t ahnd,
 		  const struct blt_copy_data *blt);
 
-void blt_mem_init(int fd, struct blt_mem_data *mem);
+void blt_mem_copy_init(int fd, struct blt_mem_copy_data *mem,
+		       enum blt_memop_type copy_type);
+
+void blt_mem_set_init(int fd, struct blt_mem_set_data *mem,
+		      enum blt_memop_type fill_type);
 
 int blt_mem_copy(int fd, const intel_ctx_t *ctx,
 			 const struct intel_execution_engine2 *e,
 			 uint64_t ahnd,
-			 const struct blt_mem_data *mem);
+			 const struct blt_mem_copy_data *mem);
 
 int blt_mem_set(int fd, const intel_ctx_t *ctx,
 			const struct intel_execution_engine2 *e, uint64_t ahnd,
-			const struct blt_mem_data *mem, uint8_t fill_data);
+			const struct blt_mem_set_data *mem, uint8_t fill_data);
 
 void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
 		  int16_t x1, int16_t y1, int16_t x2, int16_t y2,
@@ -302,7 +314,7 @@ void blt_set_mem_object(struct blt_mem_object *obj,
 			uint32_t handle, uint64_t size, uint32_t pitch,
 			uint32_t width, uint32_t height, uint32_t region,
 			uint8_t mocs_index, uint8_t pat_index,
-			enum blt_memop_type type, enum blt_compression compression);
+			enum blt_compression compression);
 
 void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
 			uint8_t compression_format,
diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
index a9e9bd2359..5681d4d6ab 100644
--- a/tests/intel/xe_copy_basic.c
+++ b/tests/intel/xe_copy_basic.c
@@ -44,7 +44,7 @@ static void
 mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ctx,
 	 uint32_t size, uint32_t width, uint32_t height, uint32_t region)
 {
-	struct blt_mem_data mem = {};
+	struct blt_mem_copy_data mem = {};
 	uint64_t bb_size = xe_bb_size(fd, SZ_4K);
 	uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0,
 						  INTEL_ALLOCATOR_SIMPLE,
@@ -56,13 +56,11 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
 
 	bb = xe_bo_create(fd, 0, bb_size, region, 0);
 
-	blt_mem_init(fd, &mem);
+	blt_mem_copy_init(fd, &mem, TYPE_LINEAR);
 	blt_set_mem_object(&mem.src, src_handle, size, width, width, height,
-			   region, src_mocs, DEFAULT_PAT_INDEX, TYPE_LINEAR,
-			   COMPRESSION_DISABLED);
+			   region, src_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
 	blt_set_mem_object(&mem.dst, dst_handle, size, width, width, height,
-			   region, dst_mocs, DEFAULT_PAT_INDEX, TYPE_LINEAR,
-			   COMPRESSION_DISABLED);
+			   region, dst_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
 	mem.src.ptr = xe_bo_map(fd, src_handle, size);
 	mem.dst.ptr = xe_bo_map(fd, dst_handle, size);
 
@@ -97,7 +95,7 @@ static void
 mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx, uint32_t size,
 	uint32_t width, uint32_t height, uint8_t fill_data, uint32_t region)
 {
-	struct blt_mem_data mem = {};
+	struct blt_mem_set_data mem = {};
 	uint64_t bb_size = xe_bb_size(fd, SZ_4K);
 	uint64_t ahnd = intel_allocator_open_full(fd, ctx->vm, 0, 0,
 						  INTEL_ALLOCATOR_SIMPLE,
@@ -107,9 +105,9 @@ mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx, uint32_t size,
 	uint8_t *result;
 
 	bb = xe_bo_create(fd, 0, bb_size, region, 0);
-	blt_mem_init(fd, &mem);
+	blt_mem_set_init(fd, &mem, TYPE_LINEAR);
 	blt_set_mem_object(&mem.dst, dst_handle, size, width, width, height, region,
-			   dst_mocs, DEFAULT_PAT_INDEX, TYPE_LINEAR, COMPRESSION_DISABLED);
+			   dst_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
 	mem.dst.ptr = xe_bo_map(fd, dst_handle, size);
 	blt_set_batch(&mem.bb, bb, bb_size, region);
 	blt_mem_set(fd, ctx, NULL, ahnd, &mem, fill_data);
diff --git a/tests/intel/xe_render_copy.c b/tests/intel/xe_render_copy.c
index 7ebde01c44..6b5cb69684 100644
--- a/tests/intel/xe_render_copy.c
+++ b/tests/intel/xe_render_copy.c
@@ -470,10 +470,10 @@ static void mem_copy_busy(int fd, struct drm_xe_engine_class_instance *hwe, uint
 	dst_handle = xe_bo_create(fd, 0, copy_size, region, 0);
 	blt_set_mem_object(mem_copy.src, src_handle, copy_size, width, width, height, region,
 			   intel_get_uc_mocs_index(fd), DEFAULT_PAT_INDEX,
-			   TYPE_LINEAR, COMPRESSION_DISABLED);
+			   COMPRESSION_DISABLED);
 	blt_set_mem_object(mem_copy.dst, dst_handle, copy_size, width, width, height, region,
 			   intel_get_uc_mocs_index(fd), DEFAULT_PAT_INDEX,
-			   TYPE_LINEAR, COMPRESSION_DISABLED);
+			   COMPRESSION_DISABLED);
 	mem_copy.src->ptr = xe_bo_map(fd, src_handle, copy_size);
 	mem_copy.dst->ptr = xe_bo_map(fd, dst_handle, copy_size);
 	mem_copy.src_offset = get_offset_pat_index(ahnd, mem_copy.src->handle,
diff --git a/tests/intel/xe_spin_batch.c b/tests/intel/xe_spin_batch.c
index 06c5f9d3f9..21b08ba067 100644
--- a/tests/intel/xe_spin_batch.c
+++ b/tests/intel/xe_spin_batch.c
@@ -350,11 +350,9 @@ static void xe_spin_mem_copy_region(int fd, struct drm_xe_engine_class_instance
 	src_handle = xe_bo_create(fd, 0, copy_size, region, 0);
 	dst_handle = xe_bo_create(fd, 0, copy_size, region, 0);
 	blt_set_mem_object(mem_copy.src, src_handle, copy_size, width, width, height, region,
-			   intel_get_uc_mocs_index(fd), DEFAULT_PAT_INDEX,
-			   TYPE_LINEAR, COMPRESSION_DISABLED);
+			   intel_get_uc_mocs_index(fd), DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
 	blt_set_mem_object(mem_copy.dst, dst_handle, copy_size, width, width, height, region,
-			   intel_get_uc_mocs_index(fd), DEFAULT_PAT_INDEX,
-			   TYPE_LINEAR, COMPRESSION_DISABLED);
+			   intel_get_uc_mocs_index(fd), DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
 	mem_copy.src->ptr = xe_bo_map(fd, src_handle, copy_size);
 	mem_copy.dst->ptr = xe_bo_map(fd, dst_handle, copy_size);
 	mem_copy.src_offset = get_offset_pat_index(ahnd, mem_copy.src->handle,
-- 
2.43.0

[PATCH i-g-t v3 03/11] lib/intel_cmds_info: add blt_memop_mode (byte/page)

[Zbigniew Kempczyński]

Add 'mode' field for further extending in tests. It is used for
mem-copy linear type which supports copy mode in bytes or pages.

Cc: Francois Dugast <francois.dugast@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_blt.c             |  3 +++
 lib/intel_blt.h             |  2 ++
 lib/intel_cmds_info.h       | 11 +++++++++++
 tests/intel/xe_copy_basic.c |  2 +-
 4 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index 4c90d157c9..6bfaf09a2b 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -1802,18 +1802,21 @@ int blt_fast_copy(int fd,
  * blt_mem_copy_init:
  * @fd: drm fd
  * @mem: structure for initialization
+ * @mode: copy mode - byte or page (256B)
  * @copy_type: linear or matrix
  *
  * Function is zeroing @mem and sets fd and driver fields (INTEL_DRIVER_I915 or
  * INTEL_DRIVER_XE).
  */
 void blt_mem_copy_init(int fd, struct blt_mem_copy_data *mem,
+		       enum blt_memop_mode mode,
 		       enum blt_memop_type copy_type)
 {
 	memset(mem, 0, sizeof(*mem));
 
 	mem->fd = fd;
 	mem->driver = get_intel_driver(fd);
+	mem->mode = mode;
 	mem->copy_type = copy_type;
 }
 
diff --git a/lib/intel_blt.h b/lib/intel_blt.h
index 9efa799881..f2509ab175 100644
--- a/lib/intel_blt.h
+++ b/lib/intel_blt.h
@@ -130,6 +130,7 @@ struct blt_copy_data {
 struct blt_mem_copy_data {
 	int fd;
 	enum intel_driver driver;
+	enum blt_memop_mode mode;
 	enum blt_memop_type copy_type;
 	struct blt_mem_object src;
 	struct blt_mem_object dst;
@@ -274,6 +275,7 @@ int blt_fast_copy(int fd,
 		  const struct blt_copy_data *blt);
 
 void blt_mem_copy_init(int fd, struct blt_mem_copy_data *mem,
+		       enum blt_memop_mode mode,
 		       enum blt_memop_type copy_type);
 
 void blt_mem_set_init(int fd, struct blt_mem_set_data *mem,
diff --git a/lib/intel_cmds_info.h b/lib/intel_cmds_info.h
index 88ba892645..17f60ce912 100644
--- a/lib/intel_cmds_info.h
+++ b/lib/intel_cmds_info.h
@@ -30,6 +30,17 @@ enum blt_memop_type {
 	TYPE_MATRIX,
 };
 
+/**
+ * enum blt_memop_mode - memory operation mode mem-copy.
+ *
+ * Mem-copy with linear type supports mode operation in bytes or pages
+ * (page is 256B chunk).
+ */
+enum blt_memop_mode {
+	MODE_BYTE,
+	MODE_PAGE,
+};
+
 enum blt_cmd_type {
 	SRC_COPY,
 	MEM_SET,
diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
index 5681d4d6ab..f252d29fd4 100644
--- a/tests/intel/xe_copy_basic.c
+++ b/tests/intel/xe_copy_basic.c
@@ -56,7 +56,7 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
 
 	bb = xe_bo_create(fd, 0, bb_size, region, 0);
 
-	blt_mem_copy_init(fd, &mem, TYPE_LINEAR);
+	blt_mem_copy_init(fd, &mem, MODE_BYTE, TYPE_LINEAR);
 	blt_set_mem_object(&mem.src, src_handle, size, width, width, height,
 			   region, src_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
 	blt_set_mem_object(&mem.dst, dst_handle, size, width, width, height,
-- 
2.43.0

[PATCH i-g-t v3 04/11] lib/intel_blt: add emit batchbuffer end

[Zbigniew Kempczyński]

Blitter functions allow emit BBE on demand. This gives the caller
to combine different emit functions in single batch.

Cc: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Francois Dugast <francois.dugast@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_blt.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index 6bfaf09a2b..04549ab42e 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -1820,7 +1820,9 @@ void blt_mem_copy_init(int fd, struct blt_mem_copy_data *mem,
 	mem->copy_type = copy_type;
 }
 
-static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_copy_data *mem)
+static void emit_blt_mem_copy(int fd, uint64_t ahnd,
+			      const struct blt_mem_copy_data *mem,
+			      bool emit_bbe)
 {
 	uint64_t dst_offset, src_offset;
 	int i;
@@ -1846,7 +1848,9 @@ static void emit_blt_mem_copy(int fd, uint64_t ahnd, const struct blt_mem_copy_d
 	batch[i++] = dst_offset;
 	batch[i++] = dst_offset << 32;
 	batch[i++] = mem->src.mocs_index << XE2_MEM_COPY_MOCS_SHIFT | mem->dst.mocs_index;
-	batch[i++] = MI_BATCH_BUFFER_END;
+
+	if (emit_bbe)
+		batch[i++] = MI_BATCH_BUFFER_END;
 
 	munmap(batch, mem->bb.size);
 }
@@ -1880,7 +1884,7 @@ int blt_mem_copy(int fd, const intel_ctx_t *ctx,
 					  0, mem->dst.pat_index);
 	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, 0);
 
-	emit_blt_mem_copy(fd, ahnd, mem);
+	emit_blt_mem_copy(fd, ahnd, mem, true);
 
 	if (mem->driver == INTEL_DRIVER_XE) {
 		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
-- 
2.43.0

[PATCH i-g-t v3 05/11] lib/intel_blt: use struct instead of inline coding

[Zbigniew Kempczyński]

Structs with bitfields offer better control to avoid setting
unnecessary bits and get unexpected behavior.

Add struct for mem-copy and replace current byte copy implementation
to byte/page adding iterator for insert couple of mem-copy instructions
if user passed objects which width is greater than limit.

On the first glance order of assigning fields might be weird, but
this will be used in consecutive patch which extends copy from linear
to matrix.

Bspec: 53418
Cc: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Francois Dugast <francois.dugast@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_blt.c | 171 ++++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 144 insertions(+), 27 deletions(-)

diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index 04549ab42e..265f5ed50f 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -1798,6 +1798,73 @@ int blt_fast_copy(int fd,
 	return ret;
 }
 
+struct xe_mem_copy_data {
+	struct {
+		uint32_t length:			BITRANGE(0, 7);
+		uint32_t compression_format:	BITRANGE(8, 12);
+		uint32_t compression_enable:	BITRANGE(13, 13);
+		uint32_t rsvd0:			BITRANGE(14, 14);
+		uint32_t dst_compressible:	BITRANGE(15, 15);
+		uint32_t src_compressible:	BITRANGE(16, 16);
+		uint32_t copy_type:		BITRANGE(17, 18);
+		uint32_t mode:			BITRANGE(19, 19);
+		uint32_t rsvd1:			BITRANGE(20, 21);
+		uint32_t opcode:			BITRANGE(22, 28);
+		uint32_t client:			BITRANGE(29, 31);
+	} dw00;
+
+	struct {
+		union {
+			struct {
+				uint32_t width:			BITRANGE(0, 17);
+				uint32_t rsvd0:			BITRANGE(18, 31);
+			} byte_copy;
+			struct {
+				uint32_t width:			BITRANGE(0, 23);
+				uint32_t rsvd0:			BITRANGE(24, 31);
+			} page_copy;
+			uint32_t val;
+		};
+	} dw01;
+
+	struct {
+		uint32_t height:			BITRANGE(0, 17);
+		uint32_t rsvd0:			BITRANGE(18, 31);
+	} dw02;
+
+	struct {
+		uint32_t src_pitch:		BITRANGE(0, 17);
+		uint32_t rsvd0:			BITRANGE(18, 31);
+	} dw03;
+
+	struct {
+		uint32_t dst_pitch:		BITRANGE(0, 17);
+		uint32_t rsvd0:			BITRANGE(18, 31);
+	} dw04;
+
+	struct {
+		uint32_t src_address_lo;
+	} dw05;
+
+	struct {
+		uint32_t src_address_hi;
+	} dw06;
+
+	struct {
+		uint32_t dst_address_lo;
+	} dw07;
+
+	struct {
+		uint32_t dst_address_hi;
+	} dw08;
+
+	struct {
+		uint32_t dst_mocs:		BITRANGE(0, 6);
+		uint32_t rsvd0:			BITRANGE(7, 24);
+		uint32_t src_mocs:		BITRANGE(25, 31);
+	} dw09;
+};
+
 /**
  * blt_mem_copy_init:
  * @fd: drm fd
@@ -1820,41 +1887,91 @@ void blt_mem_copy_init(int fd, struct blt_mem_copy_data *mem,
 	mem->copy_type = copy_type;
 }
 
-static void emit_blt_mem_copy(int fd, uint64_t ahnd,
-			      const struct blt_mem_copy_data *mem,
-			      bool emit_bbe)
+static uint64_t emit_blt_mem_copy(int fd, uint64_t ahnd,
+				  const struct blt_mem_copy_data *mem,
+				  uint64_t bb_pos, bool emit_bbe)
 {
-	uint64_t dst_offset, src_offset;
-	int i;
-	uint32_t *batch;
-	uint32_t optype;
+	struct xe_mem_copy_data data = {};
+	uint64_t dst_offset, src_offset, shift;
+	uint32_t height, width_max, remain;
+	uint32_t bbe = MI_BATCH_BUFFER_END;
+	uint32_t *bb;
+
+	if (mem->mode == MODE_BYTE) {
+		data.dw01.byte_copy.width = -1;
+		width_max = data.dw01.byte_copy.width + 1;
+		shift = width_max;
+	} else {
+		data.dw01.page_copy.width = -1;
+		width_max = data.dw01.page_copy.width + 1;
+		shift = width_max << 8;
+	}
 
 	src_offset = get_offset_pat_index(ahnd, mem->src.handle, mem->src.size,
 					  0, mem->src.pat_index);
 	dst_offset = get_offset_pat_index(ahnd, mem->dst.handle, mem->dst.size,
 					  0, mem->dst.pat_index);
 
-	batch = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
-	optype = mem->copy_type == TYPE_MATRIX ? 1 << 17 : 0;
-
-	i = 0;
-	batch[i++] = MEM_COPY_CMD | optype;
-	batch[i++] = mem->src.width - 1;
-	batch[i++] = mem->src.height - 1;
-	batch[i++] = mem->src.pitch - 1;
-	batch[i++] = mem->dst.pitch - 1;
-	batch[i++] = src_offset;
-	batch[i++] = src_offset << 32;
-	batch[i++] = dst_offset;
-	batch[i++] = dst_offset << 32;
-	batch[i++] = mem->src.mocs_index << XE2_MEM_COPY_MOCS_SHIFT | mem->dst.mocs_index;
-
-	if (emit_bbe)
-		batch[i++] = MI_BATCH_BUFFER_END;
-
-	munmap(batch, mem->bb.size);
+	bb = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
+
+	height = mem->dst.height;
+
+	data.dw00.client = 0x2;
+	data.dw00.opcode = 0x5a;
+	data.dw00.length = 8;
+	data.dw00.mode = mem->mode;
+	data.dw00.copy_type = mem->copy_type;
+
+	data.dw02.height = height - 1;
+	data.dw05.src_address_lo = src_offset;
+	data.dw06.src_address_hi = src_offset >> 32;
+	data.dw07.dst_address_lo = dst_offset;
+	data.dw08.dst_address_hi = dst_offset >> 32;
+	data.dw09.src_mocs = mem->src.mocs_index;
+	data.dw09.dst_mocs = mem->dst.mocs_index;
+
+	remain = mem->src.width;
+
+	/* Truncate pitches to match operation bits */
+	if (mem->src.pitch > width_max)
+		data.dw03.src_pitch = width_max - 1;
+	else
+		data.dw03.src_pitch = mem->src.pitch;
+
+	if (mem->dst.pitch > width_max)
+		data.dw04.dst_pitch = width_max - 1;
+	else
+		data.dw04.dst_pitch = mem->dst.pitch;
+
+	while (remain) {
+		data.dw01.val = min_t(uint32_t, width_max, remain) - 1;
+
+		igt_assert(bb_pos + sizeof(data) < mem->bb.size);
+		memcpy(bb + bb_pos, &data, sizeof(data));
+		bb_pos += sizeof(data);
+
+		remain -= remain > width_max ? width_max : remain;
+		src_offset += shift;
+		dst_offset += shift;
+
+		data.dw05.src_address_lo = src_offset;
+		data.dw06.src_address_hi = src_offset >> 32;
+		data.dw07.dst_address_lo = dst_offset;
+		data.dw08.dst_address_hi = dst_offset >> 32;
+	}
+
+	if (emit_bbe) {
+		igt_assert(bb_pos + sizeof(uint32_t) < mem->bb.size);
+		memcpy(bb + bb_pos, &bbe, sizeof(bbe));
+		bb_pos += sizeof(uint32_t);
+	}
+
+	munmap(bb, mem->bb.size);
+
+	return bb_pos;
 }
 
+
 /**
  * blt_mem_copy:
  * @fd: drm fd
@@ -1884,7 +2001,7 @@ int blt_mem_copy(int fd, const intel_ctx_t *ctx,
 					  0, mem->dst.pat_index);
 	bb_offset = get_offset(ahnd, mem->bb.handle, mem->bb.size, 0);
 
-	emit_blt_mem_copy(fd, ahnd, mem, true);
+	emit_blt_mem_copy(fd, ahnd, mem, 0, true);
 
 	if (mem->driver == INTEL_DRIVER_XE) {
 		intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset));
-- 
2.43.0

[PATCH i-g-t v3 06/11] tests/xe_copy_basic: replace size to rect which keeps objects geometry

[Zbigniew Kempczyński]

Testing byte/page + linear/matrix mem-copy requires passing different
pitch/width/height so replace simple size to geometry.

Change mem-copy and mem-set to use rect instead of size for
copying bytes.

Cc: Francois Dugast <francois.dugast@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/intel/xe_copy_basic.c | 44 +++++++++++++++++++++++--------------
 1 file changed, 28 insertions(+), 16 deletions(-)

diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
index f252d29fd4..569f250cc4 100644
--- a/tests/intel/xe_copy_basic.c
+++ b/tests/intel/xe_copy_basic.c
@@ -19,6 +19,13 @@
 
 #define MEM_FILL 0x8b
 
+struct rect {
+	uint32_t pitch;
+	uint32_t width;
+	uint32_t height;
+	enum blt_memop_mode mode;
+};
+
 /**
  * TEST: Test to validate copy commands on xe
  * Category: Core
@@ -42,7 +49,9 @@
  */
 static void
 mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ctx,
-	 uint32_t size, uint32_t width, uint32_t height, uint32_t region)
+	 enum blt_memop_type type, enum blt_memop_mode mode,
+	 uint32_t size, uint32_t pitch,
+	 uint32_t width, uint32_t height, uint32_t region)
 {
 	struct blt_mem_copy_data mem = {};
 	uint64_t bb_size = xe_bb_size(fd, SZ_4K);
@@ -125,13 +134,15 @@ mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx, uint32_t size,
 	munmap(mem.dst.ptr, size);
 }
 
-static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd, uint32_t region)
+static void copy_test(int fd, struct rect *rect, enum blt_cmd_type cmd, uint32_t region)
 {
 	struct drm_xe_engine_class_instance inst = {
 		.engine_class = DRM_XE_ENGINE_CLASS_COPY,
 	};
-	uint32_t src_handle, dst_handle, vm, exec_queue, src_size, dst_size;
-	uint32_t bo_size = ALIGN(size, xe_get_default_alignment(fd));
+	uint32_t src_handle, dst_handle, vm, exec_queue;
+	uint32_t pitch = rect->pitch ?: rect->width;
+	uint32_t blocksize = rect->mode == MODE_PAGE ? pitch << 8 : pitch;
+	uint32_t bo_size = ALIGN(blocksize * rect->height, xe_get_default_alignment(fd));
 	intel_ctx_t *ctx;
 
 	src_handle = xe_bo_create(fd, 0, bo_size, region, 0);
@@ -140,13 +151,11 @@ static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd, uint32_t reg
 	exec_queue = xe_exec_queue_create(fd, vm, &inst, 0);
 	ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0);
 
-	src_size = bo_size;
-	dst_size = bo_size;
-
 	if (cmd == MEM_COPY)
-		mem_copy(fd, src_handle, dst_handle, ctx, src_size, size, 1, region);
+		mem_copy(fd, src_handle, dst_handle, ctx, TYPE_LINEAR, rect->mode,
+			 bo_size, pitch, rect->width, rect->height, region);
 	else if (cmd == MEM_SET)
-		mem_set(fd, dst_handle, ctx, dst_size, size, 1, MEM_FILL, region);
+		mem_set(fd, dst_handle, ctx, bo_size, rect->width, 1, MEM_FILL, region);
 
 	gem_close(fd, src_handle);
 	gem_close(fd, dst_handle);
@@ -160,7 +169,10 @@ igt_main
 	int fd;
 	struct igt_collection *set, *regions;
 	uint32_t region;
-	uint64_t size[] = {0xFD, 0x369, 0x3FFF, 0xFFFE};
+	struct rect linear[] = { { 0, 0xfd, 1 },
+				 { 0, 0x369, 1 },
+				 { 0, 0x3fff, 1 },
+				 { 0, 0xfffe, 1 } };
 
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_XE);
@@ -170,22 +182,22 @@ igt_main
 					       DRM_XE_MEM_REGION_CLASS_VRAM);
 	}
 
-	for (int i = 0; i < ARRAY_SIZE(size); i++) {
-		igt_subtest_f("mem-copy-linear-0x%"PRIx64"", size[i]) {
+	for (int i = 0; i < ARRAY_SIZE(linear); i++) {
+		igt_subtest_f("mem-copy-linear-0x%x", linear[i].width) {
 			igt_require(blt_has_mem_copy(fd));
 			for_each_variation_r(regions, 1, set) {
 				region = igt_collection_get_value(regions, 0);
-				copy_test(fd, size[i], MEM_COPY, region);
+				copy_test(fd, &linear[i], MEM_COPY, region);
 			}
 		}
 	}
 
-	for (int i = 0; i < ARRAY_SIZE(size); i++) {
-		igt_subtest_f("mem-set-linear-0x%"PRIx64"", size[i]) {
+	for (int i = 0; i < ARRAY_SIZE(linear); i++) {
+		igt_subtest_f("mem-set-linear-0x%x", linear[i].width) {
 			igt_require(blt_has_mem_set(fd));
 			for_each_variation_r(regions, 1, set) {
 				region = igt_collection_get_value(regions, 0);
-				copy_test(fd, size[i], MEM_SET, region);
+				copy_test(fd, &linear[i], MEM_SET, region);
 			}
 		}
 	}
-- 
2.43.0

[PATCH i-g-t v3 07/11] tests/xe_copy_basic: add testcase with large buffer size

[Zbigniew Kempczyński]

Maximum possible size for mem-copy/byte is 256KiB. Verify intel_blt
is able to emit multiple mem-copy commands to copy buffer which
is larger than 256KiB.

Cc: Francois Dugast <francois.dugast@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/intel/xe_copy_basic.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
index 569f250cc4..bed3e39426 100644
--- a/tests/intel/xe_copy_basic.c
+++ b/tests/intel/xe_copy_basic.c
@@ -46,6 +46,7 @@ struct rect {
  * @0x3fff: 0x3fff
  * @0xfd: 0xfd
  * @0xfffe: 0xfffe
+ * @0x8fffe: 0x8fffe
  */
 static void
 mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ctx,
@@ -99,6 +100,7 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
  * @0x3fff: 0x3fff
  * @0xfd: 0xfd
  * @0xfffe: 0xfffe
+ * @0x8fffe: 0x8fffe
  */
 static void
 mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx, uint32_t size,
@@ -172,7 +174,8 @@ igt_main
 	struct rect linear[] = { { 0, 0xfd, 1 },
 				 { 0, 0x369, 1 },
 				 { 0, 0x3fff, 1 },
-				 { 0, 0xfffe, 1 } };
+				 { 0, 0xfffe, 1 },
+				 { 0, 0x8fffe, 1 } };
 
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_XE);
-- 
2.43.0

[PATCH i-g-t v3 08/11] tests/xe_copy_basic: add subtest to verify mem-copy in pages

[Zbigniew Kempczyński]

Mem-copy in linear mode supports copying in 256B pages. Verify is
it properly handled in intel_blt.

Cc: Francois Dugast <francois.dugast@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/intel/xe_copy_basic.c | 56 ++++++++++++++++++++++++++++++++++---
 1 file changed, 52 insertions(+), 4 deletions(-)

diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
index bed3e39426..404fe7f50a 100644
--- a/tests/intel/xe_copy_basic.c
+++ b/tests/intel/xe_copy_basic.c
@@ -48,6 +48,20 @@ struct rect {
  * @0xfffe: 0xfffe
  * @0x8fffe: 0x8fffe
  */
+
+/**
+ *
+ * SUBTEST: mem-page-copy-%s
+ * Description: Test validates MEM_COPY command, it takes various
+ *              parameters needed for the filling batch buffer for MEM_COPY command
+ *              with size %arg[1].
+ * Test category: functionality test
+ *
+ * arg[1]:
+ * @1: 1
+ * @17: 17
+ */
+
 static void
 mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ctx,
 	 enum blt_memop_type type, enum blt_memop_mode mode,
@@ -62,23 +76,45 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
 	uint8_t src_mocs = intel_get_uc_mocs_index(fd);
 	uint8_t dst_mocs = src_mocs;
 	uint32_t bb;
-	int result;
+	uint8_t *psrc, *pdst;
+	int result, i;
 
 	bb = xe_bo_create(fd, 0, bb_size, region, 0);
 
-	blt_mem_copy_init(fd, &mem, MODE_BYTE, TYPE_LINEAR);
+	blt_mem_copy_init(fd, &mem, mode, type);
 	blt_set_mem_object(&mem.src, src_handle, size, width, width, height,
 			   region, src_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
 	blt_set_mem_object(&mem.dst, dst_handle, size, width, width, height,
 			   region, dst_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
 	mem.src.ptr = xe_bo_map(fd, src_handle, size);
 	mem.dst.ptr = xe_bo_map(fd, dst_handle, size);
+	psrc = (uint8_t *) mem.src.ptr;
+	pdst = (uint8_t *) mem.dst.ptr;
+
+	srand(time(NULL));
+
+	/* Randomize whole src */
+	for (i = 0; i < size; i++)
+		psrc[i] = rand();
 
 	blt_set_batch(&mem.bb, bb, bb_size, region);
 	igt_assert(mem.src.width == mem.dst.width);
 
 	blt_mem_copy(fd, ctx, NULL, ahnd, &mem);
-	result = memcmp(mem.src.ptr, mem.dst.ptr, mem.src.size);
+
+	if (type == TYPE_LINEAR && mode == MODE_BYTE) {
+		result = memcmp(psrc, pdst, width);
+
+		/* Rest of dst must contain 0 */
+		for (i = width; i < size; i++) {
+			if (pdst[i] != 0) {
+				result = -1;
+				break;
+			}
+		}
+	} else {
+		result = memcmp(psrc, pdst, pitch << 8);
+	}
 
 	intel_allocator_bind(ahnd, 0, 0);
 	munmap(mem.src.ptr, size);
@@ -86,7 +122,7 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
 	gem_close(fd, bb);
 	put_ahnd(ahnd);
 
-	igt_assert_f(!result, "source and destination differ\n");
+	igt_assert_f(!result, "destination doesn't contain valid data\n");
 }
 
 /**
@@ -176,6 +212,8 @@ igt_main
 				 { 0, 0x3fff, 1 },
 				 { 0, 0xfffe, 1 },
 				 { 0, 0x8fffe, 1 } };
+	struct rect page[] = { { 0, 1, 1, MODE_PAGE },
+			       { 0, 17, 1, MODE_PAGE }};
 
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_XE);
@@ -195,6 +233,16 @@ igt_main
 		}
 	}
 
+	for (int i = 0; i < ARRAY_SIZE(page); i++) {
+		igt_subtest_f("mem-page-copy-%u", page[i].width) {
+			igt_require(blt_has_mem_copy(fd));
+			for_each_variation_r(regions, 1, set) {
+				region = igt_collection_get_value(regions, 0);
+				copy_test(fd, &page[i], MEM_COPY, region);
+			}
+		}
+	}
+
 	for (int i = 0; i < ARRAY_SIZE(linear); i++) {
 		igt_subtest_f("mem-set-linear-0x%x", linear[i].width) {
 			igt_require(blt_has_mem_set(fd));
-- 
2.43.0

[PATCH i-g-t v3 09/11] lib/intel_blt: add support for matrix mem-copy

[Zbigniew Kempczyński]

Linear copy in intel_blt supports passing large buffers (which
requires to be spread over couple mem-copies). For matrix this is
a little bit more complicated so I left simple case in which
pitch/width/height must be within mem-copy command limits -
18-bit width * 18-bit height gives 64GiB object so testing
copying bigger buffer would be an overkill.

Cc: Francois Dugast <francois.dugast@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_blt.c | 69 +++++++++++++++++++++++++++++++++----------------
 1 file changed, 47 insertions(+), 22 deletions(-)

diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index 265f5ed50f..77a03aff4e 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -1893,17 +1893,18 @@ static uint64_t emit_blt_mem_copy(int fd, uint64_t ahnd,
 {
 	struct xe_mem_copy_data data = {};
 	uint64_t dst_offset, src_offset, shift;
-	uint32_t height, width_max, remain;
+	uint32_t width, height, width_max, height_max, remain;
 	uint32_t bbe = MI_BATCH_BUFFER_END;
 	uint32_t *bb;
 
 	if (mem->mode == MODE_BYTE) {
 		data.dw01.byte_copy.width = -1;
-		width_max = data.dw01.byte_copy.width + 1;
+		height_max = width_max = data.dw01.byte_copy.width + 1;
 		shift = width_max;
 	} else {
 		data.dw01.page_copy.width = -1;
 		width_max = data.dw01.page_copy.width + 1;
+		height_max = 1;
 		shift = width_max << 8;
 	}
 
@@ -1914,6 +1915,7 @@ static uint64_t emit_blt_mem_copy(int fd, uint64_t ahnd,
 
 	bb = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
 
+	width = mem->src.width;
 	height = mem->dst.height;
 
 	data.dw00.client = 0x2;
@@ -1930,34 +1932,57 @@ static uint64_t emit_blt_mem_copy(int fd, uint64_t ahnd,
 	data.dw09.src_mocs = mem->src.mocs_index;
 	data.dw09.dst_mocs = mem->dst.mocs_index;
 
-	remain = mem->src.width;
+	/* For matrix we don't iterate */
+	if (mem->copy_type == TYPE_MATRIX) {
+		if (width > width_max) {
+			width = width_max;
+			igt_warn("src width is bigger than max width [%u > %u => %u], truncating it\n",
+				 mem->src.width, width_max, width);
+		}
 
-	/* Truncate pitches to match operation bits */
-	if (mem->src.pitch > width_max)
-		data.dw03.src_pitch = width_max - 1;
-	else
-		data.dw03.src_pitch = mem->src.pitch;
+		if (height > height_max) {
+			height = height_max;
+			igt_warn("src height is bigger than max height [%u > %u => %u], truncating it\n",
+				 mem->src.height, height_max, height);
+		}
 
-	if (mem->dst.pitch > width_max)
-		data.dw04.dst_pitch = width_max - 1;
-	else
-		data.dw04.dst_pitch = mem->dst.pitch;
-
-	while (remain) {
-		data.dw01.val = min_t(uint32_t, width_max, remain) - 1;
+		data.dw01.byte_copy.width = width - 1;
+		data.dw03.src_pitch = mem->src.pitch - 1;
+		data.dw04.dst_pitch = mem->dst.pitch - 1;
 
 		igt_assert(bb_pos + sizeof(data) < mem->bb.size);
 		memcpy(bb + bb_pos, &data, sizeof(data));
 		bb_pos += sizeof(data);
+	} else {
+		remain = mem->src.width;
 
-		remain -= remain > width_max ? width_max : remain;
-		src_offset += shift;
-		dst_offset += shift;
+		/* Truncate pitches to match operation bits */
+		if (mem->src.pitch > width_max)
+			data.dw03.src_pitch = width_max - 1;
+		else
+			data.dw03.src_pitch = mem->src.pitch;
 
-		data.dw05.src_address_lo = src_offset;
-		data.dw06.src_address_hi = src_offset >> 32;
-		data.dw07.dst_address_lo = dst_offset;
-		data.dw08.dst_address_hi = dst_offset >> 32;
+		if (mem->dst.pitch > width_max)
+			data.dw04.dst_pitch = width_max - 1;
+		else
+			data.dw04.dst_pitch = mem->dst.pitch;
+
+		while (remain) {
+			data.dw01.val = min_t(uint32_t, width_max, remain) - 1;
+
+			igt_assert(bb_pos + sizeof(data) < mem->bb.size);
+			memcpy(bb + bb_pos, &data, sizeof(data));
+			bb_pos += sizeof(data);
+
+			remain -= remain > width_max ? width_max : remain;
+			src_offset += shift;
+			dst_offset += shift;
+
+			data.dw05.src_address_lo = src_offset;
+			data.dw06.src_address_hi = src_offset >> 32;
+			data.dw07.dst_address_lo = dst_offset;
+			data.dw08.dst_address_hi = dst_offset >> 32;
+		}
 	}
 
 	if (emit_bbe) {
-- 
2.43.0

[PATCH i-g-t v3 10/11] tests/xe_copy_basic: add mem-copy matrix subtests

[Zbigniew Kempczyński]

Verify intel_blt is able to properly copy matrix from one buffer
to another.

Cc: Francois Dugast <francois.dugast@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 tests/intel/xe_copy_basic.c | 52 +++++++++++++++++++++++++++++++++----
 1 file changed, 47 insertions(+), 5 deletions(-)

diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
index 404fe7f50a..be400e3175 100644
--- a/tests/intel/xe_copy_basic.c
+++ b/tests/intel/xe_copy_basic.c
@@ -62,6 +62,19 @@ struct rect {
  * @17: 17
  */
 
+/**
+ *
+ * SUBTEST: mem-matrix-copy-%s
+ * Description: Test validates MEM_COPY command, it takes various
+ *              parameters needed for the filling batch buffer for MEM_COPY command
+ *              with size %arg[1].
+ * Test category: functionality test
+ *
+ * arg[1]:
+ * @2x2: 2x2
+ * @200x127: 200x127
+ */
+
 static void
 mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ctx,
 	 enum blt_memop_type type, enum blt_memop_mode mode,
@@ -79,13 +92,17 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
 	uint8_t *psrc, *pdst;
 	int result, i;
 
+	igt_debug("size: %u, pitch: %u, width: %u, height: %u (type: %d, mode: %d)\n",
+		  size, pitch, width, height, type, mode);
+
 	bb = xe_bo_create(fd, 0, bb_size, region, 0);
 
 	blt_mem_copy_init(fd, &mem, mode, type);
-	blt_set_mem_object(&mem.src, src_handle, size, width, width, height,
+	blt_set_mem_object(&mem.src, src_handle, size, pitch, width, height,
 			   region, src_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
-	blt_set_mem_object(&mem.dst, dst_handle, size, width, width, height,
+	blt_set_mem_object(&mem.dst, dst_handle, size, pitch, width, height,
 			   region, dst_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
+
 	mem.src.ptr = xe_bo_map(fd, src_handle, size);
 	mem.dst.ptr = xe_bo_map(fd, dst_handle, size);
 	psrc = (uint8_t *) mem.src.ptr;
@@ -112,8 +129,20 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
 				break;
 			}
 		}
-	} else {
+	} else if (type == TYPE_LINEAR && mode == MODE_PAGE) {
 		result = memcmp(psrc, pdst, pitch << 8);
+	} else {
+		result = 0;
+
+		for (i = 0; i < pitch * height; i++) {
+			if (i % pitch > width && pdst[i] != 0) {
+				result = -1;
+				break;
+			} else if (i % pitch < width && psrc[i] != pdst[i]) {
+				result = -1;
+				break;
+			}
+		}
 	}
 
 	intel_allocator_bind(ahnd, 0, 0);
@@ -190,8 +219,10 @@ static void copy_test(int fd, struct rect *rect, enum blt_cmd_type cmd, uint32_t
 	ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0);
 
 	if (cmd == MEM_COPY)
-		mem_copy(fd, src_handle, dst_handle, ctx, TYPE_LINEAR, rect->mode,
-			 bo_size, pitch, rect->width, rect->height, region);
+		mem_copy(fd, src_handle, dst_handle, ctx,
+			 rect->height > 1 ? TYPE_MATRIX : TYPE_LINEAR,
+			 rect->mode, bo_size, pitch,
+			 rect->width, rect->height, region);
 	else if (cmd == MEM_SET)
 		mem_set(fd, dst_handle, ctx, bo_size, rect->width, 1, MEM_FILL, region);
 
@@ -214,6 +245,7 @@ igt_main
 				 { 0, 0x8fffe, 1 } };
 	struct rect page[] = { { 0, 1, 1, MODE_PAGE },
 			       { 0, 17, 1, MODE_PAGE }};
+	struct rect matrix[] = { { 4, 2, 2 }, { 256, 200, 127 } };
 
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_XE);
@@ -243,6 +275,16 @@ igt_main
 		}
 	}
 
+	for (int i = 0; i < ARRAY_SIZE(matrix); i++) {
+		igt_subtest_f("mem-matrix-copy-%ux%u", matrix[i].width, matrix[i].height) {
+			igt_require(blt_has_mem_copy(fd));
+			for_each_variation_r(regions, 1, set) {
+				region = igt_collection_get_value(regions, 0);
+				copy_test(fd, &matrix[i], MEM_COPY, region);
+			}
+		}
+	}
+
 	for (int i = 0; i < ARRAY_SIZE(linear); i++) {
 		igt_subtest_f("mem-set-linear-0x%x", linear[i].width) {
 			igt_require(blt_has_mem_set(fd));
-- 
2.43.0

[PATCH i-g-t v3 11/11] lib/intel_blt: add mem-copy debug facility

[Zbigniew Kempczyński]

Sometimes dumping batch with command is useful, especially during
debugging. Basic functions in intel_blt like block-copy/fast-copy/
surf-ctrl-copy) already have such batch dump code. Add similar
function for mem-copy.

Cc: Francois Dugast <francois.dugast@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 lib/intel_blt.c             | 37 +++++++++++++++++++++++++++++++++++++
 lib/intel_blt.h             |  1 +
 tests/intel/xe_copy_basic.c | 28 +++++++++++++++++++++++++++-
 3 files changed, 65 insertions(+), 1 deletion(-)

diff --git a/lib/intel_blt.c b/lib/intel_blt.c
index 77a03aff4e..8a05f482fd 100644
--- a/lib/intel_blt.c
+++ b/lib/intel_blt.c
@@ -1887,6 +1887,33 @@ void blt_mem_copy_init(int fd, struct blt_mem_copy_data *mem,
 	mem->copy_type = copy_type;
 }
 
+static void dump_bb_mem_copy_cmd(struct xe_mem_copy_data *data)
+{
+	uint32_t *cmd = (uint32_t *) data;
+
+	igt_info("BB details:\n");
+	igt_info(" dw00: [%08x] <client: 0x%x, opcode: 0x%x, length: %d> "
+		 "[copy type: %d, mode: %d]\n",
+		 cmd[0], data->dw00.client, data->dw00.opcode, data->dw00.length,
+		 data->dw00.copy_type, data->dw00.mode);
+	igt_info(" dw01: [%08x] width: %u\n", cmd[1],
+		 data->dw00.mode == MODE_BYTE ? data->dw01.byte_copy.width :
+						data->dw01.page_copy.width);
+	igt_info(" dw02: [%08x] height: %u\n", cmd[2], data->dw02.height);
+	igt_info(" dw03: [%08x] src pitch: %u\n", cmd[3], data->dw03.src_pitch);
+	igt_info(" dw04: [%08x] dst pitch: %u\n", cmd[4], data->dw04.dst_pitch);
+	igt_info(" dw05: [%08x] src offset lo (0x%x)\n",
+		 cmd[5], data->dw05.src_address_lo);
+	igt_info(" dw06: [%08x] src offset hi (0x%x)\n",
+		 cmd[6], data->dw06.src_address_hi);
+	igt_info(" dw07: [%08x] dst offset lo (0x%x)\n",
+		 cmd[7], data->dw07.dst_address_lo);
+	igt_info(" dw08: [%08x] dst offset hi (0x%x)\n",
+		 cmd[8], data->dw08.dst_address_hi);
+	igt_info(" dw09: [%08x] mocs <dst: 0x%x, src: 0x%x>\n",
+		 cmd[8], data->dw09.dst_mocs, data->dw09.src_mocs);
+}
+
 static uint64_t emit_blt_mem_copy(int fd, uint64_t ahnd,
 				  const struct blt_mem_copy_data *mem,
 				  uint64_t bb_pos, bool emit_bbe)
@@ -1953,6 +1980,11 @@ static uint64_t emit_blt_mem_copy(int fd, uint64_t ahnd,
 		igt_assert(bb_pos + sizeof(data) < mem->bb.size);
 		memcpy(bb + bb_pos, &data, sizeof(data));
 		bb_pos += sizeof(data);
+
+		if (mem->print_bb) {
+			igt_info("[MEM COPY]\n");
+			dump_bb_mem_copy_cmd(&data);
+		}
 	} else {
 		remain = mem->src.width;
 
@@ -1982,6 +2014,11 @@ static uint64_t emit_blt_mem_copy(int fd, uint64_t ahnd,
 			data.dw06.src_address_hi = src_offset >> 32;
 			data.dw07.dst_address_lo = dst_offset;
 			data.dw08.dst_address_hi = dst_offset >> 32;
+
+			if (mem->print_bb) {
+				igt_info("[MEM COPY]\n");
+				dump_bb_mem_copy_cmd(&data);
+			}
 		}
 	}
 
diff --git a/lib/intel_blt.h b/lib/intel_blt.h
index f2509ab175..54a096c039 100644
--- a/lib/intel_blt.h
+++ b/lib/intel_blt.h
@@ -135,6 +135,7 @@ struct blt_mem_copy_data {
 	struct blt_mem_object src;
 	struct blt_mem_object dst;
 	struct blt_copy_batch bb;
+	bool print_bb;
 };
 
 struct blt_mem_set_data {
diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
index be400e3175..bb1a4c536c 100644
--- a/tests/intel/xe_copy_basic.c
+++ b/tests/intel/xe_copy_basic.c
@@ -19,6 +19,12 @@
 
 #define MEM_FILL 0x8b
 
+static struct param {
+	bool print_bb;
+} param = {
+	.print_bb = false,
+};
+
 struct rect {
 	uint32_t pitch;
 	uint32_t width;
@@ -98,6 +104,8 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
 	bb = xe_bo_create(fd, 0, bb_size, region, 0);
 
 	blt_mem_copy_init(fd, &mem, mode, type);
+	mem.print_bb = param.print_bb;
+
 	blt_set_mem_object(&mem.src, src_handle, size, pitch, width, height,
 			   region, src_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
 	blt_set_mem_object(&mem.dst, dst_handle, size, pitch, width, height,
@@ -233,7 +241,25 @@ static void copy_test(int fd, struct rect *rect, enum blt_cmd_type cmd, uint32_t
 	free(ctx);
 }
 
-igt_main
+static int opt_handler(int opt, int opt_index, void *data)
+{
+	switch (opt) {
+	case 'b':
+		param.print_bb = true;
+		igt_debug("Print bb: %d\n", param.print_bb);
+		break;
+	default:
+		return IGT_OPT_HANDLER_ERROR;
+	}
+
+	return IGT_OPT_HANDLER_SUCCESS;
+}
+
+const char *help_str =
+	"  -b\tPrint bb"
+	;
+
+igt_main_args("b", NULL, help_str, opt_handler, NULL)
 {
 	int fd;
 	struct igt_collection *set, *regions;
-- 
2.43.0

✗ i915.CI.BAT: failure for Improve mem-copy/mem-set lib and tests (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3578 bytes --]

== Series Details ==

Series: Improve mem-copy/mem-set lib and tests (rev2)
URL   : https://patchwork.freedesktop.org/series/148977/
State : failure

== Summary ==

CI Bug Log - changes from IGT_8377 -> IGTPW_13174
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_13174 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_13174, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13174/index.html

Participating hosts (42 -> 40)
------------------------------

  Missing    (2): fi-tgl-1115g4 fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_13174:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live:
    - fi-bsw-n3050:       [PASS][1] -> [DMESG-FAIL][2] +1 other test dmesg-fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8377/fi-bsw-n3050/igt@i915_selftest@live.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13174/fi-bsw-n3050/igt@i915_selftest@live.html

  * igt@i915_selftest@live@gem_contexts:
    - bat-arls-6:         [PASS][3] -> [INCOMPLETE][4] +1 other test incomplete
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8377/bat-arls-6/igt@i915_selftest@live@gem_contexts.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13174/bat-arls-6/igt@i915_selftest@live@gem_contexts.html

  
Known issues
------------

  Here are the changes found in IGTPW_13174 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-arlh-2:         [PASS][5] -> [INCOMPLETE][6] ([i915#14046]) +1 other test incomplete
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8377/bat-arlh-2/igt@i915_selftest@live.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13174/bat-arlh-2/igt@i915_selftest@live.html

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-14:         [PASS][7] -> [DMESG-FAIL][8] ([i915#12061]) +1 other test dmesg-fail
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8377/bat-dg2-14/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13174/bat-dg2-14/igt@i915_selftest@live@workarounds.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-arls-5:         [DMESG-FAIL][9] ([i915#12061]) -> [PASS][10] +1 other test pass
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_8377/bat-arls-5/igt@i915_selftest@live@workarounds.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13174/bat-arls-5/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#14046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14046


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_8377 -> IGTPW_13174

  CI-20190529: 20190529
  CI_DRM_16587: dad3dc322768427e2ecb1a887cb3b710f8bc6848 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_13174: 8fb03fd8fec1b3e78e7892c91b7396b8201fa396 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8377: b8dfaa900e3eadadfdba19f075157983d6dbd5b8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_13174/index.html

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✓ Xe.CI.BAT: success for Improve mem-copy/mem-set lib and tests (rev2)

[Patchwork]

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== Series Details ==

Series: Improve mem-copy/mem-set lib and tests (rev2)
URL   : https://patchwork.freedesktop.org/series/148977/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_8377_BAT -> XEIGTPW_13174_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (8 -> 8)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in XEIGTPW_13174_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_sysfs_debugfs@xe-sysfs-read-all-entries:
    - bat-lnl-2:          [PASS][1] -> [DMESG-WARN][2] ([Intel XE#5002])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/bat-lnl-2/igt@intel_sysfs_debugfs@xe-sysfs-read-all-entries.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/bat-lnl-2/igt@intel_sysfs_debugfs@xe-sysfs-read-all-entries.html

  * igt@xe_exec_atomic@basic-dec-all@engine-drm_xe_engine_class_video_decode-instance-0-tile-1-system-memory:
    - bat-lnl-2:          [PASS][3] -> [INCOMPLETE][4] ([Intel XE#4966]) +1 other test incomplete
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/bat-lnl-2/igt@xe_exec_atomic@basic-dec-all@engine-drm_xe_engine_class_video_decode-instance-0-tile-1-system-memory.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/bat-lnl-2/igt@xe_exec_atomic@basic-dec-all@engine-drm_xe_engine_class_video_decode-instance-0-tile-1-system-memory.html

  
  [Intel XE#4966]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4966
  [Intel XE#5002]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5002


Build changes
-------------

  * IGT: IGT_8377 -> IGTPW_13174

  IGTPW_13174: 8fb03fd8fec1b3e78e7892c91b7396b8201fa396 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8377: b8dfaa900e3eadadfdba19f075157983d6dbd5b8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3131-dad3dc322768427e2ecb1a887cb3b710f8bc6848: dad3dc322768427e2ecb1a887cb3b710f8bc6848

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/index.html

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✓ Xe.CI.Full: success for Improve mem-copy/mem-set lib and tests (rev2)

[Patchwork]

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== Series Details ==

Series: Improve mem-copy/mem-set lib and tests (rev2)
URL   : https://patchwork.freedesktop.org/series/148977/
State : success

== Summary ==

CI Bug Log - changes from XEIGT_8377_FULL -> XEIGTPW_13174_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (4 -> 3)
------------------------------

  Missing    (1): shard-adlp 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in XEIGTPW_13174_FULL:

### IGT changes ###

#### Possible regressions ####

  * {igt@xe_copy_basic@mem-page-copy-17} (NEW):
    - shard-dg2-set2:     NOTRUN -> [SKIP][1] +5 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-432/igt@xe_copy_basic@mem-page-copy-17.html

  
New tests
---------

  New tests have been introduced between XEIGT_8377_FULL and XEIGTPW_13174_FULL:

### New IGT tests (6) ###

  * igt@xe_copy_basic@mem-copy-linear-0x8fffe:
    - Statuses : 1 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.02] s

  * igt@xe_copy_basic@mem-matrix-copy-200x127:
    - Statuses : 2 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.10] s

  * igt@xe_copy_basic@mem-matrix-copy-2x2:
    - Statuses : 1 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@xe_copy_basic@mem-page-copy-1:
    - Statuses : 1 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@xe_copy_basic@mem-page-copy-17:
    - Statuses : 2 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.01] s

  * igt@xe_copy_basic@mem-set-linear-0x8fffe:
    - Statuses : 2 pass(s) 1 skip(s)
    - Exec time: [0.0, 0.01] s

  

Known issues
------------

  Here are the changes found in XEIGTPW_13174_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-tiled:
    - shard-bmg:          [PASS][2] -> [DMESG-WARN][3] ([Intel XE#3428])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-4/igt@kms_async_flips@async-flip-with-page-flip-events-tiled.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@kms_async_flips@async-flip-with-page-flip-events-tiled.html

  * igt@kms_async_flips@invalid-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][4] ([Intel XE#873])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-1/igt@kms_async_flips@invalid-async-flip.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2327]) +3 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][6] ([Intel XE#316])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#1467])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-8/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#1124]) +11 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#1124]) +5 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-6/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-dg2-set2:     NOTRUN -> [SKIP][10] ([Intel XE#619])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#1124]) +2 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-436/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2314] / [Intel XE#2894])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][13] ([Intel XE#2191]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-435/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-2-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#367]) +2 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html

  * igt@kms_bw@linear-tiling-4-displays-2560x1440p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][15] ([Intel XE#367])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#1512])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-6/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2887]) +17 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][18] ([Intel XE#2907]) +1 other test skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs@pipe-c-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#2669]) +3 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-3/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs@pipe-c-edp-1.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs@pipe-b-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2652] / [Intel XE#787]) +4 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs@pipe-b-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#2887]) +6 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     [PASS][22] -> [INCOMPLETE][23] ([Intel XE#3862]) +1 other test incomplete
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-436/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-dp-4.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][24] ([Intel XE#3442])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-435/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#3432]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][26] ([Intel XE#787]) +181 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-436/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][27] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][28] ([Intel XE#455] / [Intel XE#787]) +33 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-dp-4.html

  * igt@kms_cdclk@mode-transition@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][29] ([Intel XE#4417]) +3 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html

  * igt@kms_chamelium_color@ctm-0-50:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#306]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-6/igt@kms_chamelium_color@ctm-0-50.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-dg2-set2:     NOTRUN -> [SKIP][31] ([Intel XE#306])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-436/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_color@degamma:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#2325]) +3 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_frames@hdmi-aspect-ratio:
    - shard-dg2-set2:     NOTRUN -> [SKIP][33] ([Intel XE#373]) +8 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@kms_chamelium_frames@hdmi-aspect-ratio.html

  * igt@kms_chamelium_hpd@dp-hpd-storm-disable:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#2252]) +4 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html

  * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#373]) +3 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-1/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html

  * igt@kms_content_protection@atomic:
    - shard-dg2-set2:     NOTRUN -> [FAIL][36] ([Intel XE#1178]) +2 other tests fail
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-436/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#2390])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_content_protection@dp-mst-type-1.html
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#307])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-7/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@lic-type-0@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][39] ([Intel XE#1178]) +1 other test fail
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-8/igt@kms_content_protection@lic-type-0@pipe-a-dp-2.html

  * igt@kms_content_protection@mei-interface:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#2341]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@kms_content_protection@mei-interface.html

  * igt@kms_cursor_crc@cursor-offscreen-128x42:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#1424])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-1/igt@kms_cursor_crc@cursor-offscreen-128x42.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#2321])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85:
    - shard-bmg:          NOTRUN -> [SKIP][43] ([Intel XE#2320]) +4 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@kms_cursor_crc@cursor-onscreen-256x85.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#2321]) +1 other test skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-4/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#2291]) +1 other test skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#309]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-7/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
    - shard-bmg:          [PASS][47] -> [SKIP][48] ([Intel XE#2291]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#323])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#2286])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#1508])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-dg2-set2:     NOTRUN -> [SKIP][52] ([Intel XE#4354])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-432/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#4354])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#2244])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-8/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#2244]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-1/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#4156])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_feature_discovery@chamelium:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#2372])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@kms_feature_discovery@chamelium.html
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#701])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-2/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@display-4x:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#1138])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-dg2-set2:     NOTRUN -> [SKIP][60] ([Intel XE#1137])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-432/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@psr1:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#2374]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#1421]) +5 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-6/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4:
    - shard-dg2-set2:     [PASS][63] -> [FAIL][64] ([Intel XE#301]) +5 other tests fail
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-464/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3:
    - shard-bmg:          [PASS][65] -> [FAIL][66] ([Intel XE#3321])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-bmg:          NOTRUN -> [SKIP][67] ([Intel XE#2316]) +4 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@flip-vs-expired-vblank@a-dp4:
    - shard-dg2-set2:     [PASS][68] -> [FAIL][69] ([Intel XE#301] / [Intel XE#3321]) +1 other test fail
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-463/igt@kms_flip@flip-vs-expired-vblank@a-dp4.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@a-dp4.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][70] ([Intel XE#455]) +9 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-464/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][71] ([Intel XE#1401]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][72] ([Intel XE#2380]) +1 other test skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#1397] / [Intel XE#1745])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-8/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#1397])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-8/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling:
    - shard-lnl:          NOTRUN -> [FAIL][75] ([Intel XE#4683]) +1 other test fail
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-6/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#2293] / [Intel XE#2380]) +6 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][77] ([Intel XE#1401] / [Intel XE#1745]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#2293]) +6 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][79] ([Intel XE#651]) +6 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-3/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][80] ([Intel XE#651]) +11 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][81] ([Intel XE#2311]) +25 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][82] ([Intel XE#4141]) +13 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-rte:
    - shard-lnl:          NOTRUN -> [SKIP][83] ([Intel XE#656]) +17 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#2313]) +25 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][85] ([Intel XE#2312]) +16 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][86] ([Intel XE#653]) +16 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_getfb@getfb2-accept-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][87] ([Intel XE#2340])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_getfb@getfb2-accept-ccs.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg2-set2:     [PASS][88] -> [SKIP][89] ([Intel XE#455])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-463/igt@kms_hdr@invalid-hdr.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@static-swap:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#1503]) +1 other test skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-1/igt@kms_hdr@static-swap.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-dg2-set2:     NOTRUN -> [SKIP][91] ([Intel XE#346])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-432/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-dg2-set2:     NOTRUN -> [SKIP][92] ([Intel XE#4298])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][93] ([Intel XE#2927])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][94] ([Intel XE#2934])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-bmg:          NOTRUN -> [SKIP][95] ([Intel XE#2501])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-8/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-bmg:          NOTRUN -> [SKIP][96] ([Intel XE#2486])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-bmg:          NOTRUN -> [SKIP][97] ([Intel XE#4329])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][98] ([Intel XE#4359])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-433/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64:
    - shard-dg2-set2:     [PASS][99] -> [FAIL][100] ([Intel XE#616]) +3 other tests fail
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-434/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-436/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-6-size-64.html

  * igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256:
    - shard-dg2-set2:     NOTRUN -> [FAIL][101] ([Intel XE#616]) +3 other tests fail
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-464/igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-bmg:          NOTRUN -> [SKIP][102] ([Intel XE#5021])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-yf.html
    - shard-lnl:          NOTRUN -> [SKIP][103] ([Intel XE#4596])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-6/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-a:
    - shard-lnl:          NOTRUN -> [SKIP][104] ([Intel XE#2763]) +7 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-7/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-a.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-c:
    - shard-dg2-set2:     NOTRUN -> [SKIP][105] ([Intel XE#2763]) +2 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-c.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-d:
    - shard-dg2-set2:     NOTRUN -> [SKIP][106] ([Intel XE#2763] / [Intel XE#455])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-d.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d:
    - shard-bmg:          NOTRUN -> [SKIP][107] ([Intel XE#2763]) +9 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-dg2-set2:     NOTRUN -> [SKIP][108] ([Intel XE#870])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][109] ([Intel XE#2938])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-8/igt@kms_pm_backlight@brightness-with-dpms.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][110] ([Intel XE#2938])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-432/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-lnl:          [PASS][111] -> [FAIL][112] ([Intel XE#718]) +1 other test fail
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-lnl-1/igt@kms_pm_dc@dc6-psr.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-7/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-bmg:          NOTRUN -> [SKIP][113] ([Intel XE#2505])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-lnl:          NOTRUN -> [SKIP][114] ([Intel XE#1439] / [Intel XE#3141])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-2/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-bmg:          NOTRUN -> [SKIP][115] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-lnl:          NOTRUN -> [SKIP][116] ([Intel XE#2893] / [Intel XE#4608])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-4/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][117] ([Intel XE#4608]) +6 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-4/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][118] ([Intel XE#1489]) +12 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][119] ([Intel XE#1489]) +3 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-436/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][120] ([Intel XE#2387])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-8/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@fbc-psr2-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][121] ([Intel XE#2850] / [Intel XE#929]) +11 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-432/igt@kms_psr@fbc-psr2-dpms.html
    - shard-lnl:          NOTRUN -> [SKIP][122] ([Intel XE#1406]) +2 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-5/igt@kms_psr@fbc-psr2-dpms.html

  * igt@kms_psr@fbc-psr2-dpms@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][123] ([Intel XE#4609])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-5/igt@kms_psr@fbc-psr2-dpms@edp-1.html

  * igt@kms_psr@psr-primary-page-flip:
    - shard-bmg:          NOTRUN -> [SKIP][124] ([Intel XE#2234] / [Intel XE#2850]) +19 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-dg2-set2:     NOTRUN -> [SKIP][125] ([Intel XE#1127]) +1 other test skip
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-bmg:          NOTRUN -> [SKIP][126] ([Intel XE#3414] / [Intel XE#3904]) +2 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
    - shard-lnl:          NOTRUN -> [SKIP][127] ([Intel XE#3414] / [Intel XE#3904])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_scaling_modes@scaling-mode-full:
    - shard-bmg:          NOTRUN -> [SKIP][128] ([Intel XE#2413])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@kms_scaling_modes@scaling-mode-full.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-bmg:          NOTRUN -> [SKIP][129] ([Intel XE#1435]) +1 other test skip
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_setmode@basic@pipe-b-edp-1:
    - shard-lnl:          [PASS][130] -> [FAIL][131] ([Intel XE#2883]) +2 other tests fail
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-lnl-1/igt@kms_setmode@basic@pipe-b-edp-1.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-6/igt@kms_setmode@basic@pipe-b-edp-1.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          NOTRUN -> [SKIP][132] ([Intel XE#2426])
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vrr@lobf:
    - shard-bmg:          NOTRUN -> [SKIP][133] ([Intel XE#2168])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@kms_vrr@lobf.html

  * igt@kms_vrr@seamless-rr-switch-vrr:
    - shard-bmg:          NOTRUN -> [SKIP][134] ([Intel XE#1499])
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-8/igt@kms_vrr@seamless-rr-switch-vrr.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-lnl:          NOTRUN -> [SKIP][135] ([Intel XE#756])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-4/igt@kms_writeback@writeback-fb-id.html
    - shard-bmg:          NOTRUN -> [SKIP][136] ([Intel XE#756])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@kms_writeback@writeback-fb-id.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-dg2-set2:     NOTRUN -> [SKIP][137] ([Intel XE#756]) +1 other test skip
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@kms_writeback@writeback-pixel-formats.html

  * igt@sriov_basic@enable-vfs-autoprobe-off:
    - shard-bmg:          NOTRUN -> [SKIP][138] ([Intel XE#1091] / [Intel XE#2849])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@sriov_basic@enable-vfs-autoprobe-off.html

  * igt@xe_configfs@survivability-mode:
    - shard-lnl:          NOTRUN -> [SKIP][139] ([Intel XE#5084])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-1/igt@xe_configfs@survivability-mode.html

  * igt@xe_copy_basic@mem-copy-linear-0xfffe:
    - shard-dg2-set2:     NOTRUN -> [SKIP][140] ([Intel XE#1123])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@xe_copy_basic@mem-copy-linear-0xfffe.html

  * igt@xe_create@multigpu-create-massive-size:
    - shard-bmg:          NOTRUN -> [SKIP][141] ([Intel XE#2504])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-8/igt@xe_create@multigpu-create-massive-size.html

  * igt@xe_eu_stall@invalid-event-report-count:
    - shard-dg2-set2:     NOTRUN -> [SKIP][142] ([Intel XE#4497]) +1 other test skip
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@xe_eu_stall@invalid-event-report-count.html

  * igt@xe_eudebug_online@interrupt-all-set-breakpoint:
    - shard-lnl:          NOTRUN -> [SKIP][143] ([Intel XE#4837]) +7 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-8/igt@xe_eudebug_online@interrupt-all-set-breakpoint.html

  * igt@xe_eudebug_online@preempt-breakpoint:
    - shard-dg2-set2:     NOTRUN -> [SKIP][144] ([Intel XE#4837]) +5 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-433/igt@xe_eudebug_online@preempt-breakpoint.html

  * igt@xe_eudebug_online@single-step:
    - shard-bmg:          NOTRUN -> [SKIP][145] ([Intel XE#4837]) +18 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@xe_eudebug_online@single-step.html

  * igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd:
    - shard-lnl:          NOTRUN -> [SKIP][146] ([Intel XE#688])
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-8/igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr:
    - shard-dg2-set2:     [PASS][147] -> [SKIP][148] ([Intel XE#1392]) +1 other test skip
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-464/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][149] ([Intel XE#2322]) +12 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate:
    - shard-dg2-set2:     NOTRUN -> [SKIP][150] ([Intel XE#1392])
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_basic@multigpu-once-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][151] ([Intel XE#1392]) +2 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-5/igt@xe_exec_basic@multigpu-once-userptr-invalidate.html

  * igt@xe_exec_fault_mode@many-execqueues-basic-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][152] ([Intel XE#288]) +12 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@xe_exec_fault_mode@many-execqueues-basic-imm.html

  * igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence:
    - shard-dg2-set2:     NOTRUN -> [SKIP][153] ([Intel XE#2360])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence.html

  * igt@xe_exec_system_allocator@process-many-execqueues-mmap-new-huge:
    - shard-bmg:          NOTRUN -> [SKIP][154] ([Intel XE#4943]) +28 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@xe_exec_system_allocator@process-many-execqueues-mmap-new-huge.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset:
    - shard-lnl:          [PASS][155] -> [FAIL][156] ([Intel XE#5018]) +1 other test fail
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-lnl-1/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-8/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-malloc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][157] ([Intel XE#4915]) +150 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-436/igt@xe_exec_system_allocator@threads-shared-vm-many-large-malloc.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-new-huge-nomemset:
    - shard-lnl:          NOTRUN -> [SKIP][158] ([Intel XE#4943]) +6 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-7/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-new-huge-nomemset.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_add_hw_engine_class_defaults:
    - shard-lnl:          NOTRUN -> [ABORT][159] ([Intel XE#4757])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-8/igt@xe_fault_injection@inject-fault-probe-function-xe_add_hw_engine_class_defaults.html

  * igt@xe_noexec_ping_pong:
    - shard-lnl:          NOTRUN -> [SKIP][160] ([Intel XE#379])
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-1/igt@xe_noexec_ping_pong.html

  * igt@xe_oa@missing-sample-flags:
    - shard-dg2-set2:     NOTRUN -> [SKIP][161] ([Intel XE#2541] / [Intel XE#3573]) +4 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-464/igt@xe_oa@missing-sample-flags.html

  * igt@xe_oa@syncs-ufence-wait-cfg:
    - shard-dg2-set2:     NOTRUN -> [SKIP][162] ([Intel XE#2541] / [Intel XE#3573] / [Intel XE#4501])
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@xe_oa@syncs-ufence-wait-cfg.html

  * igt@xe_pat@pat-index-xehpc:
    - shard-bmg:          NOTRUN -> [SKIP][163] ([Intel XE#1420])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@xe_pat@pat-index-xehpc.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][164] ([Intel XE#2838] / [Intel XE#979])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@xe_pat@pat-index-xehpc.html
    - shard-lnl:          NOTRUN -> [SKIP][165] ([Intel XE#1420] / [Intel XE#2838])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-8/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-bmg:          NOTRUN -> [SKIP][166] ([Intel XE#2236])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_pm@d3cold-basic:
    - shard-lnl:          NOTRUN -> [SKIP][167] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-5/igt@xe_pm@d3cold-basic.html
    - shard-bmg:          NOTRUN -> [SKIP][168] ([Intel XE#2284])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-8/igt@xe_pm@d3cold-basic.html

  * igt@xe_pm@d3cold-mocs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][169] ([Intel XE#2284])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@xe_pm@d3cold-mocs.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-dg2-set2:     NOTRUN -> [SKIP][170] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-435/igt@xe_pm@s2idle-d3cold-basic-exec.html

  * igt@xe_pm@s3-vm-bind-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][171] ([Intel XE#584])
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-5/igt@xe_pm@s3-vm-bind-userptr.html

  * igt@xe_pm@s4-mocs:
    - shard-lnl:          [PASS][172] -> [ABORT][173] ([Intel XE#1794])
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-lnl-1/igt@xe_pm@s4-mocs.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-2/igt@xe_pm@s4-mocs.html

  * igt@xe_pmu@all-fn-engine-activity-load:
    - shard-lnl:          NOTRUN -> [SKIP][174] ([Intel XE#4650])
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-7/igt@xe_pmu@all-fn-engine-activity-load.html
    - shard-bmg:          NOTRUN -> [SKIP][175] ([Intel XE#4650])
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@xe_pmu@all-fn-engine-activity-load.html

  * igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy:
    - shard-bmg:          NOTRUN -> [SKIP][176] ([Intel XE#4733]) +1 other test skip
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy.html

  * igt@xe_pxp@pxp-stale-queue-post-suspend:
    - shard-dg2-set2:     NOTRUN -> [SKIP][177] ([Intel XE#4733])
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-464/igt@xe_pxp@pxp-stale-queue-post-suspend.html

  * igt@xe_query@multigpu-query-engines:
    - shard-dg2-set2:     NOTRUN -> [SKIP][178] ([Intel XE#944]) +2 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-432/igt@xe_query@multigpu-query-engines.html

  * igt@xe_query@multigpu-query-invalid-cs-cycles:
    - shard-bmg:          NOTRUN -> [SKIP][179] ([Intel XE#944]) +3 other tests skip
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-8/igt@xe_query@multigpu-query-invalid-cs-cycles.html

  * igt@xe_query@multigpu-query-topology-l3-bank-mask:
    - shard-lnl:          NOTRUN -> [SKIP][180] ([Intel XE#944]) +2 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-7/igt@xe_query@multigpu-query-topology-l3-bank-mask.html

  * igt@xe_spin_batch@spin-mem-copy:
    - shard-dg2-set2:     NOTRUN -> [SKIP][181] ([Intel XE#4821])
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@xe_spin_batch@spin-mem-copy.html

  * igt@xe_sriov_scheduling@equal-throughput:
    - shard-bmg:          NOTRUN -> [SKIP][182] ([Intel XE#4351])
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@xe_sriov_scheduling@equal-throughput.html

  
#### Possible fixes ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1:
    - shard-lnl:          [FAIL][183] ([Intel XE#911]) -> [PASS][184] +3 other tests pass
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-lnl-8/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-7/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html

  * igt@kms_bw@linear-tiling-1-displays-3840x2160p:
    - shard-lnl:          [ABORT][185] -> [PASS][186]
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-lnl-3/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-1/igt@kms_bw@linear-tiling-1-displays-3840x2160p.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-bmg:          [SKIP][187] ([Intel XE#2291]) -> [PASS][188] +2 other tests pass
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-1/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-bmg:          [SKIP][189] ([Intel XE#2316]) -> [PASS][190] +2 other tests pass
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-1/igt@kms_flip@2x-flip-vs-dpms.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-8/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a6-dp4:
    - shard-dg2-set2:     [FAIL][191] ([Intel XE#301]) -> [PASS][192] +8 other tests pass
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-464/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a6-dp4.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a6-dp4.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3:
    - shard-bmg:          [FAIL][193] ([Intel XE#3321]) -> [PASS][194] +1 other test pass
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@kms_flip@2x-flip-vs-expired-vblank@ac-dp2-hdmi-a3.html

  * igt@kms_flip@2x-plain-flip-ts-check:
    - shard-dg2-set2:     [FAIL][195] ([Intel XE#2882]) -> [PASS][196]
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@kms_flip@2x-plain-flip-ts-check.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@kms_flip@2x-plain-flip-ts-check.html

  * igt@kms_flip@flip-vs-expired-vblank@b-dp4:
    - shard-dg2-set2:     [FAIL][197] ([Intel XE#301] / [Intel XE#3321]) -> [PASS][198] +1 other test pass
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-463/igt@kms_flip@flip-vs-expired-vblank@b-dp4.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@b-dp4.html

  * igt@kms_flip@flip-vs-panning:
    - shard-bmg:          [DMESG-WARN][199] ([Intel XE#3428]) -> [PASS][200] +1 other test pass
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-6/igt@kms_flip@flip-vs-panning.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@kms_flip@flip-vs-panning.html

  * igt@kms_flip@wf_vblank-ts-check@a-edp1:
    - shard-lnl:          [FAIL][201] ([Intel XE#886]) -> [PASS][202] +1 other test pass
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-lnl-3/igt@kms_flip@wf_vblank-ts-check@a-edp1.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-5/igt@kms_flip@wf_vblank-ts-check@a-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
    - shard-dg2-set2:     [SKIP][203] ([Intel XE#2231] / [Intel XE#4208]) -> [PASS][204] +4 other tests pass
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_plane_alpha_blend@coverage-vs-premult-vs-constant:
    - shard-dg2-set2:     [SKIP][205] ([Intel XE#4208] / [i915#2575]) -> [PASS][206] +16 other tests pass
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@kms_plane_alpha_blend@coverage-vs-premult-vs-constant.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@kms_plane_alpha_blend@coverage-vs-premult-vs-constant.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-bmg:          [SKIP][207] ([Intel XE#4596]) -> [PASS][208]
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-1/igt@kms_plane_multiple@2x-tiling-x.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@xe_exec_basic@multigpu-once-null:
    - shard-dg2-set2:     [SKIP][209] ([Intel XE#1392]) -> [PASS][210] +3 other tests pass
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@xe_exec_basic@multigpu-once-null.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@xe_exec_basic@multigpu-once-null.html

  * igt@xe_module_load@load:
    - shard-dg2-set2:     ([PASS][211], [PASS][212], [PASS][213], [PASS][214], [PASS][215], [PASS][216], [PASS][217], [PASS][218], [PASS][219], [PASS][220], [PASS][221], [PASS][222], [PASS][223], [PASS][224], [PASS][225], [PASS][226], [PASS][227], [PASS][228], [PASS][229], [PASS][230], [SKIP][231], [PASS][232], [PASS][233], [PASS][234], [PASS][235], [PASS][236]) ([Intel XE#378]) -> ([PASS][237], [PASS][238], [PASS][239], [PASS][240], [PASS][241], [PASS][242], [PASS][243], [PASS][244], [PASS][245], [PASS][246], [PASS][247], [PASS][248], [PASS][249], [PASS][250], [PASS][251], [PASS][252], [PASS][253], [PASS][254], [PASS][255], [PASS][256], [PASS][257], [PASS][258], [PASS][259], [PASS][260], [PASS][261])
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-434/igt@xe_module_load@load.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@xe_module_load@load.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@xe_module_load@load.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-434/igt@xe_module_load@load.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-464/igt@xe_module_load@load.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-463/igt@xe_module_load@load.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-466/igt@xe_module_load@load.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-466/igt@xe_module_load@load.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-464/igt@xe_module_load@load.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-464/igt@xe_module_load@load.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-435/igt@xe_module_load@load.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-466/igt@xe_module_load@load.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-466/igt@xe_module_load@load.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-435/igt@xe_module_load@load.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-436/igt@xe_module_load@load.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-436/igt@xe_module_load@load.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@xe_module_load@load.html
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-436/igt@xe_module_load@load.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-436/igt@xe_module_load@load.html
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-463/igt@xe_module_load@load.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@xe_module_load@load.html
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-433/igt@xe_module_load@load.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-463/igt@xe_module_load@load.html
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-433/igt@xe_module_load@load.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@xe_module_load@load.html
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-463/igt@xe_module_load@load.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-435/igt@xe_module_load@load.html
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-436/igt@xe_module_load@load.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-436/igt@xe_module_load@load.html
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-436/igt@xe_module_load@load.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-433/igt@xe_module_load@load.html
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-464/igt@xe_module_load@load.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-464/igt@xe_module_load@load.html
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@xe_module_load@load.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-464/igt@xe_module_load@load.html
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@xe_module_load@load.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@xe_module_load@load.html
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@xe_module_load@load.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@xe_module_load@load.html
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@xe_module_load@load.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@xe_module_load@load.html
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@xe_module_load@load.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@xe_module_load@load.html
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@xe_module_load@load.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@xe_module_load@load.html
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@xe_module_load@load.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-432/igt@xe_module_load@load.html
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-432/igt@xe_module_load@load.html
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-432/igt@xe_module_load@load.html
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@xe_module_load@load.html
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-435/igt@xe_module_load@load.html

  * igt@xe_module_load@reload-no-display:
    - shard-bmg:          [INCOMPLETE][262] -> [PASS][263]
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-8/igt@xe_module_load@reload-no-display.html
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@xe_module_load@reload-no-display.html

  * igt@xe_pm@s4-basic:
    - shard-lnl:          [ABORT][264] ([Intel XE#1794]) -> [PASS][265]
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-lnl-2/igt@xe_pm@s4-basic.html
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-lnl-1/igt@xe_pm@s4-basic.html

  * igt@xe_vm@large-split-binds-536870912:
    - shard-dg2-set2:     [SKIP][266] ([Intel XE#4208]) -> [PASS][267] +25 other tests pass
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@xe_vm@large-split-binds-536870912.html
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-432/igt@xe_vm@large-split-binds-536870912.html

  
#### Warnings ####

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
    - shard-dg2-set2:     [SKIP][268] ([Intel XE#2231] / [Intel XE#4208]) -> [SKIP][269] ([Intel XE#1124])
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html

  * igt@kms_bw@linear-tiling-1-displays-1920x1080p:
    - shard-dg2-set2:     [SKIP][270] ([Intel XE#4208] / [i915#2575]) -> [SKIP][271] ([Intel XE#367])
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs:
    - shard-dg2-set2:     [SKIP][272] ([Intel XE#2231] / [Intel XE#4208]) -> [SKIP][273] ([Intel XE#455] / [Intel XE#787]) +3 other tests skip
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [SKIP][274] ([Intel XE#2231] / [Intel XE#4208]) -> [INCOMPLETE][275] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522])
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_chamelium_color@degamma:
    - shard-dg2-set2:     [SKIP][276] ([Intel XE#4208] / [i915#2575]) -> [SKIP][277] ([Intel XE#306])
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@kms_chamelium_color@degamma.html
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_hpd@common-hpd-after-hibernate:
    - shard-dg2-set2:     [SKIP][278] ([Intel XE#4208] / [i915#2575]) -> [SKIP][279] ([Intel XE#373])
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@kms_chamelium_hpd@common-hpd-after-hibernate.html
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@kms_chamelium_hpd@common-hpd-after-hibernate.html

  * igt@kms_content_protection@uevent:
    - shard-bmg:          [FAIL][280] ([Intel XE#1188]) -> [SKIP][281] ([Intel XE#2341])
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-4/igt@kms_content_protection@uevent.html
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_content_protection@uevent.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-dg2-set2:     [SKIP][282] ([Intel XE#2231] / [Intel XE#4208]) -> [SKIP][283] ([Intel XE#455])
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-432/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff:
    - shard-dg2-set2:     [SKIP][284] ([Intel XE#2231] / [Intel XE#4208]) -> [SKIP][285] ([Intel XE#651]) +4 other tests skip
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff.html
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
    - shard-bmg:          [SKIP][286] ([Intel XE#2312]) -> [SKIP][287] ([Intel XE#4141]) +2 other tests skip
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          [SKIP][288] ([Intel XE#4141]) -> [SKIP][289] ([Intel XE#2312]) +2 other tests skip
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][290] ([Intel XE#2312]) -> [SKIP][291] ([Intel XE#2311]) +3 other tests skip
   [290]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html
   [291]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][292] ([Intel XE#2311]) -> [SKIP][293] ([Intel XE#2312]) +7 other tests skip
   [292]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [293]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][294] ([Intel XE#2312]) -> [SKIP][295] ([Intel XE#2313]) +4 other tests skip
   [294]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html
   [295]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][296] ([Intel XE#2313]) -> [SKIP][297] ([Intel XE#2312]) +5 other tests skip
   [296]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
   [297]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render:
    - shard-dg2-set2:     [SKIP][298] ([Intel XE#2231] / [Intel XE#4208]) -> [SKIP][299] ([Intel XE#653]) +3 other tests skip
   [298]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html
   [299]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-dg2-set2:     [SKIP][300] ([Intel XE#4208] / [i915#2575]) -> [SKIP][301] ([Intel XE#5021])
   [300]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@kms_plane_multiple@2x-tiling-yf.html
   [301]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation:
    - shard-dg2-set2:     [SKIP][302] ([Intel XE#4208] / [i915#2575]) -> [SKIP][303] ([Intel XE#2763] / [Intel XE#455])
   [302]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html
   [303]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html

  * igt@kms_psr@psr2-cursor-plane-onoff:
    - shard-dg2-set2:     [SKIP][304] ([Intel XE#2231] / [Intel XE#4208]) -> [SKIP][305] ([Intel XE#2850] / [Intel XE#929]) +1 other test skip
   [304]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@kms_psr@psr2-cursor-plane-onoff.html
   [305]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@kms_psr@psr2-cursor-plane-onoff.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-dg2-set2:     [SKIP][306] ([Intel XE#4208] / [i915#2575]) -> [SKIP][307] ([Intel XE#3414])
   [306]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
   [307]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@xe_configfs@survivability-mode:
    - shard-dg2-set2:     [SKIP][308] ([Intel XE#4208]) -> [SKIP][309] ([Intel XE#5084])
   [308]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@xe_configfs@survivability-mode.html
   [309]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-436/igt@xe_configfs@survivability-mode.html

  * igt@xe_eudebug@discovery-race-vmbind:
    - shard-dg2-set2:     [SKIP][310] ([Intel XE#4208]) -> [SKIP][311] ([Intel XE#4837]) +1 other test skip
   [310]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@xe_eudebug@discovery-race-vmbind.html
   [311]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-435/igt@xe_eudebug@discovery-race-vmbind.html

  * igt@xe_exec_basic@multigpu-once-userptr-invalidate:
    - shard-dg2-set2:     [SKIP][312] ([Intel XE#4208]) -> [SKIP][313] ([Intel XE#1392])
   [312]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@xe_exec_basic@multigpu-once-userptr-invalidate.html
   [313]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-432/igt@xe_exec_basic@multigpu-once-userptr-invalidate.html

  * igt@xe_exec_fault_mode@twice-rebind-prefetch:
    - shard-dg2-set2:     [SKIP][314] ([Intel XE#4208]) -> [SKIP][315] ([Intel XE#288]) +2 other tests skip
   [314]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@xe_exec_fault_mode@twice-rebind-prefetch.html
   [315]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-434/igt@xe_exec_fault_mode@twice-rebind-prefetch.html

  * igt@xe_exec_system_allocator@process-many-free-race-nomemset:
    - shard-dg2-set2:     [SKIP][316] ([Intel XE#4208]) -> [SKIP][317] ([Intel XE#4915]) +35 other tests skip
   [316]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@xe_exec_system_allocator@process-many-free-race-nomemset.html
   [317]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@xe_exec_system_allocator@process-many-free-race-nomemset.html

  * igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-free-huge:
    - shard-dg2-set2:     [SKIP][318] ([Intel XE#4915]) -> [INCOMPLETE][319] ([Intel XE#2594])
   [318]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-466/igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-free-huge.html
   [319]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-free-huge.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][320], [PASS][321], [PASS][322], [PASS][323], [PASS][324], [PASS][325], [PASS][326], [PASS][327], [PASS][328], [PASS][329], [PASS][330], [PASS][331], [PASS][332], [PASS][333], [PASS][334], [PASS][335], [PASS][336], [PASS][337], [PASS][338], [PASS][339], [SKIP][340], [PASS][341], [PASS][342], [PASS][343], [PASS][344], [PASS][345]) ([Intel XE#2457]) -> ([PASS][346], [PASS][347], [PASS][348], [PASS][349], [PASS][350], [PASS][351], [PASS][352], [PASS][353], [PASS][354], [PASS][355], [PASS][356], [PASS][357], [PASS][358], [PASS][359], [PASS][360], [PASS][361], [PASS][362], [DMESG-WARN][363], [DMESG-WARN][364], [PASS][365], [DMESG-WARN][366], [PASS][367], [PASS][368], [PASS][369], [PASS][370]) ([Intel XE#3428])
   [320]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-4/igt@xe_module_load@load.html
   [321]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-1/igt@xe_module_load@load.html
   [322]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-5/igt@xe_module_load@load.html
   [323]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-2/igt@xe_module_load@load.html
   [324]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-5/igt@xe_module_load@load.html
   [325]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-5/igt@xe_module_load@load.html
   [326]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-5/igt@xe_module_load@load.html
   [327]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-5/igt@xe_module_load@load.html
   [328]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-5/igt@xe_module_load@load.html
   [329]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-1/igt@xe_module_load@load.html
   [330]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-8/igt@xe_module_load@load.html
   [331]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-8/igt@xe_module_load@load.html
   [332]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-8/igt@xe_module_load@load.html
   [333]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-6/igt@xe_module_load@load.html
   [334]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-6/igt@xe_module_load@load.html
   [335]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-5/igt@xe_module_load@load.html
   [336]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-4/igt@xe_module_load@load.html
   [337]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-4/igt@xe_module_load@load.html
   [338]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-4/igt@xe_module_load@load.html
   [339]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-6/igt@xe_module_load@load.html
   [340]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-6/igt@xe_module_load@load.html
   [341]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-2/igt@xe_module_load@load.html
   [342]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-1/igt@xe_module_load@load.html
   [343]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-1/igt@xe_module_load@load.html
   [344]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-5/igt@xe_module_load@load.html
   [345]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-bmg-1/igt@xe_module_load@load.html
   [346]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@xe_module_load@load.html
   [347]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@xe_module_load@load.html
   [348]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-5/igt@xe_module_load@load.html
   [349]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-5/igt@xe_module_load@load.html
   [350]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-5/igt@xe_module_load@load.html
   [351]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-2/igt@xe_module_load@load.html
   [352]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@xe_module_load@load.html
   [353]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-4/igt@xe_module_load@load.html
   [354]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-5/igt@xe_module_load@load.html
   [355]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-5/igt@xe_module_load@load.html
   [356]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-5/igt@xe_module_load@load.html
   [357]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-5/igt@xe_module_load@load.html
   [358]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@xe_module_load@load.html
   [359]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-8/igt@xe_module_load@load.html
   [360]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-8/igt@xe_module_load@load.html
   [361]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-8/igt@xe_module_load@load.html
   [362]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@xe_module_load@load.html
   [363]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@xe_module_load@load.html
   [364]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@xe_module_load@load.html
   [365]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@xe_module_load@load.html
   [366]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-6/igt@xe_module_load@load.html
   [367]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@xe_module_load@load.html
   [368]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@xe_module_load@load.html
   [369]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-1/igt@xe_module_load@load.html
   [370]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-bmg-5/igt@xe_module_load@load.html

  * igt@xe_peer2peer@write:
    - shard-dg2-set2:     [FAIL][371] ([Intel XE#1173]) -> [SKIP][372] ([Intel XE#1061])
   [371]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-433/igt@xe_peer2peer@write.html
   [372]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-432/igt@xe_peer2peer@write.html

  * igt@xe_query@multigpu-query-topology-l3-bank-mask:
    - shard-dg2-set2:     [SKIP][373] ([Intel XE#4208]) -> [SKIP][374] ([Intel XE#944])
   [373]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@xe_query@multigpu-query-topology-l3-bank-mask.html
   [374]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-466/igt@xe_query@multigpu-query-topology-l3-bank-mask.html

  * igt@xe_render_copy@render-stress-0-copies:
    - shard-dg2-set2:     [SKIP][375] ([Intel XE#4208]) -> [SKIP][376] ([Intel XE#4814])
   [375]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_8377/shard-dg2-432/igt@xe_render_copy@render-stress-0-copies.html
   [376]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/shard-dg2-463/igt@xe_render_copy@render-stress-0-copies.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
  [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1137]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1137
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1467]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1467
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2231
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2236]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2236
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2340
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#2372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2372
  [Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
  [Intel XE#2501]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2501
  [Intel XE#2504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2504
  [Intel XE#2505]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2505
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2594
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
  [Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
  [Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
  [Intel XE#2934]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2934
  [Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3428
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#379]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/379
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
  [Intel XE#4208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4208
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
  [Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4351
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4359]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4359
  [Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417
  [Intel XE#4497]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4497
  [Intel XE#4501]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4501
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
  [Intel XE#4683]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4683
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4757]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4757
  [Intel XE#4814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4814
  [Intel XE#4821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4821
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5018]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5018
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5084
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/873
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/911
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979
  [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575


Build changes
-------------

  * IGT: IGT_8377 -> IGTPW_13174

  IGTPW_13174: 8fb03fd8fec1b3e78e7892c91b7396b8201fa396 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  IGT_8377: b8dfaa900e3eadadfdba19f075157983d6dbd5b8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3131-dad3dc322768427e2ecb1a887cb3b710f8bc6848: dad3dc322768427e2ecb1a887cb3b710f8bc6848

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_13174/index.html

[-- Attachment #2: Type: text/html, Size: 106221 bytes --]

Re: [PATCH i-g-t v3 03/11] lib/intel_cmds_info: add blt_memop_mode (byte/page)

[Francois Dugast]

On Fri, May 23, 2025 at 10:01:18AM +0200, Zbigniew Kempczyński wrote:
> Add 'mode' field for further extending in tests. It is used for
> mem-copy linear type which supports copy mode in bytes or pages.
> 
> Cc: Francois Dugast <francois.dugast@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Reviewed-by: Francois Dugast <francois.dugast@intel.com>

> ---
>  lib/intel_blt.c             |  3 +++
>  lib/intel_blt.h             |  2 ++
>  lib/intel_cmds_info.h       | 11 +++++++++++
>  tests/intel/xe_copy_basic.c |  2 +-
>  4 files changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/intel_blt.c b/lib/intel_blt.c
> index 4c90d157c9..6bfaf09a2b 100644
> --- a/lib/intel_blt.c
> +++ b/lib/intel_blt.c
> @@ -1802,18 +1802,21 @@ int blt_fast_copy(int fd,
>   * blt_mem_copy_init:
>   * @fd: drm fd
>   * @mem: structure for initialization
> + * @mode: copy mode - byte or page (256B)
>   * @copy_type: linear or matrix
>   *
>   * Function is zeroing @mem and sets fd and driver fields (INTEL_DRIVER_I915 or
>   * INTEL_DRIVER_XE).
>   */
>  void blt_mem_copy_init(int fd, struct blt_mem_copy_data *mem,
> +		       enum blt_memop_mode mode,
>  		       enum blt_memop_type copy_type)
>  {
>  	memset(mem, 0, sizeof(*mem));
>  
>  	mem->fd = fd;
>  	mem->driver = get_intel_driver(fd);
> +	mem->mode = mode;
>  	mem->copy_type = copy_type;
>  }
>  
> diff --git a/lib/intel_blt.h b/lib/intel_blt.h
> index 9efa799881..f2509ab175 100644
> --- a/lib/intel_blt.h
> +++ b/lib/intel_blt.h
> @@ -130,6 +130,7 @@ struct blt_copy_data {
>  struct blt_mem_copy_data {
>  	int fd;
>  	enum intel_driver driver;
> +	enum blt_memop_mode mode;
>  	enum blt_memop_type copy_type;
>  	struct blt_mem_object src;
>  	struct blt_mem_object dst;
> @@ -274,6 +275,7 @@ int blt_fast_copy(int fd,
>  		  const struct blt_copy_data *blt);
>  
>  void blt_mem_copy_init(int fd, struct blt_mem_copy_data *mem,
> +		       enum blt_memop_mode mode,
>  		       enum blt_memop_type copy_type);
>  
>  void blt_mem_set_init(int fd, struct blt_mem_set_data *mem,
> diff --git a/lib/intel_cmds_info.h b/lib/intel_cmds_info.h
> index 88ba892645..17f60ce912 100644
> --- a/lib/intel_cmds_info.h
> +++ b/lib/intel_cmds_info.h
> @@ -30,6 +30,17 @@ enum blt_memop_type {
>  	TYPE_MATRIX,
>  };
>  
> +/**
> + * enum blt_memop_mode - memory operation mode mem-copy.
> + *
> + * Mem-copy with linear type supports mode operation in bytes or pages
> + * (page is 256B chunk).
> + */
> +enum blt_memop_mode {
> +	MODE_BYTE,
> +	MODE_PAGE,
> +};
> +
>  enum blt_cmd_type {
>  	SRC_COPY,
>  	MEM_SET,
> diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
> index 5681d4d6ab..f252d29fd4 100644
> --- a/tests/intel/xe_copy_basic.c
> +++ b/tests/intel/xe_copy_basic.c
> @@ -56,7 +56,7 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
>  
>  	bb = xe_bo_create(fd, 0, bb_size, region, 0);
>  
> -	blt_mem_copy_init(fd, &mem, TYPE_LINEAR);
> +	blt_mem_copy_init(fd, &mem, MODE_BYTE, TYPE_LINEAR);
>  	blt_set_mem_object(&mem.src, src_handle, size, width, width, height,
>  			   region, src_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
>  	blt_set_mem_object(&mem.dst, dst_handle, size, width, width, height,
> -- 
> 2.43.0
> 

Re: [PATCH i-g-t v3 06/11] tests/xe_copy_basic: replace size to rect which keeps objects geometry

[Francois Dugast]

On Fri, May 23, 2025 at 10:01:21AM +0200, Zbigniew Kempczyński wrote:
> Testing byte/page + linear/matrix mem-copy requires passing different
> pitch/width/height so replace simple size to geometry.
> 
> Change mem-copy and mem-set to use rect instead of size for
> copying bytes.
> 
> Cc: Francois Dugast <francois.dugast@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>  tests/intel/xe_copy_basic.c | 44 +++++++++++++++++++++++--------------
>  1 file changed, 28 insertions(+), 16 deletions(-)
> 
> diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
> index f252d29fd4..569f250cc4 100644
> --- a/tests/intel/xe_copy_basic.c
> +++ b/tests/intel/xe_copy_basic.c
> @@ -19,6 +19,13 @@
>  
>  #define MEM_FILL 0x8b
>  
> +struct rect {
> +	uint32_t pitch;
> +	uint32_t width;
> +	uint32_t height;
> +	enum blt_memop_mode mode;
> +};
> +
>  /**
>   * TEST: Test to validate copy commands on xe
>   * Category: Core
> @@ -42,7 +49,9 @@
>   */
>  static void
>  mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ctx,
> -	 uint32_t size, uint32_t width, uint32_t height, uint32_t region)
> +	 enum blt_memop_type type, enum blt_memop_mode mode,
> +	 uint32_t size, uint32_t pitch,
> +	 uint32_t width, uint32_t height, uint32_t region)

What is the point of adding those arguments here if they are not used
in mem_copy()? Should this be part of patch #8?

>  {
>  	struct blt_mem_copy_data mem = {};
>  	uint64_t bb_size = xe_bb_size(fd, SZ_4K);
> @@ -125,13 +134,15 @@ mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx, uint32_t size,
>  	munmap(mem.dst.ptr, size);
>  }
>  
> -static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd, uint32_t region)
> +static void copy_test(int fd, struct rect *rect, enum blt_cmd_type cmd, uint32_t region)
>  {
>  	struct drm_xe_engine_class_instance inst = {
>  		.engine_class = DRM_XE_ENGINE_CLASS_COPY,
>  	};
> -	uint32_t src_handle, dst_handle, vm, exec_queue, src_size, dst_size;
> -	uint32_t bo_size = ALIGN(size, xe_get_default_alignment(fd));
> +	uint32_t src_handle, dst_handle, vm, exec_queue;
> +	uint32_t pitch = rect->pitch ?: rect->width;
> +	uint32_t blocksize = rect->mode == MODE_PAGE ? pitch << 8 : pitch;
> +	uint32_t bo_size = ALIGN(blocksize * rect->height, xe_get_default_alignment(fd));
>  	intel_ctx_t *ctx;
>  
>  	src_handle = xe_bo_create(fd, 0, bo_size, region, 0);
> @@ -140,13 +151,11 @@ static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd, uint32_t reg
>  	exec_queue = xe_exec_queue_create(fd, vm, &inst, 0);
>  	ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0);
>  
> -	src_size = bo_size;
> -	dst_size = bo_size;
> -
>  	if (cmd == MEM_COPY)
> -		mem_copy(fd, src_handle, dst_handle, ctx, src_size, size, 1, region);
> +		mem_copy(fd, src_handle, dst_handle, ctx, TYPE_LINEAR, rect->mode,
> +			 bo_size, pitch, rect->width, rect->height, region);
>  	else if (cmd == MEM_SET)
> -		mem_set(fd, dst_handle, ctx, dst_size, size, 1, MEM_FILL, region);
> +		mem_set(fd, dst_handle, ctx, bo_size, rect->width, 1, MEM_FILL, region);
>  
>  	gem_close(fd, src_handle);
>  	gem_close(fd, dst_handle);
> @@ -160,7 +169,10 @@ igt_main
>  	int fd;
>  	struct igt_collection *set, *regions;
>  	uint32_t region;
> -	uint64_t size[] = {0xFD, 0x369, 0x3FFF, 0xFFFE};
> +	struct rect linear[] = { { 0, 0xfd, 1 },
> +				 { 0, 0x369, 1 },
> +				 { 0, 0x3fff, 1 },
> +				 { 0, 0xfffe, 1 } };
>  
>  	igt_fixture {
>  		fd = drm_open_driver(DRIVER_XE);
> @@ -170,22 +182,22 @@ igt_main
>  					       DRM_XE_MEM_REGION_CLASS_VRAM);
>  	}
>  
> -	for (int i = 0; i < ARRAY_SIZE(size); i++) {
> -		igt_subtest_f("mem-copy-linear-0x%"PRIx64"", size[i]) {
> +	for (int i = 0; i < ARRAY_SIZE(linear); i++) {
> +		igt_subtest_f("mem-copy-linear-0x%x", linear[i].width) {
>  			igt_require(blt_has_mem_copy(fd));
>  			for_each_variation_r(regions, 1, set) {
>  				region = igt_collection_get_value(regions, 0);
> -				copy_test(fd, size[i], MEM_COPY, region);
> +				copy_test(fd, &linear[i], MEM_COPY, region);
>  			}
>  		}
>  	}
>  
> -	for (int i = 0; i < ARRAY_SIZE(size); i++) {
> -		igt_subtest_f("mem-set-linear-0x%"PRIx64"", size[i]) {
> +	for (int i = 0; i < ARRAY_SIZE(linear); i++) {
> +		igt_subtest_f("mem-set-linear-0x%x", linear[i].width) {
>  			igt_require(blt_has_mem_set(fd));
>  			for_each_variation_r(regions, 1, set) {
>  				region = igt_collection_get_value(regions, 0);
> -				copy_test(fd, size[i], MEM_SET, region);
> +				copy_test(fd, &linear[i], MEM_SET, region);
>  			}
>  		}
>  	}
> -- 
> 2.43.0
> 

Re: [PATCH i-g-t v3 07/11] tests/xe_copy_basic: add testcase with large buffer size

[Francois Dugast]

On Fri, May 23, 2025 at 10:01:22AM +0200, Zbigniew Kempczyński wrote:
> Maximum possible size for mem-copy/byte is 256KiB. Verify intel_blt
> is able to emit multiple mem-copy commands to copy buffer which
> is larger than 256KiB.
> 
> Cc: Francois Dugast <francois.dugast@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Reviewed-by: Francois Dugast <francois.dugast@intel.com>

> ---
>  tests/intel/xe_copy_basic.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
> index 569f250cc4..bed3e39426 100644
> --- a/tests/intel/xe_copy_basic.c
> +++ b/tests/intel/xe_copy_basic.c
> @@ -46,6 +46,7 @@ struct rect {
>   * @0x3fff: 0x3fff
>   * @0xfd: 0xfd
>   * @0xfffe: 0xfffe
> + * @0x8fffe: 0x8fffe
>   */
>  static void
>  mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ctx,
> @@ -99,6 +100,7 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
>   * @0x3fff: 0x3fff
>   * @0xfd: 0xfd
>   * @0xfffe: 0xfffe
> + * @0x8fffe: 0x8fffe
>   */
>  static void
>  mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx, uint32_t size,
> @@ -172,7 +174,8 @@ igt_main
>  	struct rect linear[] = { { 0, 0xfd, 1 },
>  				 { 0, 0x369, 1 },
>  				 { 0, 0x3fff, 1 },
> -				 { 0, 0xfffe, 1 } };
> +				 { 0, 0xfffe, 1 },
> +				 { 0, 0x8fffe, 1 } };
>  
>  	igt_fixture {
>  		fd = drm_open_driver(DRIVER_XE);
> -- 
> 2.43.0
> 

Re: [PATCH i-g-t v3 08/11] tests/xe_copy_basic: add subtest to verify mem-copy in pages

[Francois Dugast]

On Fri, May 23, 2025 at 10:01:23AM +0200, Zbigniew Kempczyński wrote:
> Mem-copy in linear mode supports copying in 256B pages. Verify is
> it properly handled in intel_blt.
> 
> Cc: Francois Dugast <francois.dugast@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>  tests/intel/xe_copy_basic.c | 56 ++++++++++++++++++++++++++++++++++---
>  1 file changed, 52 insertions(+), 4 deletions(-)
> 
> diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
> index bed3e39426..404fe7f50a 100644
> --- a/tests/intel/xe_copy_basic.c
> +++ b/tests/intel/xe_copy_basic.c
> @@ -48,6 +48,20 @@ struct rect {
>   * @0xfffe: 0xfffe
>   * @0x8fffe: 0x8fffe
>   */
> +
> +/**
> + *
> + * SUBTEST: mem-page-copy-%s
> + * Description: Test validates MEM_COPY command, it takes various
                                                                     ^
Is something missing here? The line wrap is odd and after this series the
test description ends up being exactly the same for mem-copy-linear-%s,
mem-page-copy-%s and mem-matrix-copy-%s.

With that fixed:

    Reviewed-by: Francois Dugast <francois.dugast@intel.com>

> + *              parameters needed for the filling batch buffer for MEM_COPY command
> + *              with size %arg[1].
> + * Test category: functionality test
> + *
> + * arg[1]:
> + * @1: 1
> + * @17: 17
> + */
> +
>  static void
>  mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ctx,
>  	 enum blt_memop_type type, enum blt_memop_mode mode,
> @@ -62,23 +76,45 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
>  	uint8_t src_mocs = intel_get_uc_mocs_index(fd);
>  	uint8_t dst_mocs = src_mocs;
>  	uint32_t bb;
> -	int result;
> +	uint8_t *psrc, *pdst;
> +	int result, i;
>  
>  	bb = xe_bo_create(fd, 0, bb_size, region, 0);
>  
> -	blt_mem_copy_init(fd, &mem, MODE_BYTE, TYPE_LINEAR);
> +	blt_mem_copy_init(fd, &mem, mode, type);
>  	blt_set_mem_object(&mem.src, src_handle, size, width, width, height,
>  			   region, src_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
>  	blt_set_mem_object(&mem.dst, dst_handle, size, width, width, height,
>  			   region, dst_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
>  	mem.src.ptr = xe_bo_map(fd, src_handle, size);
>  	mem.dst.ptr = xe_bo_map(fd, dst_handle, size);
> +	psrc = (uint8_t *) mem.src.ptr;
> +	pdst = (uint8_t *) mem.dst.ptr;
> +
> +	srand(time(NULL));
> +
> +	/* Randomize whole src */
> +	for (i = 0; i < size; i++)
> +		psrc[i] = rand();
>  
>  	blt_set_batch(&mem.bb, bb, bb_size, region);
>  	igt_assert(mem.src.width == mem.dst.width);
>  
>  	blt_mem_copy(fd, ctx, NULL, ahnd, &mem);
> -	result = memcmp(mem.src.ptr, mem.dst.ptr, mem.src.size);
> +
> +	if (type == TYPE_LINEAR && mode == MODE_BYTE) {
> +		result = memcmp(psrc, pdst, width);
> +
> +		/* Rest of dst must contain 0 */
> +		for (i = width; i < size; i++) {
> +			if (pdst[i] != 0) {
> +				result = -1;
> +				break;
> +			}
> +		}
> +	} else {
> +		result = memcmp(psrc, pdst, pitch << 8);
> +	}
>  
>  	intel_allocator_bind(ahnd, 0, 0);
>  	munmap(mem.src.ptr, size);
> @@ -86,7 +122,7 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
>  	gem_close(fd, bb);
>  	put_ahnd(ahnd);
>  
> -	igt_assert_f(!result, "source and destination differ\n");
> +	igt_assert_f(!result, "destination doesn't contain valid data\n");
>  }
>  
>  /**
> @@ -176,6 +212,8 @@ igt_main
>  				 { 0, 0x3fff, 1 },
>  				 { 0, 0xfffe, 1 },
>  				 { 0, 0x8fffe, 1 } };
> +	struct rect page[] = { { 0, 1, 1, MODE_PAGE },
> +			       { 0, 17, 1, MODE_PAGE }};
>  
>  	igt_fixture {
>  		fd = drm_open_driver(DRIVER_XE);
> @@ -195,6 +233,16 @@ igt_main
>  		}
>  	}
>  
> +	for (int i = 0; i < ARRAY_SIZE(page); i++) {
> +		igt_subtest_f("mem-page-copy-%u", page[i].width) {
> +			igt_require(blt_has_mem_copy(fd));
> +			for_each_variation_r(regions, 1, set) {
> +				region = igt_collection_get_value(regions, 0);
> +				copy_test(fd, &page[i], MEM_COPY, region);
> +			}
> +		}
> +	}
> +
>  	for (int i = 0; i < ARRAY_SIZE(linear); i++) {
>  		igt_subtest_f("mem-set-linear-0x%x", linear[i].width) {
>  			igt_require(blt_has_mem_set(fd));
> -- 
> 2.43.0
> 

Re: [PATCH i-g-t v3 09/11] lib/intel_blt: add support for matrix mem-copy

[Francois Dugast]

On Fri, May 23, 2025 at 10:01:24AM +0200, Zbigniew Kempczyński wrote:
> Linear copy in intel_blt supports passing large buffers (which
> requires to be spread over couple mem-copies). For matrix this is
> a little bit more complicated so I left simple case in which

Patch LGTM but a nit: impersonal style is preferred over "I did X". 

With that:

    Reviewed-by: Francois Dugast <francois.dugast@intel.com>

> pitch/width/height must be within mem-copy command limits -
> 18-bit width * 18-bit height gives 64GiB object so testing
> copying bigger buffer would be an overkill.
> 
> Cc: Francois Dugast <francois.dugast@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>  lib/intel_blt.c | 69 +++++++++++++++++++++++++++++++++----------------
>  1 file changed, 47 insertions(+), 22 deletions(-)
> 
> diff --git a/lib/intel_blt.c b/lib/intel_blt.c
> index 265f5ed50f..77a03aff4e 100644
> --- a/lib/intel_blt.c
> +++ b/lib/intel_blt.c
> @@ -1893,17 +1893,18 @@ static uint64_t emit_blt_mem_copy(int fd, uint64_t ahnd,
>  {
>  	struct xe_mem_copy_data data = {};
>  	uint64_t dst_offset, src_offset, shift;
> -	uint32_t height, width_max, remain;
> +	uint32_t width, height, width_max, height_max, remain;
>  	uint32_t bbe = MI_BATCH_BUFFER_END;
>  	uint32_t *bb;
>  
>  	if (mem->mode == MODE_BYTE) {
>  		data.dw01.byte_copy.width = -1;
> -		width_max = data.dw01.byte_copy.width + 1;
> +		height_max = width_max = data.dw01.byte_copy.width + 1;
>  		shift = width_max;
>  	} else {
>  		data.dw01.page_copy.width = -1;
>  		width_max = data.dw01.page_copy.width + 1;
> +		height_max = 1;
>  		shift = width_max << 8;
>  	}
>  
> @@ -1914,6 +1915,7 @@ static uint64_t emit_blt_mem_copy(int fd, uint64_t ahnd,
>  
>  	bb = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
>  
> +	width = mem->src.width;
>  	height = mem->dst.height;
>  
>  	data.dw00.client = 0x2;
> @@ -1930,34 +1932,57 @@ static uint64_t emit_blt_mem_copy(int fd, uint64_t ahnd,
>  	data.dw09.src_mocs = mem->src.mocs_index;
>  	data.dw09.dst_mocs = mem->dst.mocs_index;
>  
> -	remain = mem->src.width;
> +	/* For matrix we don't iterate */
> +	if (mem->copy_type == TYPE_MATRIX) {
> +		if (width > width_max) {
> +			width = width_max;
> +			igt_warn("src width is bigger than max width [%u > %u => %u], truncating it\n",
> +				 mem->src.width, width_max, width);
> +		}
>  
> -	/* Truncate pitches to match operation bits */
> -	if (mem->src.pitch > width_max)
> -		data.dw03.src_pitch = width_max - 1;
> -	else
> -		data.dw03.src_pitch = mem->src.pitch;
> +		if (height > height_max) {
> +			height = height_max;
> +			igt_warn("src height is bigger than max height [%u > %u => %u], truncating it\n",
> +				 mem->src.height, height_max, height);
> +		}
>  
> -	if (mem->dst.pitch > width_max)
> -		data.dw04.dst_pitch = width_max - 1;
> -	else
> -		data.dw04.dst_pitch = mem->dst.pitch;
> -
> -	while (remain) {
> -		data.dw01.val = min_t(uint32_t, width_max, remain) - 1;
> +		data.dw01.byte_copy.width = width - 1;
> +		data.dw03.src_pitch = mem->src.pitch - 1;
> +		data.dw04.dst_pitch = mem->dst.pitch - 1;
>  
>  		igt_assert(bb_pos + sizeof(data) < mem->bb.size);
>  		memcpy(bb + bb_pos, &data, sizeof(data));
>  		bb_pos += sizeof(data);
> +	} else {
> +		remain = mem->src.width;
>  
> -		remain -= remain > width_max ? width_max : remain;
> -		src_offset += shift;
> -		dst_offset += shift;
> +		/* Truncate pitches to match operation bits */
> +		if (mem->src.pitch > width_max)
> +			data.dw03.src_pitch = width_max - 1;
> +		else
> +			data.dw03.src_pitch = mem->src.pitch;
>  
> -		data.dw05.src_address_lo = src_offset;
> -		data.dw06.src_address_hi = src_offset >> 32;
> -		data.dw07.dst_address_lo = dst_offset;
> -		data.dw08.dst_address_hi = dst_offset >> 32;
> +		if (mem->dst.pitch > width_max)
> +			data.dw04.dst_pitch = width_max - 1;
> +		else
> +			data.dw04.dst_pitch = mem->dst.pitch;
> +
> +		while (remain) {
> +			data.dw01.val = min_t(uint32_t, width_max, remain) - 1;
> +
> +			igt_assert(bb_pos + sizeof(data) < mem->bb.size);
> +			memcpy(bb + bb_pos, &data, sizeof(data));
> +			bb_pos += sizeof(data);
> +
> +			remain -= remain > width_max ? width_max : remain;
> +			src_offset += shift;
> +			dst_offset += shift;
> +
> +			data.dw05.src_address_lo = src_offset;
> +			data.dw06.src_address_hi = src_offset >> 32;
> +			data.dw07.dst_address_lo = dst_offset;
> +			data.dw08.dst_address_hi = dst_offset >> 32;
> +		}
>  	}
>  
>  	if (emit_bbe) {
> -- 
> 2.43.0
> 

Re: [PATCH i-g-t v3 10/11] tests/xe_copy_basic: add mem-copy matrix subtests

[Francois Dugast]

On Fri, May 23, 2025 at 10:01:25AM +0200, Zbigniew Kempczyński wrote:
> Verify intel_blt is able to properly copy matrix from one buffer
> to another.
> 
> Cc: Francois Dugast <francois.dugast@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
>  tests/intel/xe_copy_basic.c | 52 +++++++++++++++++++++++++++++++++----
>  1 file changed, 47 insertions(+), 5 deletions(-)
> 
> diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
> index 404fe7f50a..be400e3175 100644
> --- a/tests/intel/xe_copy_basic.c
> +++ b/tests/intel/xe_copy_basic.c
> @@ -62,6 +62,19 @@ struct rect {
>   * @17: 17
>   */
>  
> +/**
> + *
> + * SUBTEST: mem-matrix-copy-%s
> + * Description: Test validates MEM_COPY command, it takes various
> + *              parameters needed for the filling batch buffer for MEM_COPY command
> + *              with size %arg[1].

Please see comment on test description in patch #8.

With that:

    Reviewed-by: Francois Dugast <francois.dugast@intel.com>

> + * Test category: functionality test
> + *
> + * arg[1]:
> + * @2x2: 2x2
> + * @200x127: 200x127
> + */
> +
>  static void
>  mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ctx,
>  	 enum blt_memop_type type, enum blt_memop_mode mode,
> @@ -79,13 +92,17 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
>  	uint8_t *psrc, *pdst;
>  	int result, i;
>  
> +	igt_debug("size: %u, pitch: %u, width: %u, height: %u (type: %d, mode: %d)\n",
> +		  size, pitch, width, height, type, mode);
> +
>  	bb = xe_bo_create(fd, 0, bb_size, region, 0);
>  
>  	blt_mem_copy_init(fd, &mem, mode, type);
> -	blt_set_mem_object(&mem.src, src_handle, size, width, width, height,
> +	blt_set_mem_object(&mem.src, src_handle, size, pitch, width, height,
>  			   region, src_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
> -	blt_set_mem_object(&mem.dst, dst_handle, size, width, width, height,
> +	blt_set_mem_object(&mem.dst, dst_handle, size, pitch, width, height,
>  			   region, dst_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
> +
>  	mem.src.ptr = xe_bo_map(fd, src_handle, size);
>  	mem.dst.ptr = xe_bo_map(fd, dst_handle, size);
>  	psrc = (uint8_t *) mem.src.ptr;
> @@ -112,8 +129,20 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
>  				break;
>  			}
>  		}
> -	} else {
> +	} else if (type == TYPE_LINEAR && mode == MODE_PAGE) {
>  		result = memcmp(psrc, pdst, pitch << 8);
> +	} else {
> +		result = 0;
> +
> +		for (i = 0; i < pitch * height; i++) {
> +			if (i % pitch > width && pdst[i] != 0) {
> +				result = -1;
> +				break;
> +			} else if (i % pitch < width && psrc[i] != pdst[i]) {
> +				result = -1;
> +				break;
> +			}
> +		}
>  	}
>  
>  	intel_allocator_bind(ahnd, 0, 0);
> @@ -190,8 +219,10 @@ static void copy_test(int fd, struct rect *rect, enum blt_cmd_type cmd, uint32_t
>  	ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0);
>  
>  	if (cmd == MEM_COPY)
> -		mem_copy(fd, src_handle, dst_handle, ctx, TYPE_LINEAR, rect->mode,
> -			 bo_size, pitch, rect->width, rect->height, region);
> +		mem_copy(fd, src_handle, dst_handle, ctx,
> +			 rect->height > 1 ? TYPE_MATRIX : TYPE_LINEAR,
> +			 rect->mode, bo_size, pitch,
> +			 rect->width, rect->height, region);
>  	else if (cmd == MEM_SET)
>  		mem_set(fd, dst_handle, ctx, bo_size, rect->width, 1, MEM_FILL, region);
>  
> @@ -214,6 +245,7 @@ igt_main
>  				 { 0, 0x8fffe, 1 } };
>  	struct rect page[] = { { 0, 1, 1, MODE_PAGE },
>  			       { 0, 17, 1, MODE_PAGE }};
> +	struct rect matrix[] = { { 4, 2, 2 }, { 256, 200, 127 } };
>  
>  	igt_fixture {
>  		fd = drm_open_driver(DRIVER_XE);
> @@ -243,6 +275,16 @@ igt_main
>  		}
>  	}
>  
> +	for (int i = 0; i < ARRAY_SIZE(matrix); i++) {
> +		igt_subtest_f("mem-matrix-copy-%ux%u", matrix[i].width, matrix[i].height) {
> +			igt_require(blt_has_mem_copy(fd));
> +			for_each_variation_r(regions, 1, set) {
> +				region = igt_collection_get_value(regions, 0);
> +				copy_test(fd, &matrix[i], MEM_COPY, region);
> +			}
> +		}
> +	}
> +
>  	for (int i = 0; i < ARRAY_SIZE(linear); i++) {
>  		igt_subtest_f("mem-set-linear-0x%x", linear[i].width) {
>  			igt_require(blt_has_mem_set(fd));
> -- 
> 2.43.0
> 

Re: [PATCH i-g-t v3 11/11] lib/intel_blt: add mem-copy debug facility

[Francois Dugast]

On Fri, May 23, 2025 at 10:01:26AM +0200, Zbigniew Kempczyński wrote:
> Sometimes dumping batch with command is useful, especially during
> debugging. Basic functions in intel_blt like block-copy/fast-copy/
> surf-ctrl-copy) already have such batch dump code. Add similar
> function for mem-copy.
> 
> Cc: Francois Dugast <francois.dugast@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Reviewed-by: Francois Dugast <francois.dugast@intel.com>

> ---
>  lib/intel_blt.c             | 37 +++++++++++++++++++++++++++++++++++++
>  lib/intel_blt.h             |  1 +
>  tests/intel/xe_copy_basic.c | 28 +++++++++++++++++++++++++++-
>  3 files changed, 65 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/intel_blt.c b/lib/intel_blt.c
> index 77a03aff4e..8a05f482fd 100644
> --- a/lib/intel_blt.c
> +++ b/lib/intel_blt.c
> @@ -1887,6 +1887,33 @@ void blt_mem_copy_init(int fd, struct blt_mem_copy_data *mem,
>  	mem->copy_type = copy_type;
>  }
>  
> +static void dump_bb_mem_copy_cmd(struct xe_mem_copy_data *data)
> +{
> +	uint32_t *cmd = (uint32_t *) data;
> +
> +	igt_info("BB details:\n");
> +	igt_info(" dw00: [%08x] <client: 0x%x, opcode: 0x%x, length: %d> "
> +		 "[copy type: %d, mode: %d]\n",
> +		 cmd[0], data->dw00.client, data->dw00.opcode, data->dw00.length,
> +		 data->dw00.copy_type, data->dw00.mode);
> +	igt_info(" dw01: [%08x] width: %u\n", cmd[1],
> +		 data->dw00.mode == MODE_BYTE ? data->dw01.byte_copy.width :
> +						data->dw01.page_copy.width);
> +	igt_info(" dw02: [%08x] height: %u\n", cmd[2], data->dw02.height);
> +	igt_info(" dw03: [%08x] src pitch: %u\n", cmd[3], data->dw03.src_pitch);
> +	igt_info(" dw04: [%08x] dst pitch: %u\n", cmd[4], data->dw04.dst_pitch);
> +	igt_info(" dw05: [%08x] src offset lo (0x%x)\n",
> +		 cmd[5], data->dw05.src_address_lo);
> +	igt_info(" dw06: [%08x] src offset hi (0x%x)\n",
> +		 cmd[6], data->dw06.src_address_hi);
> +	igt_info(" dw07: [%08x] dst offset lo (0x%x)\n",
> +		 cmd[7], data->dw07.dst_address_lo);
> +	igt_info(" dw08: [%08x] dst offset hi (0x%x)\n",
> +		 cmd[8], data->dw08.dst_address_hi);
> +	igt_info(" dw09: [%08x] mocs <dst: 0x%x, src: 0x%x>\n",
> +		 cmd[8], data->dw09.dst_mocs, data->dw09.src_mocs);
> +}
> +
>  static uint64_t emit_blt_mem_copy(int fd, uint64_t ahnd,
>  				  const struct blt_mem_copy_data *mem,
>  				  uint64_t bb_pos, bool emit_bbe)
> @@ -1953,6 +1980,11 @@ static uint64_t emit_blt_mem_copy(int fd, uint64_t ahnd,
>  		igt_assert(bb_pos + sizeof(data) < mem->bb.size);
>  		memcpy(bb + bb_pos, &data, sizeof(data));
>  		bb_pos += sizeof(data);
> +
> +		if (mem->print_bb) {
> +			igt_info("[MEM COPY]\n");
> +			dump_bb_mem_copy_cmd(&data);
> +		}
>  	} else {
>  		remain = mem->src.width;
>  
> @@ -1982,6 +2014,11 @@ static uint64_t emit_blt_mem_copy(int fd, uint64_t ahnd,
>  			data.dw06.src_address_hi = src_offset >> 32;
>  			data.dw07.dst_address_lo = dst_offset;
>  			data.dw08.dst_address_hi = dst_offset >> 32;
> +
> +			if (mem->print_bb) {
> +				igt_info("[MEM COPY]\n");
> +				dump_bb_mem_copy_cmd(&data);
> +			}
>  		}
>  	}
>  
> diff --git a/lib/intel_blt.h b/lib/intel_blt.h
> index f2509ab175..54a096c039 100644
> --- a/lib/intel_blt.h
> +++ b/lib/intel_blt.h
> @@ -135,6 +135,7 @@ struct blt_mem_copy_data {
>  	struct blt_mem_object src;
>  	struct blt_mem_object dst;
>  	struct blt_copy_batch bb;
> +	bool print_bb;
>  };
>  
>  struct blt_mem_set_data {
> diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
> index be400e3175..bb1a4c536c 100644
> --- a/tests/intel/xe_copy_basic.c
> +++ b/tests/intel/xe_copy_basic.c
> @@ -19,6 +19,12 @@
>  
>  #define MEM_FILL 0x8b
>  
> +static struct param {
> +	bool print_bb;
> +} param = {
> +	.print_bb = false,
> +};
> +
>  struct rect {
>  	uint32_t pitch;
>  	uint32_t width;
> @@ -98,6 +104,8 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
>  	bb = xe_bo_create(fd, 0, bb_size, region, 0);
>  
>  	blt_mem_copy_init(fd, &mem, mode, type);
> +	mem.print_bb = param.print_bb;
> +
>  	blt_set_mem_object(&mem.src, src_handle, size, pitch, width, height,
>  			   region, src_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
>  	blt_set_mem_object(&mem.dst, dst_handle, size, pitch, width, height,
> @@ -233,7 +241,25 @@ static void copy_test(int fd, struct rect *rect, enum blt_cmd_type cmd, uint32_t
>  	free(ctx);
>  }
>  
> -igt_main
> +static int opt_handler(int opt, int opt_index, void *data)
> +{
> +	switch (opt) {
> +	case 'b':
> +		param.print_bb = true;
> +		igt_debug("Print bb: %d\n", param.print_bb);
> +		break;
> +	default:
> +		return IGT_OPT_HANDLER_ERROR;
> +	}
> +
> +	return IGT_OPT_HANDLER_SUCCESS;
> +}
> +
> +const char *help_str =
> +	"  -b\tPrint bb"
> +	;
> +
> +igt_main_args("b", NULL, help_str, opt_handler, NULL)
>  {
>  	int fd;
>  	struct igt_collection *set, *regions;
> -- 
> 2.43.0
> 

Re: [PATCH i-g-t v3 06/11] tests/xe_copy_basic: replace size to rect which keeps objects geometry

[Zbigniew Kempczyński]

On Tue, May 27, 2025 at 09:15:14PM +0200, Francois Dugast wrote:
> On Fri, May 23, 2025 at 10:01:21AM +0200, Zbigniew Kempczyński wrote:
> > Testing byte/page + linear/matrix mem-copy requires passing different
> > pitch/width/height so replace simple size to geometry.
> > 
> > Change mem-copy and mem-set to use rect instead of size for
> > copying bytes.
> > 
> > Cc: Francois Dugast <francois.dugast@intel.com>
> > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > ---
> >  tests/intel/xe_copy_basic.c | 44 +++++++++++++++++++++++--------------
> >  1 file changed, 28 insertions(+), 16 deletions(-)
> > 
> > diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
> > index f252d29fd4..569f250cc4 100644
> > --- a/tests/intel/xe_copy_basic.c
> > +++ b/tests/intel/xe_copy_basic.c
> > @@ -19,6 +19,13 @@
> >  
> >  #define MEM_FILL 0x8b
> >  
> > +struct rect {
> > +	uint32_t pitch;
> > +	uint32_t width;
> > +	uint32_t height;
> > +	enum blt_memop_mode mode;
> > +};
> > +
> >  /**
> >   * TEST: Test to validate copy commands on xe
> >   * Category: Core
> > @@ -42,7 +49,9 @@
> >   */
> >  static void
> >  mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ctx,
> > -	 uint32_t size, uint32_t width, uint32_t height, uint32_t region)
> > +	 enum blt_memop_type type, enum blt_memop_mode mode,
> > +	 uint32_t size, uint32_t pitch,
> > +	 uint32_t width, uint32_t height, uint32_t region)
> 
> What is the point of adding those arguments here if they are not used
> in mem_copy()? Should this be part of patch #8?

You're right. I need to fix patches division because these arguments
are not used here. I'm going to fix this in the next revision.

Thank you for spotting this in the review.

--
Zbigniew

> 
> >  {
> >  	struct blt_mem_copy_data mem = {};
> >  	uint64_t bb_size = xe_bb_size(fd, SZ_4K);
> > @@ -125,13 +134,15 @@ mem_set(int fd, uint32_t dst_handle, const intel_ctx_t *ctx, uint32_t size,
> >  	munmap(mem.dst.ptr, size);
> >  }
> >  
> > -static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd, uint32_t region)
> > +static void copy_test(int fd, struct rect *rect, enum blt_cmd_type cmd, uint32_t region)
> >  {
> >  	struct drm_xe_engine_class_instance inst = {
> >  		.engine_class = DRM_XE_ENGINE_CLASS_COPY,
> >  	};
> > -	uint32_t src_handle, dst_handle, vm, exec_queue, src_size, dst_size;
> > -	uint32_t bo_size = ALIGN(size, xe_get_default_alignment(fd));
> > +	uint32_t src_handle, dst_handle, vm, exec_queue;
> > +	uint32_t pitch = rect->pitch ?: rect->width;
> > +	uint32_t blocksize = rect->mode == MODE_PAGE ? pitch << 8 : pitch;
> > +	uint32_t bo_size = ALIGN(blocksize * rect->height, xe_get_default_alignment(fd));
> >  	intel_ctx_t *ctx;
> >  
> >  	src_handle = xe_bo_create(fd, 0, bo_size, region, 0);
> > @@ -140,13 +151,11 @@ static void copy_test(int fd, uint32_t size, enum blt_cmd_type cmd, uint32_t reg
> >  	exec_queue = xe_exec_queue_create(fd, vm, &inst, 0);
> >  	ctx = intel_ctx_xe(fd, vm, exec_queue, 0, 0, 0);
> >  
> > -	src_size = bo_size;
> > -	dst_size = bo_size;
> > -
> >  	if (cmd == MEM_COPY)
> > -		mem_copy(fd, src_handle, dst_handle, ctx, src_size, size, 1, region);
> > +		mem_copy(fd, src_handle, dst_handle, ctx, TYPE_LINEAR, rect->mode,
> > +			 bo_size, pitch, rect->width, rect->height, region);
> >  	else if (cmd == MEM_SET)
> > -		mem_set(fd, dst_handle, ctx, dst_size, size, 1, MEM_FILL, region);
> > +		mem_set(fd, dst_handle, ctx, bo_size, rect->width, 1, MEM_FILL, region);
> >  
> >  	gem_close(fd, src_handle);
> >  	gem_close(fd, dst_handle);
> > @@ -160,7 +169,10 @@ igt_main
> >  	int fd;
> >  	struct igt_collection *set, *regions;
> >  	uint32_t region;
> > -	uint64_t size[] = {0xFD, 0x369, 0x3FFF, 0xFFFE};
> > +	struct rect linear[] = { { 0, 0xfd, 1 },
> > +				 { 0, 0x369, 1 },
> > +				 { 0, 0x3fff, 1 },
> > +				 { 0, 0xfffe, 1 } };
> >  
> >  	igt_fixture {
> >  		fd = drm_open_driver(DRIVER_XE);
> > @@ -170,22 +182,22 @@ igt_main
> >  					       DRM_XE_MEM_REGION_CLASS_VRAM);
> >  	}
> >  
> > -	for (int i = 0; i < ARRAY_SIZE(size); i++) {
> > -		igt_subtest_f("mem-copy-linear-0x%"PRIx64"", size[i]) {
> > +	for (int i = 0; i < ARRAY_SIZE(linear); i++) {
> > +		igt_subtest_f("mem-copy-linear-0x%x", linear[i].width) {
> >  			igt_require(blt_has_mem_copy(fd));
> >  			for_each_variation_r(regions, 1, set) {
> >  				region = igt_collection_get_value(regions, 0);
> > -				copy_test(fd, size[i], MEM_COPY, region);
> > +				copy_test(fd, &linear[i], MEM_COPY, region);
> >  			}
> >  		}
> >  	}
> >  
> > -	for (int i = 0; i < ARRAY_SIZE(size); i++) {
> > -		igt_subtest_f("mem-set-linear-0x%"PRIx64"", size[i]) {
> > +	for (int i = 0; i < ARRAY_SIZE(linear); i++) {
> > +		igt_subtest_f("mem-set-linear-0x%x", linear[i].width) {
> >  			igt_require(blt_has_mem_set(fd));
> >  			for_each_variation_r(regions, 1, set) {
> >  				region = igt_collection_get_value(regions, 0);
> > -				copy_test(fd, size[i], MEM_SET, region);
> > +				copy_test(fd, &linear[i], MEM_SET, region);
> >  			}
> >  		}
> >  	}
> > -- 
> > 2.43.0
> > 

Re: [PATCH i-g-t v3 08/11] tests/xe_copy_basic: add subtest to verify mem-copy in pages

[Zbigniew Kempczyński]

On Tue, May 27, 2025 at 09:23:58PM +0200, Francois Dugast wrote:
> On Fri, May 23, 2025 at 10:01:23AM +0200, Zbigniew Kempczyński wrote:
> > Mem-copy in linear mode supports copying in 256B pages. Verify is
> > it properly handled in intel_blt.
> > 
> > Cc: Francois Dugast <francois.dugast@intel.com>
> > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > ---
> >  tests/intel/xe_copy_basic.c | 56 ++++++++++++++++++++++++++++++++++---
> >  1 file changed, 52 insertions(+), 4 deletions(-)
> > 
> > diff --git a/tests/intel/xe_copy_basic.c b/tests/intel/xe_copy_basic.c
> > index bed3e39426..404fe7f50a 100644
> > --- a/tests/intel/xe_copy_basic.c
> > +++ b/tests/intel/xe_copy_basic.c
> > @@ -48,6 +48,20 @@ struct rect {
> >   * @0xfffe: 0xfffe
> >   * @0x8fffe: 0x8fffe
> >   */
> > +
> > +/**
> > + *
> > + * SUBTEST: mem-page-copy-%s
> > + * Description: Test validates MEM_COPY command, it takes various
>                                                                      ^
> Is something missing here? The line wrap is odd and after this series the
> test description ends up being exactly the same for mem-copy-linear-%s,
> mem-page-copy-%s and mem-matrix-copy-%s.

Right, copy-paste issue, check in the next revision if you have nothing
against new description. Assuming no - r-b applied.

--
Zbigniew

> 
> With that fixed:
> 
>     Reviewed-by: Francois Dugast <francois.dugast@intel.com>
> 
> > + *              parameters needed for the filling batch buffer for MEM_COPY command
> > + *              with size %arg[1].
> > + * Test category: functionality test
> > + *
> > + * arg[1]:
> > + * @1: 1
> > + * @17: 17
> > + */
> > +
> >  static void
> >  mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ctx,
> >  	 enum blt_memop_type type, enum blt_memop_mode mode,
> > @@ -62,23 +76,45 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
> >  	uint8_t src_mocs = intel_get_uc_mocs_index(fd);
> >  	uint8_t dst_mocs = src_mocs;
> >  	uint32_t bb;
> > -	int result;
> > +	uint8_t *psrc, *pdst;
> > +	int result, i;
> >  
> >  	bb = xe_bo_create(fd, 0, bb_size, region, 0);
> >  
> > -	blt_mem_copy_init(fd, &mem, MODE_BYTE, TYPE_LINEAR);
> > +	blt_mem_copy_init(fd, &mem, mode, type);
> >  	blt_set_mem_object(&mem.src, src_handle, size, width, width, height,
> >  			   region, src_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
> >  	blt_set_mem_object(&mem.dst, dst_handle, size, width, width, height,
> >  			   region, dst_mocs, DEFAULT_PAT_INDEX, COMPRESSION_DISABLED);
> >  	mem.src.ptr = xe_bo_map(fd, src_handle, size);
> >  	mem.dst.ptr = xe_bo_map(fd, dst_handle, size);
> > +	psrc = (uint8_t *) mem.src.ptr;
> > +	pdst = (uint8_t *) mem.dst.ptr;
> > +
> > +	srand(time(NULL));
> > +
> > +	/* Randomize whole src */
> > +	for (i = 0; i < size; i++)
> > +		psrc[i] = rand();
> >  
> >  	blt_set_batch(&mem.bb, bb, bb_size, region);
> >  	igt_assert(mem.src.width == mem.dst.width);
> >  
> >  	blt_mem_copy(fd, ctx, NULL, ahnd, &mem);
> > -	result = memcmp(mem.src.ptr, mem.dst.ptr, mem.src.size);
> > +
> > +	if (type == TYPE_LINEAR && mode == MODE_BYTE) {
> > +		result = memcmp(psrc, pdst, width);
> > +
> > +		/* Rest of dst must contain 0 */
> > +		for (i = width; i < size; i++) {
> > +			if (pdst[i] != 0) {
> > +				result = -1;
> > +				break;
> > +			}
> > +		}
> > +	} else {
> > +		result = memcmp(psrc, pdst, pitch << 8);
> > +	}
> >  
> >  	intel_allocator_bind(ahnd, 0, 0);
> >  	munmap(mem.src.ptr, size);
> > @@ -86,7 +122,7 @@ mem_copy(int fd, uint32_t src_handle, uint32_t dst_handle, const intel_ctx_t *ct
> >  	gem_close(fd, bb);
> >  	put_ahnd(ahnd);
> >  
> > -	igt_assert_f(!result, "source and destination differ\n");
> > +	igt_assert_f(!result, "destination doesn't contain valid data\n");
> >  }
> >  
> >  /**
> > @@ -176,6 +212,8 @@ igt_main
> >  				 { 0, 0x3fff, 1 },
> >  				 { 0, 0xfffe, 1 },
> >  				 { 0, 0x8fffe, 1 } };
> > +	struct rect page[] = { { 0, 1, 1, MODE_PAGE },
> > +			       { 0, 17, 1, MODE_PAGE }};
> >  
> >  	igt_fixture {
> >  		fd = drm_open_driver(DRIVER_XE);
> > @@ -195,6 +233,16 @@ igt_main
> >  		}
> >  	}
> >  
> > +	for (int i = 0; i < ARRAY_SIZE(page); i++) {
> > +		igt_subtest_f("mem-page-copy-%u", page[i].width) {
> > +			igt_require(blt_has_mem_copy(fd));
> > +			for_each_variation_r(regions, 1, set) {
> > +				region = igt_collection_get_value(regions, 0);
> > +				copy_test(fd, &page[i], MEM_COPY, region);
> > +			}
> > +		}
> > +	}
> > +
> >  	for (int i = 0; i < ARRAY_SIZE(linear); i++) {
> >  		igt_subtest_f("mem-set-linear-0x%x", linear[i].width) {
> >  			igt_require(blt_has_mem_set(fd));
> > -- 
> > 2.43.0
> > 

Re: [PATCH i-g-t v3 09/11] lib/intel_blt: add support for matrix mem-copy

[Zbigniew Kempczyński]

On Wed, May 28, 2025 at 10:23:41AM +0200, Francois Dugast wrote:
> On Fri, May 23, 2025 at 10:01:24AM +0200, Zbigniew Kempczyński wrote:
> > Linear copy in intel_blt supports passing large buffers (which
> > requires to be spread over couple mem-copies). For matrix this is
> > a little bit more complicated so I left simple case in which
> 
> Patch LGTM but a nit: impersonal style is preferred over "I did X". 

Ok, reprhased this. Check if it is ok now, anyway I applied r-b.

--
Zbigniew

> 
> With that:
> 
>     Reviewed-by: Francois Dugast <francois.dugast@intel.com>
> 
> > pitch/width/height must be within mem-copy command limits -
> > 18-bit width * 18-bit height gives 64GiB object so testing
> > copying bigger buffer would be an overkill.
> > 
> > Cc: Francois Dugast <francois.dugast@intel.com>
> > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > ---
> >  lib/intel_blt.c | 69 +++++++++++++++++++++++++++++++++----------------
> >  1 file changed, 47 insertions(+), 22 deletions(-)
> > 
> > diff --git a/lib/intel_blt.c b/lib/intel_blt.c
> > index 265f5ed50f..77a03aff4e 100644
> > --- a/lib/intel_blt.c
> > +++ b/lib/intel_blt.c
> > @@ -1893,17 +1893,18 @@ static uint64_t emit_blt_mem_copy(int fd, uint64_t ahnd,
> >  {
> >  	struct xe_mem_copy_data data = {};
> >  	uint64_t dst_offset, src_offset, shift;
> > -	uint32_t height, width_max, remain;
> > +	uint32_t width, height, width_max, height_max, remain;
> >  	uint32_t bbe = MI_BATCH_BUFFER_END;
> >  	uint32_t *bb;
> >  
> >  	if (mem->mode == MODE_BYTE) {
> >  		data.dw01.byte_copy.width = -1;
> > -		width_max = data.dw01.byte_copy.width + 1;
> > +		height_max = width_max = data.dw01.byte_copy.width + 1;
> >  		shift = width_max;
> >  	} else {
> >  		data.dw01.page_copy.width = -1;
> >  		width_max = data.dw01.page_copy.width + 1;
> > +		height_max = 1;
> >  		shift = width_max << 8;
> >  	}
> >  
> > @@ -1914,6 +1915,7 @@ static uint64_t emit_blt_mem_copy(int fd, uint64_t ahnd,
> >  
> >  	bb = bo_map(fd, mem->bb.handle, mem->bb.size, mem->driver);
> >  
> > +	width = mem->src.width;
> >  	height = mem->dst.height;
> >  
> >  	data.dw00.client = 0x2;
> > @@ -1930,34 +1932,57 @@ static uint64_t emit_blt_mem_copy(int fd, uint64_t ahnd,
> >  	data.dw09.src_mocs = mem->src.mocs_index;
> >  	data.dw09.dst_mocs = mem->dst.mocs_index;
> >  
> > -	remain = mem->src.width;
> > +	/* For matrix we don't iterate */
> > +	if (mem->copy_type == TYPE_MATRIX) {
> > +		if (width > width_max) {
> > +			width = width_max;
> > +			igt_warn("src width is bigger than max width [%u > %u => %u], truncating it\n",
> > +				 mem->src.width, width_max, width);
> > +		}
> >  
> > -	/* Truncate pitches to match operation bits */
> > -	if (mem->src.pitch > width_max)
> > -		data.dw03.src_pitch = width_max - 1;
> > -	else
> > -		data.dw03.src_pitch = mem->src.pitch;
> > +		if (height > height_max) {
> > +			height = height_max;
> > +			igt_warn("src height is bigger than max height [%u > %u => %u], truncating it\n",
> > +				 mem->src.height, height_max, height);
> > +		}
> >  
> > -	if (mem->dst.pitch > width_max)
> > -		data.dw04.dst_pitch = width_max - 1;
> > -	else
> > -		data.dw04.dst_pitch = mem->dst.pitch;
> > -
> > -	while (remain) {
> > -		data.dw01.val = min_t(uint32_t, width_max, remain) - 1;
> > +		data.dw01.byte_copy.width = width - 1;
> > +		data.dw03.src_pitch = mem->src.pitch - 1;
> > +		data.dw04.dst_pitch = mem->dst.pitch - 1;
> >  
> >  		igt_assert(bb_pos + sizeof(data) < mem->bb.size);
> >  		memcpy(bb + bb_pos, &data, sizeof(data));
> >  		bb_pos += sizeof(data);
> > +	} else {
> > +		remain = mem->src.width;
> >  
> > -		remain -= remain > width_max ? width_max : remain;
> > -		src_offset += shift;
> > -		dst_offset += shift;
> > +		/* Truncate pitches to match operation bits */
> > +		if (mem->src.pitch > width_max)
> > +			data.dw03.src_pitch = width_max - 1;
> > +		else
> > +			data.dw03.src_pitch = mem->src.pitch;
> >  
> > -		data.dw05.src_address_lo = src_offset;
> > -		data.dw06.src_address_hi = src_offset >> 32;
> > -		data.dw07.dst_address_lo = dst_offset;
> > -		data.dw08.dst_address_hi = dst_offset >> 32;
> > +		if (mem->dst.pitch > width_max)
> > +			data.dw04.dst_pitch = width_max - 1;
> > +		else
> > +			data.dw04.dst_pitch = mem->dst.pitch;
> > +
> > +		while (remain) {
> > +			data.dw01.val = min_t(uint32_t, width_max, remain) - 1;
> > +
> > +			igt_assert(bb_pos + sizeof(data) < mem->bb.size);
> > +			memcpy(bb + bb_pos, &data, sizeof(data));
> > +			bb_pos += sizeof(data);
> > +
> > +			remain -= remain > width_max ? width_max : remain;
> > +			src_offset += shift;
> > +			dst_offset += shift;
> > +
> > +			data.dw05.src_address_lo = src_offset;
> > +			data.dw06.src_address_hi = src_offset >> 32;
> > +			data.dw07.dst_address_lo = dst_offset;
> > +			data.dw08.dst_address_hi = dst_offset >> 32;
> > +		}
> >  	}
> >  
> >  	if (emit_bbe) {
> > -- 
> > 2.43.0
> >