Re: [PATCH v3 2/2] PCI: Fix runtime PM usage count underflow on device unplug

[Lukas Wunner <lukas@wunner.de>]

On Mon, Jun 23, 2025 at 06:37:33AM -0500, Mario Limonciello wrote:
> On 6/23/25 5:11 AM, Rafael J. Wysocki wrote:
> > On Mon, Jun 23, 2025 at 12:05???PM Lukas Wunner <lukas@wunner.de> wrote:
> > > On Mon, Jun 23, 2025 at 09:37:07AM +0200, Lukas Wunner wrote:
> > > > On Mon, Jun 23, 2025 at 08:43:25AM +0200, Lukas Wunner wrote:
> > > > > On Sun, Jun 22, 2025 at 01:39:26PM -0500, Mario Limonciello wrote:
> > > > > > I did this check and yes specifically on this PCIe port with
> > > > > > the underflow the d3 possible lookup returns false during
> > > > > > pcie_portdrv_remove().  It returns true during
> > > > > > pcie_portdrv_probe().
> > > > > 
> > > > > That's not supposed to happen.  The expectation is that
> > > > > pci_bridge_d3_possible() always returns the same value.
> > > > 
> > > > I'm wondering if the patch below fixes the issue?
> 
> Yes this works, thanks!

Could you still check what the value read from the Slot Capabilities
register is in pciehp_is_native() (if the patch is not applied)?

I guess it must be something else than "all ones" and I'd like to
understand why.

Thanks,

Lukas