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From: Paul Kocialkowski <paulk@sys-base.io>
To: Parthiban Nallathambi <parthiban@linumiz.com>
Cc: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	Samuel Holland <samuel@sholland.org>,
	Maxime Ripard <mripard@kernel.org>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Linus Walleij <linus.walleij@linaro.org>,
	Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	iommu@lists.linux.dev, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
	dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org,
	linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH 17/22] phy: allwinner: phy-sun6i-mipi-dphy: add LVDS support
Date: Wed, 25 Jun 2025 10:41:56 +0200	[thread overview]
Message-ID: <aFu2VBhCIEdLIPv3@shepard> (raw)
In-Reply-To: <20241227-a133-display-support-v1-17-13b52f71fb14@linumiz.com>

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Hi,

Thanks for your work on this!

On Fri 27 Dec 24, 16:38, Parthiban Nallathambi wrote:
> DPHY in A100/A133 supports both LVDS and DSI. Combo phy register
> have BIT(2) for enabling LVDS specifically, but enabling it alone
> isn't functional.
> 
> Both MIPI and LVDS needs to be enabled in the combo phy to get
> the display working under LVDS mode. There is no specific enable
> bit for LVDS apart from the one in combo phy. MIPI got enable
> control in analog 4 register which must be disabled when using
> in LVDS mode.
> 
> Introduce set_mode in phy ops to control only for MIPI DSI.

Similar work was already submitted for D1/T113-S3 LVDS support, which seems to
be the exact same situation as the A133.

See: https://patchwork.freedesktop.org/series/145276/

I just made a review of that series and find it more elegant in various ways
(especially since configuring the registers in set_mode is not the right place).
So you probably want to follow-up on that series instead.

Note that both D1/T113-S3 and A133 support a second LVDS output, LVDS1, which
uses the traditional TCON0 LVDS PHY. It would be great to be able to support
both outputs as well as dual-link modes!

All the best,

Paul

> Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
> ---
>  drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 23 +++++++++++++++++++----
>  1 file changed, 19 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> index 36eab95271b2..d164b2ea5dfd 100644
> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> @@ -314,13 +314,11 @@ static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
>  	/* Disable sigma-delta modulation. */
>  	regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0);
>  
> -	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
> -			   SUN6I_DPHY_ANA4_REG_EN_MIPI,
> -			   SUN6I_DPHY_ANA4_REG_EN_MIPI);
> -
>  	regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
> +			   SUN50I_COMBO_PHY_REG0_EN_LVDS |
>  			   SUN50I_COMBO_PHY_REG0_EN_MIPI |
>  			   SUN50I_COMBO_PHY_REG0_EN_COMBOLDO,
> +			   SUN50I_COMBO_PHY_REG0_EN_LVDS |
>  			   SUN50I_COMBO_PHY_REG0_EN_MIPI |
>  			   SUN50I_COMBO_PHY_REG0_EN_COMBOLDO);
>  
> @@ -528,6 +526,22 @@ static int sun6i_dphy_exit(struct phy *phy)
>  	return 0;
>  }
>  
> +static int sun6i_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> +{
> +	struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> +
> +	switch (mode) {
> +	case PHY_MODE_MIPI_DPHY:
> +		regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
> +				   SUN6I_DPHY_ANA4_REG_EN_MIPI,
> +				   SUN6I_DPHY_ANA4_REG_EN_MIPI);
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
>  
>  static const struct phy_ops sun6i_dphy_ops = {
>  	.configure	= sun6i_dphy_configure,
> @@ -535,6 +549,7 @@ static const struct phy_ops sun6i_dphy_ops = {
>  	.power_off	= sun6i_dphy_power_off,
>  	.init		= sun6i_dphy_init,
>  	.exit		= sun6i_dphy_exit,
> +	.set_mode	= sun6i_set_mode,
>  };
>  
>  static const struct regmap_config sun6i_dphy_regmap_config = {
> 
> -- 
> 2.39.5
> 

-- 
Paul Kocialkowski,

Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/

Expert in multimedia, graphics and embedded hardware support with Linux.

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WARNING: multiple messages have this Message-ID (diff)
From: Paul Kocialkowski <paulk@sys-base.io>
To: Parthiban Nallathambi <parthiban@linumiz.com>
Cc: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	Jernej Skrabec <jernej.skrabec@gmail.com>,
	Samuel Holland <samuel@sholland.org>,
	Maxime Ripard <mripard@kernel.org>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Linus Walleij <linus.walleij@linaro.org>,
	Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	iommu@lists.linux.dev, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
	dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org,
	linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH 17/22] phy: allwinner: phy-sun6i-mipi-dphy: add LVDS support
Date: Wed, 25 Jun 2025 10:41:56 +0200	[thread overview]
Message-ID: <aFu2VBhCIEdLIPv3@shepard> (raw)
In-Reply-To: <20241227-a133-display-support-v1-17-13b52f71fb14@linumiz.com>


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Hi,

Thanks for your work on this!

On Fri 27 Dec 24, 16:38, Parthiban Nallathambi wrote:
> DPHY in A100/A133 supports both LVDS and DSI. Combo phy register
> have BIT(2) for enabling LVDS specifically, but enabling it alone
> isn't functional.
> 
> Both MIPI and LVDS needs to be enabled in the combo phy to get
> the display working under LVDS mode. There is no specific enable
> bit for LVDS apart from the one in combo phy. MIPI got enable
> control in analog 4 register which must be disabled when using
> in LVDS mode.
> 
> Introduce set_mode in phy ops to control only for MIPI DSI.

Similar work was already submitted for D1/T113-S3 LVDS support, which seems to
be the exact same situation as the A133.

See: https://patchwork.freedesktop.org/series/145276/

I just made a review of that series and find it more elegant in various ways
(especially since configuring the registers in set_mode is not the right place).
So you probably want to follow-up on that series instead.

Note that both D1/T113-S3 and A133 support a second LVDS output, LVDS1, which
uses the traditional TCON0 LVDS PHY. It would be great to be able to support
both outputs as well as dual-link modes!

All the best,

Paul

> Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
> ---
>  drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 23 +++++++++++++++++++----
>  1 file changed, 19 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> index 36eab95271b2..d164b2ea5dfd 100644
> --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> @@ -314,13 +314,11 @@ static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
>  	/* Disable sigma-delta modulation. */
>  	regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0);
>  
> -	regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
> -			   SUN6I_DPHY_ANA4_REG_EN_MIPI,
> -			   SUN6I_DPHY_ANA4_REG_EN_MIPI);
> -
>  	regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
> +			   SUN50I_COMBO_PHY_REG0_EN_LVDS |
>  			   SUN50I_COMBO_PHY_REG0_EN_MIPI |
>  			   SUN50I_COMBO_PHY_REG0_EN_COMBOLDO,
> +			   SUN50I_COMBO_PHY_REG0_EN_LVDS |
>  			   SUN50I_COMBO_PHY_REG0_EN_MIPI |
>  			   SUN50I_COMBO_PHY_REG0_EN_COMBOLDO);
>  
> @@ -528,6 +526,22 @@ static int sun6i_dphy_exit(struct phy *phy)
>  	return 0;
>  }
>  
> +static int sun6i_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> +{
> +	struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> +
> +	switch (mode) {
> +	case PHY_MODE_MIPI_DPHY:
> +		regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
> +				   SUN6I_DPHY_ANA4_REG_EN_MIPI,
> +				   SUN6I_DPHY_ANA4_REG_EN_MIPI);
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
>  
>  static const struct phy_ops sun6i_dphy_ops = {
>  	.configure	= sun6i_dphy_configure,
> @@ -535,6 +549,7 @@ static const struct phy_ops sun6i_dphy_ops = {
>  	.power_off	= sun6i_dphy_power_off,
>  	.init		= sun6i_dphy_init,
>  	.exit		= sun6i_dphy_exit,
> +	.set_mode	= sun6i_set_mode,
>  };
>  
>  static const struct regmap_config sun6i_dphy_regmap_config = {
> 
> -- 
> 2.39.5
> 

-- 
Paul Kocialkowski,

Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/

Expert in multimedia, graphics and embedded hardware support with Linux.

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-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

  reply	other threads:[~2025-06-25  9:50 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-27 11:07 [PATCH 00/22] Add support for A100/A133 display Parthiban Nallathambi
2024-12-27 11:07 ` Parthiban Nallathambi
2024-12-27 11:07 ` [PATCH 01/22] dt-bindings: iommu: sun50i: remove resets from required property Parthiban Nallathambi
2024-12-27 11:07   ` Parthiban Nallathambi
2025-08-07 15:27   ` Paul Kocialkowski
2025-08-07 15:27     ` Paul Kocialkowski
2024-12-27 11:07 ` [PATCH 02/22] dt-bindings: display: sunxi: Add a100/a133 display engine compatibles Parthiban Nallathambi
2024-12-27 11:07   ` Parthiban Nallathambi
2024-12-27 11:07 ` [PATCH 03/22] dt-bindings: clock: sun8i de2 clock: Add PLL com clock Parthiban Nallathambi
2024-12-27 11:07   ` Parthiban Nallathambi
2024-12-27 13:16   ` Rob Herring (Arm)
2024-12-27 13:16     ` Rob Herring (Arm)
2024-12-27 11:07 ` [PATCH 04/22] dt-bindings: clock: sun8i de2 clock: Add a100/a133 compatible Parthiban Nallathambi
2024-12-27 11:07   ` Parthiban Nallathambi
2024-12-27 11:07 ` [PATCH 05/22] dt-bindings: display: sun4i: add phy property Parthiban Nallathambi
2024-12-27 11:07   ` Parthiban Nallathambi
2024-12-27 11:07 ` [PATCH 06/22] dt-bindings: display: sun4i: add a100/a133 tcon lcd Parthiban Nallathambi
2024-12-27 11:07   ` Parthiban Nallathambi
2024-12-27 11:07 ` [PATCH 07/22] dt-bindings: vendor-prefixes: Shenzhen Baijie Technology Parthiban Nallathambi
2024-12-27 11:07   ` Parthiban Nallathambi
2025-08-07 15:24   ` Paul Kocialkowski
2025-08-07 15:24     ` Paul Kocialkowski
2024-12-27 11:07 ` [PATCH 08/22] dt-bindings: arm: sunxi: document Szbaijie A133 helper board Parthiban Nallathambi
2024-12-27 11:07   ` Parthiban Nallathambi
2024-12-27 11:07 ` [PATCH 09/22] iommu: sun50i: make reset control optional Parthiban Nallathambi
2024-12-27 11:07   ` Parthiban Nallathambi
2025-01-06 11:24   ` Joerg Roedel
2025-01-06 11:24     ` Joerg Roedel
2025-08-07 15:29   ` Paul Kocialkowski
2025-08-07 15:29     ` Paul Kocialkowski
2024-12-27 11:07 ` [PATCH 10/22] pinctrl: sunxi: add missed lvds pins for a100/a133 Parthiban Nallathambi
2024-12-27 11:07   ` Parthiban Nallathambi
2025-01-13 14:30   ` Linus Walleij
2025-01-13 14:30     ` Linus Walleij
2025-01-14 15:46     ` Andre Przywara
2025-01-14 15:46       ` Andre Przywara
2025-06-25  8:46   ` Paul Kocialkowski
2025-06-25  8:46     ` Paul Kocialkowski
2025-06-25  9:36     ` Parthiban
2025-06-25  9:36       ` Parthiban
2025-06-25 10:11       ` Paul Kocialkowski
2025-06-25 10:11         ` Paul Kocialkowski
2025-06-25 10:46         ` Parthiban
2025-06-25 10:46           ` Parthiban
2024-12-27 11:07 ` [PATCH 11/22] drm/sun4i: Add support for a100/a133 display engine Parthiban Nallathambi
2024-12-27 11:07   ` Parthiban Nallathambi
2024-12-27 11:07 ` [PATCH 12/22] drm/sun4i: Add support for a100/a133 mixer Parthiban Nallathambi
2024-12-27 11:07   ` Parthiban Nallathambi
2024-12-27 11:08 ` [PATCH 13/22] drm/sun4i: make tcon top tv0 optional Parthiban Nallathambi
2024-12-27 11:08   ` Parthiban Nallathambi
2024-12-27 11:08 ` [PATCH 14/22] drm/sun4i: add a100/a133 tcon top quirks Parthiban Nallathambi
2024-12-27 11:08   ` Parthiban Nallathambi
2024-12-27 11:08 ` [PATCH 15/22] clk: sunxi-ng: sun8i-de2: add pll-com clock support Parthiban Nallathambi
2024-12-27 11:08   ` Parthiban Nallathambi
2024-12-27 11:08 ` [PATCH 16/22] clk: sunxi-ng: sun8i-de2: Add support for a100/a133 Parthiban Nallathambi
2024-12-27 11:08   ` Parthiban Nallathambi
2024-12-27 11:08 ` [PATCH 17/22] phy: allwinner: phy-sun6i-mipi-dphy: add LVDS support Parthiban Nallathambi
2024-12-27 11:08   ` Parthiban Nallathambi
2025-06-25  8:41   ` Paul Kocialkowski [this message]
2025-06-25  8:41     ` Paul Kocialkowski
2025-06-25  9:38     ` Parthiban
2025-06-25  9:38       ` Parthiban
2025-11-08 16:58     ` Parthiban
2025-11-08 16:58       ` Parthiban

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