From: Niklas Cassel <cassel@kernel.org>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Stanimir Varbanov" <svarbanov@mm-sol.com>,
"Wilfred Mallawa" <wilfred.mallawa@wdc.com>,
"Damien Le Moal" <dlemoal@kernel.org>,
"Laszlo Fiat" <laszlo.fiat@proton.me>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v3 4/6] PCI: qcom: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ
Date: Wed, 25 Jun 2025 11:06:40 +0200 [thread overview]
Message-ID: <aFu8IOsQX66mfveW@ryzen> (raw)
In-Reply-To: <ebrnndrw7kifuyixh4umos6ozhg3a45ya2ooxrf44xytdpiczs@qtd2l4tc63kt>
On Mon, Jun 23, 2025 at 08:27:19AM -0600, Manivannan Sadhasivam wrote:
> On Fri, Jun 13, 2025 at 02:48:43PM +0200, Niklas Cassel wrote:
> > Per PCIe r6.0, sec 6.6.1, software must generally wait a minimum of
> > 100ms (PCIE_RESET_CONFIG_WAIT_MS) after Link training completes before
> > sending a Configuration Request.
> >
> > Prior to 36971d6c5a9a ("PCI: qcom: Don't wait for link if we can detect
> > Link Up"), qcom used dw_pcie_wait_for_link(), which waited between 0
> > and 90ms after the link came up before we enumerate the bus, and this
> > was apparently enough for most devices.
> >
> > After 36971d6c5a9a, qcom_pcie_global_irq_thread() started enumeration
> > immediately when handling the link-up IRQ, and devices (e.g., Laszlo
> > Fiat's PLEXTOR PX-256M8PeGN NVMe SSD) may not be ready to handle config
> > requests yet.
> >
> > Delay PCIE_RESET_CONFIG_WAIT_MS after the link-up IRQ before starting
> > enumeration.
> >
> > Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
> > Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> > Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
>
> Shouldn't 36971d6c5a9a be the fixes commit?
See Bjorn's comment:
https://lore.kernel.org/linux-pci/20250611211456.GA869983@bhelgaas/
I would argue that 0e898eb8df4e ("PCI: rockchip-dwc: Add Rockchip
RK356X host controller driver") is the right Fixes: commit here
because dw_pcie_wait_for_link() *never* waited the required time, and
it's quite possible that other devices don't work correctly. The
delay was about 90ms - <time required for link training>, so could be
significantly less than 100ms.
Thus, following Bjorn's comment, to put the commit that introduced the driver
as the Fixes tag for dw-rockchip, I did the same thing for qcom.
Kind regards,
Niklas
next prev parent reply other threads:[~2025-06-25 9:06 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 12:48 [PATCH v3 0/6] PCI: dwc: Do not enumerate bus before endpoint devices are ready Niklas Cassel
2025-06-13 12:48 ` Niklas Cassel
2025-06-13 12:48 ` [PATCH v3 1/6] PCI: Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS Niklas Cassel
2025-06-13 12:48 ` [PATCH v3 2/6] PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS Niklas Cassel
2025-06-13 12:48 ` Niklas Cassel
2025-06-23 14:25 ` Manivannan Sadhasivam
2025-06-23 14:25 ` Manivannan Sadhasivam
2025-06-13 12:48 ` [PATCH v3 3/6] PCI: dw-rockchip: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ Niklas Cassel
2025-06-13 12:48 ` Niklas Cassel
2025-06-13 12:48 ` [PATCH v3 4/6] PCI: qcom: " Niklas Cassel
2025-06-23 14:27 ` Manivannan Sadhasivam
2025-06-25 9:06 ` Niklas Cassel [this message]
2025-06-13 12:48 ` [PATCH v3 5/6] PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up Niklas Cassel
2025-06-23 14:28 ` Manivannan Sadhasivam
2025-06-25 9:20 ` Niklas Cassel
2025-06-13 12:48 ` [PATCH v3 6/6] PCI: dwc: Reduce LINK_WAIT_SLEEP_MS Niklas Cassel
2025-06-23 14:52 ` Manivannan Sadhasivam
2025-06-25 9:02 ` Niklas Cassel
2025-06-23 10:12 ` [PATCH v3 0/6] PCI: dwc: Do not enumerate bus before endpoint devices are ready Niklas Cassel
2025-06-23 10:12 ` Niklas Cassel
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