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From: Niklas Cassel <cassel@kernel.org>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: "Jingoo Han" <jingoohan1@gmail.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Wilfred Mallawa" <wilfred.mallawa@wdc.com>,
	"Damien Le Moal" <dlemoal@kernel.org>,
	"Laszlo Fiat" <laszlo.fiat@proton.me>,
	linux-pci@vger.kernel.org
Subject: Re: [PATCH v3 5/6] PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up
Date: Wed, 25 Jun 2025 11:20:42 +0200	[thread overview]
Message-ID: <aFu_aokbo37tqfZH@ryzen> (raw)
In-Reply-To: <hmkx6vjoqshthk5rqakcyzneredcg6q45tqhnaoqvmvs36zmsk@tzd7f44qkydq>

On Mon, Jun 23, 2025 at 08:28:55AM -0600, Manivannan Sadhasivam wrote:
> On Fri, Jun 13, 2025 at 02:48:44PM +0200, Niklas Cassel wrote:
> > As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link speeds
> > greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link
> > training completes before sending a Configuration Request.
> > 
> > Add this delay in dw_pcie_wait_for_link(), after the link is reported as
> > up. The delay will only be performed in the success case where the link
> > came up.
> > 
> > DWC glue drivers that have a link up IRQ (drivers that set
> > use_linkup_irq = true) do not call dw_pcie_wait_for_link(), instead they
> > perform this delay in their threaded link up IRQ handler.
> > 
> > Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
> > Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> > Signed-off-by: Niklas Cassel <cassel@kernel.org>
> > ---
> >  drivers/pci/controller/dwc/pcie-designware.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index 4d794964fa0f..24903f67d724 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -714,6 +714,13 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci)
> >  		return -ETIMEDOUT;
> >  	}
> >  
> > +	/*
> > +	 * As per PCIe r6.0, sec 6.6.1, a Downstream Port that supports Link
> > +	 * speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms
> > +	 * after Link training completes before sending a Configuration Request.
> > +	 */
> 
> As the comment clearly states, we should only wait if the downstream port
> supports link speed > 5.0 GT/s. So you should have the below check:
> 
> 	if (pci->max_link_speed > 1)
> 		msleep(PCIE_RESET_CONFIG_WAIT_MS);

PCIe 1.0 has 2.5 GT/s
PCIe 2.0 has 5.0 GT/s

Thus will assume that you actually meant:

if (pci->max_link_speed > 2)


Kind regards,
Niklas

  reply	other threads:[~2025-06-25  9:20 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-13 12:48 [PATCH v3 0/6] PCI: dwc: Do not enumerate bus before endpoint devices are ready Niklas Cassel
2025-06-13 12:48 ` Niklas Cassel
2025-06-13 12:48 ` [PATCH v3 1/6] PCI: Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS Niklas Cassel
2025-06-13 12:48 ` [PATCH v3 2/6] PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS Niklas Cassel
2025-06-13 12:48   ` Niklas Cassel
2025-06-23 14:25   ` Manivannan Sadhasivam
2025-06-23 14:25     ` Manivannan Sadhasivam
2025-06-13 12:48 ` [PATCH v3 3/6] PCI: dw-rockchip: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ Niklas Cassel
2025-06-13 12:48   ` Niklas Cassel
2025-06-13 12:48 ` [PATCH v3 4/6] PCI: qcom: " Niklas Cassel
2025-06-23 14:27   ` Manivannan Sadhasivam
2025-06-25  9:06     ` Niklas Cassel
2025-06-13 12:48 ` [PATCH v3 5/6] PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up Niklas Cassel
2025-06-23 14:28   ` Manivannan Sadhasivam
2025-06-25  9:20     ` Niklas Cassel [this message]
2025-06-13 12:48 ` [PATCH v3 6/6] PCI: dwc: Reduce LINK_WAIT_SLEEP_MS Niklas Cassel
2025-06-23 14:52   ` Manivannan Sadhasivam
2025-06-25  9:02     ` Niklas Cassel
2025-06-23 10:12 ` [PATCH v3 0/6] PCI: dwc: Do not enumerate bus before endpoint devices are ready Niklas Cassel
2025-06-23 10:12   ` Niklas Cassel

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