Re: [PATCH v14 2/7] hw/core/machine: topology functions capabilities added

[Zhao Liu <zhao1.liu@intel.com>]

On Mon, Jul 07, 2025 at 01:19:03PM +0100, Alireza Sanaee via wrote:
> Date: Mon, 7 Jul 2025 13:19:03 +0100
> From: Alireza Sanaee via <qemu-devel@nongnu.org>
> Subject: [PATCH v14 2/7] hw/core/machine: topology functions capabilities
>  added
> X-Mailer: git-send-email 2.34.1
> 
> Add two functions one of which finds the lowest level cache defined in
> the cache description input, and the other checks if caches are defined
> at a particular level.
> 
> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
> ---
>  hw/core/machine-smp.c | 59 +++++++++++++++++++++++++++++++++++++++++++
>  include/hw/boards.h   |  7 +++++
>  2 files changed, 66 insertions(+)
> 
> diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
> index 0be0ac044c..4baf4a878e 100644
> --- a/hw/core/machine-smp.c
> +++ b/hw/core/machine-smp.c
> @@ -406,3 +406,62 @@ bool machine_check_smp_cache(const MachineState *ms, Error **errp)
>  
>      return true;
>  }
> +
> +/*
> + * This function assumes l3 and l2 have unified cache and l1 is split l1d
> + * and l1i, and further prepares the lowest cache level for a topology
> + * level.  The info will be fed to build_caches to create caches at the
> + * right level.
> + */
> +bool machine_find_lowest_level_cache_at_topo_level(const MachineState *ms,
> +                                                   int *level_found,
> +                                                   CpuTopologyLevel topo_level)
> +{
> +
> +    CpuTopologyLevel level;
> +
> +    level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I);
> +    if (level == topo_level) {
> +        *level_found = 1;

Unfortunately, there is no proper mapping between the cache enumeration
and the cache level...

> +        return true;
> +    }
> +

...at least for now, this is fine for me. We can think of how to
organize everything better afterwards. So,

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>