[PATCH RFC/RFT 0/2] Enable 64-bit polling mode for R-Car Gen3 and

[PATCH RFC/RFT 0/2] Enable 64-bit polling mode for R-Car Gen3 and

[Biju Das]

As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
During testing it is found that, if the DMA buffer is not aligned to 128
bit it fallback to PIO mode. In such cases, 64-bit access is much more
efficient than the current 16-bit.

Biju Das (2):
  mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode
  mmc: renesas_sdhi: Enable 64-bit polling mode

 drivers/mmc/host/renesas_sdhi_internal_dmac.c |  3 +-
 drivers/mmc/host/tmio_mmc.h                   | 12 +++++++
 drivers/mmc/host/tmio_mmc_core.c              | 32 +++++++++++++++++++
 include/linux/platform_data/tmio.h            |  3 ++
 4 files changed, 49 insertions(+), 1 deletion(-)

-- 
2.43.0

[PATCH RFC/RFT 1/2] mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode

[Biju Das]

As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
During testing it is found that, if the DMA buffer is not aligned to 128
bit it fallback to PIO mode. In such cases, 64-bit access is much more
efficient than the current 16-bit.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/mmc/host/tmio_mmc.h        | 12 +++++++++++
 drivers/mmc/host/tmio_mmc_core.c   | 32 ++++++++++++++++++++++++++++++
 include/linux/platform_data/tmio.h |  3 +++
 3 files changed, 47 insertions(+)

diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
index d730b7633ae1..823143a98941 100644
--- a/drivers/mmc/host/tmio_mmc.h
+++ b/drivers/mmc/host/tmio_mmc.h
@@ -242,6 +242,18 @@ static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
 	ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count);
 }
 
+static inline void sd_ctrl_read64_rep(struct tmio_mmc_host *host, int addr,
+				      u64 *buf, int count)
+{
+	ioread64_rep(host->ctl + (addr << host->bus_shift), buf, count);
+}
+
+static inline void sd_ctrl_write64_rep(struct tmio_mmc_host *host, int addr,
+				       const u64 *buf, int count)
+{
+	iowrite64_rep(host->ctl + (addr << host->bus_shift), buf, count);
+}
+
 static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
 				   u16 val)
 {
diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index 2cec463b5e00..c4eacf9545ba 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -350,6 +350,38 @@ static void tmio_mmc_transfer_data(struct tmio_mmc_host *host,
 	/*
 	 * Transfer the data
 	 */
+
+	if (host->pdata->flags & TMIO_MMC_64BIT_DATA_PORT) {
+		u64 *buf64 = (u64 *)buf;
+		u64 data = 0;
+
+		if (count >= 8) {
+			if (is_read)
+				sd_ctrl_read64_rep(host, CTL_SD_DATA_PORT,
+						   buf64, count >> 3);
+			else
+				sd_ctrl_write64_rep(host, CTL_SD_DATA_PORT,
+						    buf64, count >> 3);
+		}
+
+		/* if count was multiple of 8 */
+		if (!(count & 0x7))
+			return;
+
+		buf64 += count >> 3;
+		count %= 8;
+
+		if (is_read) {
+			sd_ctrl_read64_rep(host, CTL_SD_DATA_PORT, &data, 1);
+			memcpy(buf64, &data, count);
+		} else {
+			memcpy(&data, buf64, count);
+			sd_ctrl_write64_rep(host, CTL_SD_DATA_PORT, &data, 1);
+		}
+
+		return;
+	}
+
 	if (host->pdata->flags & TMIO_MMC_32BIT_DATA_PORT) {
 		u32 data = 0;
 		u32 *buf32 = (u32 *)buf;
diff --git a/include/linux/platform_data/tmio.h b/include/linux/platform_data/tmio.h
index b060124ba1ae..426291713b83 100644
--- a/include/linux/platform_data/tmio.h
+++ b/include/linux/platform_data/tmio.h
@@ -47,6 +47,9 @@
 /* Some controllers have a CBSY bit */
 #define TMIO_MMC_HAVE_CBSY		BIT(11)
 
+/* Some controllers have a 64-bit wide data port register */
+#define TMIO_MMC_64BIT_DATA_PORT	BIT(12)
+
 struct tmio_mmc_data {
 	void				*chan_priv_tx;
 	void				*chan_priv_rx;
-- 
2.43.0

[PATCH RFC/RFT 2/2] mmc: renesas_sdhi: Enable 64-bit polling mode

[Biju Das]

Enable 64-bit polling mode for R-Car gen3 and RZ/G2L SoCs.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/mmc/host/renesas_sdhi_internal_dmac.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index 4b389e92399e..9e3ed0bcddd6 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -107,7 +107,8 @@ static const struct renesas_sdhi_of_data of_data_rza2 = {
 
 static const struct renesas_sdhi_of_data of_data_rcar_gen3 = {
 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
-			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
+			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
+			  TMIO_MMC_64BIT_DATA_PORT,
 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
 			  MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
 	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
-- 
2.43.0

Re: [PATCH RFC/RFT 1/2] mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode

[kernel test robot]

Hi Biju,

[This is a private test report for your RFC patch.]
kernel test robot noticed the following build errors:

[auto build test ERROR on linus/master]
[also build test ERROR on ulf-hansson-mmc-mirror/next v6.16-rc4 next-20250630]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Biju-Das/mmc-tmio-Add-64-bit-read-write-support-for-SD_BUF0-in-polling-mode/20250630-161511
base:   linus/master
patch link:    https://lore.kernel.org/r/20250630081315.33288-2-biju.das.jz%40bp.renesas.com
patch subject: [PATCH RFC/RFT 1/2] mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode
config: sh-randconfig-001-20250630 (https://download.01.org/0day-ci/archive/20250701/202507010308.KUbUR1fM-lkp@intel.com/config)
compiler: sh4-linux-gcc (GCC) 15.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250701/202507010308.KUbUR1fM-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202507010308.KUbUR1fM-lkp@intel.com/

All errors (new ones prefixed by >>):

   In file included from drivers/mmc/host/renesas_sdhi.h:15,
                    from drivers/mmc/host/renesas_sdhi_sys_dmac.c:25:
   drivers/mmc/host/tmio_mmc.h: In function 'sd_ctrl_read64_rep':
>> drivers/mmc/host/tmio_mmc.h:248:9: error: implicit declaration of function 'ioread64_rep'; did you mean 'ioread32_rep'? [-Wimplicit-function-declaration]
     248 |         ioread64_rep(host->ctl + (addr << host->bus_shift), buf, count);
         |         ^~~~~~~~~~~~
         |         ioread32_rep
   drivers/mmc/host/tmio_mmc.h: In function 'sd_ctrl_write64_rep':
>> drivers/mmc/host/tmio_mmc.h:254:9: error: implicit declaration of function 'iowrite64_rep'; did you mean 'iowrite32_rep'? [-Wimplicit-function-declaration]
     254 |         iowrite64_rep(host->ctl + (addr << host->bus_shift), buf, count);
         |         ^~~~~~~~~~~~~
         |         iowrite32_rep


vim +248 drivers/mmc/host/tmio_mmc.h

   244	
   245	static inline void sd_ctrl_read64_rep(struct tmio_mmc_host *host, int addr,
   246					      u64 *buf, int count)
   247	{
 > 248		ioread64_rep(host->ctl + (addr << host->bus_shift), buf, count);
   249	}
   250	
   251	static inline void sd_ctrl_write64_rep(struct tmio_mmc_host *host, int addr,
   252					       const u64 *buf, int count)
   253	{
 > 254		iowrite64_rep(host->ctl + (addr << host->bus_shift), buf, count);
   255	}
   256	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

RE: [PATCH RFC/RFT 1/2] mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode

[Biju Das]

Hi,

> -----Original Message-----
> From: kernel test robot <lkp@intel.com>
> Subject: Re: [PATCH RFC/RFT 1/2] mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode
> 
> Hi Biju,
> 
> [This is a private test report for your RFC patch.] kernel test robot noticed the following build
> errors:
> 
> [auto build test ERROR on linus/master]
> [also build test ERROR on ulf-hansson-mmc-mirror/next v6.16-rc4 next-20250630] [If your patch is
> applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-
> format-patch#_base_tree_information]
> 
> url:    https://github.com/intel-lab-lkp/linux/commits/Biju-Das/mmc-tmio-Add-64-bit-read-write-
> support-for-SD_BUF0-in-polling-mode/20250630-161511
> base:   linus/master
> patch link:    https://lore.kernel.org/r/20250630081315.33288-2-biju.das.jz%40bp.renesas.com
> patch subject: [PATCH RFC/RFT 1/2] mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling
> mode
> config: sh-randconfig-001-20250630 (https://download.01.org/0day-
> ci/archive/20250701/202507010308.KUbUR1fM-lkp@intel.com/config)
> compiler: sh4-linux-gcc (GCC) 15.1.0
> reproduce (this is a W=1 build): (https://download.01.org/0day-
> ci/archive/20250701/202507010308.KUbUR1fM-lkp@intel.com/reproduce)
> 
> If you fix the issue in a separate patch/commit (i.e. not just a new version of the same
> patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes:
> | https://lore.kernel.org/oe-kbuild-all/202507010308.KUbUR1fM-lkp@intel.
> | com/
> 
> All errors (new ones prefixed by >>):
> 
>    In file included from drivers/mmc/host/renesas_sdhi.h:15,
>                     from drivers/mmc/host/renesas_sdhi_sys_dmac.c:25:
>    drivers/mmc/host/tmio_mmc.h: In function 'sd_ctrl_read64_rep':
> >> drivers/mmc/host/tmio_mmc.h:248:9: error: implicit declaration of
> >> function 'ioread64_rep'; did you mean 'ioread32_rep'?
> >> [-Wimplicit-function-declaration]
>      248 |         ioread64_rep(host->ctl + (addr << host->bus_shift), buf, count);
>          |         ^~~~~~~~~~~~
>          |         ioread32_rep
>    drivers/mmc/host/tmio_mmc.h: In function 'sd_ctrl_write64_rep':
> >> drivers/mmc/host/tmio_mmc.h:254:9: error: implicit declaration of
> >> function 'iowrite64_rep'; did you mean 'iowrite32_rep'?
> >> [-Wimplicit-function-declaration]
>      254 |         iowrite64_rep(host->ctl + (addr << host->bus_shift), buf, count);
>          |         ^~~~~~~~~~~~~
>          |         iowrite32_rep
> 
> 
> vim +248 drivers/mmc/host/tmio_mmc.h
> 

>    244
>    245	static inline void sd_ctrl_read64_rep(struct tmio_mmc_host *host, int addr,
>    246					      u64 *buf, int count)
>    247	{
>  > 248		ioread64_rep(host->ctl + (addr << host->bus_shift), buf, count);
>    249	}
>    250
>    251	static inline void sd_ctrl_write64_rep(struct tmio_mmc_host *host, int addr,
>    252					       const u64 *buf, int count)
>    253	{
>  > 254		iowrite64_rep(host->ctl + (addr << host->bus_shift), buf, count);
>    255	}
>    256

Maybe I can guard these functions/caller using CONFIG_ARM64 as it is applicable only to GEN3
Platforms. Similar issue seen on [1]??

[1] https://lkml.iu.edu/hypermail/linux/kernel/2209.2/04657.html


Cheers,
Biju

> 
> --
> 0-DAY CI Kernel Test Service
> https://github.com/intel/lkp-tests/wiki

Re: [PATCH RFC/RFT 0/2] Enable 64-bit polling mode for R-Car Gen3 and

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 528 bytes --]

On Mon, Jun 30, 2025 at 09:13:09AM +0100, Biju Das wrote:
> As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
> bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
> During testing it is found that, if the DMA buffer is not aligned to 128
> bit it fallback to PIO mode. In such cases, 64-bit access is much more
> efficient than the current 16-bit.

Cool, I had this somewhere on my todo-list as well. I want to test but
it will probably be only on Friday. But looking forward to it!


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

RE: [PATCH RFC/RFT 0/2] Enable 64-bit polling mode for R-Car Gen3 and

[Biju Das]

Hi Wolfram Sang,

> -----Original Message-----
> From: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Sent: 08 July 2025 21:29
> Subject: Re: [PATCH RFC/RFT 0/2] Enable 64-bit polling mode for R-Car Gen3 and
> 
> On Mon, Jun 30, 2025 at 09:13:09AM +0100, Biju Das wrote:
> > As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
> > bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
> > During testing it is found that, if the DMA buffer is not aligned to
> > 128 bit it fallback to PIO mode. In such cases, 64-bit access is much
> > more efficient than the current 16-bit.
> 
> Cool, I had this somewhere on my todo-list as well. I want to test but it will probably be only on
> Friday. But looking forward to it!

Thanks. Also, we need to find a way to handle this issue [1]

[1] https://lore.kernel.org/linux-renesas-soc/TY3PR01MB1134662BDC486D781E5B263878641A@TY3PR01MB11346.jpnprd01.prod.outlook.com/

Cheers,
Biju

Re: [PATCH RFC/RFT 1/2] mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 473 bytes --]


> Maybe I can guard these functions/caller using CONFIG_ARM64 as it is applicable only to GEN3
> Platforms. Similar issue seen on [1]??
> 
> [1] https://lkml.iu.edu/hypermail/linux/kernel/2209.2/04657.html

Maybe just use 64BIT as the guard? Seems a tad more precise to me.

Other than that, looks good to me:

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Wasn't able to test this yet, though, sorry. I hope for tomorrow, but no
promises.


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH RFC/RFT 2/2] mmc: renesas_sdhi: Enable 64-bit polling mode

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 302 bytes --]

On Mon, Jun 30, 2025 at 09:13:11AM +0100, Biju Das wrote:
> Enable 64-bit polling mode for R-Car gen3 and RZ/G2L SoCs.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Same as patch 1, not tested yet, hope for tomorrow.


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

RE: [PATCH RFC/RFT 1/2] mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode

[Biju Das]

Hi Wolfram Sang,

Thanks for the feedback.

> -----Original Message-----
> From: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Sent: 21 July 2025 12:25
> Subject: Re: [PATCH RFC/RFT 1/2] mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode
> 
> 
> > Maybe I can guard these functions/caller using CONFIG_ARM64 as it is
> > applicable only to GEN3 Platforms. Similar issue seen on [1]??
> >
> > [1] https://lkml.iu.edu/hypermail/linux/kernel/2209.2/04657.html
> 
> Maybe just use 64BIT as the guard? Seems a tad more precise to me.
> 
> Other than that, looks good to me:
> 
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> 
> Wasn't able to test this yet, though, sorry. I hope for tomorrow, but no promises.

Ok, will guard like this in next version.

#ifdef CONFIG_64BIT
static inline void sd_ctrl_read64_rep(struct tmio_mmc_host *host, int addr,
				      u64 *buf, int count)
{
	ioread64_rep(host->ctl + (addr << host->bus_shift), buf, count);
}

static inline void sd_ctrl_write64_rep(struct tmio_mmc_host *host, int addr,
				       const u64 *buf, int count)
{
	iowrite64_rep(host->ctl + (addr << host->bus_shift), buf, count);
}
#else
static inline void sd_ctrl_read64_rep(struct tmio_mmc_host *host, int addr,
				      u64 *buf, int count)
{
}

static inline void sd_ctrl_write64_rep(struct tmio_mmc_host *host, int addr,
				       const u64 *buf, int count)
{
}
#endif


Cheers,
Biju

Re: [PATCH RFC/RFT 1/2] mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode

[wsa+renesas]

> > Maybe just use 64BIT as the guard? Seems a tad more precise to me.
> > 
> > Other than that, looks good to me:
> > 
> > Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> > 
> > Wasn't able to test this yet, though, sorry. I hope for tomorrow, but no promises.
> 
> Ok, will guard like this in next version.
> 
> #ifdef CONFIG_64BIT
> static inline void sd_ctrl_read64_rep(struct tmio_mmc_host *host, int addr,
> 				      u64 *buf, int count)
> {
> 	ioread64_rep(host->ctl + (addr << host->bus_shift), buf, count);
> }

Hmm, I wonder if it is not acceptable in this case to guard the new code
block in tmio_mmc_transfer_data() with #ifdef CONFIG_64BIT. This will
remove the whole code. Your suggestion leaves some code as left overs
which might be confusing.

I found other traces in the kernel also protecting whole code blocks:

tty/serial/8250/8250_dw.c, line 230
mtd/nand/raw/cadence-nand-controller.c, line 1186

What do you think?

Re: [PATCH RFC/RFT 1/2] mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode

[Wolfram Sang]

On Mon, Jun 30, 2025 at 09:13:10AM +0100, Biju Das wrote:
> As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
> bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
> During testing it is found that, if the DMA buffer is not aligned to 128
> bit it fallback to PIO mode. In such cases, 64-bit access is much more
> efficient than the current 16-bit.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Re: [PATCH RFC/RFT 2/2] mmc: renesas_sdhi: Enable 64-bit polling mode

[Wolfram Sang]

On Mon, Jun 30, 2025 at 09:13:11AM +0100, Biju Das wrote:
> Enable 64-bit polling mode for R-Car gen3 and RZ/G2L SoCs.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

RE: [PATCH RFC/RFT 1/2] mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode

[Biju Das]

Hi Wolfram Sang,

Thanks for the feedback.

> -----Original Message-----
> From: wsa+renesas <wsa+renesas@sang-engineering.com>
> Subject: Re: [PATCH RFC/RFT 1/2] mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode
> 
> 
> > > Maybe just use 64BIT as the guard? Seems a tad more precise to me.
> > >
> > > Other than that, looks good to me:
> > >
> > > Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> > >
> > > Wasn't able to test this yet, though, sorry. I hope for tomorrow, but no promises.
> >
> > Ok, will guard like this in next version.
> >
> > #ifdef CONFIG_64BIT
> > static inline void sd_ctrl_read64_rep(struct tmio_mmc_host *host, int addr,
> > 				      u64 *buf, int count)
> > {
> > 	ioread64_rep(host->ctl + (addr << host->bus_shift), buf, count); }
> 
> Hmm, I wonder if it is not acceptable in this case to guard the new code block in
> tmio_mmc_transfer_data() with #ifdef CONFIG_64BIT. This will remove the whole code. Your suggestion
> leaves some code as left overs which might be confusing.

OK. That is a good point.

> 
> I found other traces in the kernel also protecting whole code blocks:
> 
> tty/serial/8250/8250_dw.c, line 230
> mtd/nand/raw/cadence-nand-controller.c, line 1186
> 
> What do you think?

I agree and will guard tmio_mmc_transfer_data() as well to avoid confusion.

Cheers,
Biju