[PATCH] KVM: SVM: Emulate PERF_CNTR_GLOBAL_STATUS_SET for PerfMonV2

[PATCH] KVM: SVM: Emulate PERF_CNTR_GLOBAL_STATUS_SET for PerfMonV2

[Sean Christopherson]

Emulate PERF_CNTR_GLOBAL_STATUS_SET when PerfMonV2 is enumerated to the
guest, as the MSR is supposed to exist in all AMD v2 PMUs.

Fixes: 4a2771895ca6 ("KVM: x86/svm/pmu: Add AMD PerfMonV2 support")
Cc: stable@vger.kernel.org
Cc: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
 arch/x86/include/asm/msr-index.h | 1 +
 arch/x86/kvm/pmu.c               | 5 +++++
 arch/x86/kvm/svm/pmu.c           | 1 +
 arch/x86/kvm/x86.c               | 2 ++
 4 files changed, 9 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index fa878b136eba..ea5366b733c3 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -732,6 +732,7 @@
 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS	0xc0000300
 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL		0xc0000301
 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR	0xc0000302
+#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET	0xc0000303
 
 /* AMD Last Branch Record MSRs */
 #define MSR_AMD64_LBR_SELECT			0xc000010e
diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
index 75e9cfc689f8..a84fb3d28885 100644
--- a/arch/x86/kvm/pmu.c
+++ b/arch/x86/kvm/pmu.c
@@ -650,6 +650,7 @@ int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		msr_info->data = pmu->global_ctrl;
 		break;
 	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:
+	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:
 	case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
 		msr_info->data = 0;
 		break;
@@ -711,6 +712,10 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 		if (!msr_info->host_initiated)
 			pmu->global_status &= ~data;
 		break;
+	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:
+		if (!msr_info->host_initiated)
+			pmu->global_status |= data & ~pmu->global_status_rsvd;
+		break;
 	default:
 		kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index);
 		return kvm_pmu_call(set_msr)(vcpu, msr_info);
diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c
index 288f7f2a46f2..aa4379e46e96 100644
--- a/arch/x86/kvm/svm/pmu.c
+++ b/arch/x86/kvm/svm/pmu.c
@@ -113,6 +113,7 @@ static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
 	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS:
 	case MSR_AMD64_PERF_CNTR_GLOBAL_CTL:
 	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:
+	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:
 		return pmu->version > 1;
 	default:
 		if (msr > MSR_F15H_PERF_CTR5 &&
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 2806f7104295..15c34fbac22a 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -367,6 +367,7 @@ static const u32 msrs_to_save_pmu[] = {
 	MSR_AMD64_PERF_CNTR_GLOBAL_CTL,
 	MSR_AMD64_PERF_CNTR_GLOBAL_STATUS,
 	MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR,
+	MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET,
 };
 
 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) +
@@ -7353,6 +7354,7 @@ static void kvm_probe_msr_to_save(u32 msr_index)
 	case MSR_AMD64_PERF_CNTR_GLOBAL_CTL:
 	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS:
 	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:
+	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:
 		if (!kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2))
 			return;
 		break;

base-commit: 6c7ecd725e503bf2ca69ff52c6cc48bb650b1f11
-- 
2.50.0.727.gbf7dc18ff4-goog

Re: [PATCH] KVM: SVM: Emulate PERF_CNTR_GLOBAL_STATUS_SET for PerfMonV2

[Sean Christopherson]

On Fri, Jul 11, 2025, Sean Christopherson wrote:
> Emulate PERF_CNTR_GLOBAL_STATUS_SET when PerfMonV2 is enumerated to the
> guest, as the MSR is supposed to exist in all AMD v2 PMUs.
> 
> Fixes: 4a2771895ca6 ("KVM: x86/svm/pmu: Add AMD PerfMonV2 support")
> Cc: stable@vger.kernel.org
> Cc: Sandipan Das <sandipan.das@amd.com>
> Signed-off-by: Sean Christopherson <seanjc@google.com>
> ---

...

> @@ -711,6 +712,10 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>  		if (!msr_info->host_initiated)
>  			pmu->global_status &= ~data;
>  		break;
> +	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:
> +		if (!msr_info->host_initiated)
> +			pmu->global_status |= data & ~pmu->global_status_rsvd;
> +		break;
>  	default:
>  		kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index);
>  		return kvm_pmu_call(set_msr)(vcpu, msr_info);

Tested with a hacky KUT test to verify I got the semantics correct.  I think I did?

  static void test_pmu_msrs(void)
  {
	const unsigned long long rsvd = GENMASK_ULL(63, 6);

	wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, -1ull);
	report(!rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS),
	       "Wanted '0', got 0x%" PRIx64, rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS));

	wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET, -1ull);
	report(rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS) == ~rsvd,
	       "Wanted '0x%llx', got 0x%" PRIx64,
	       ~rsvd, rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS));

	wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, -1ull);
	report(!rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS),
	       "Wanted '0', got 0x%" PRIx64, rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS));

	wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET, 0);
	report(!rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS),
	       "Wanted '0', got 0x%" PRIx64, rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS));
  }

One oddity is that the test fails when run on the mediated PMU on Turin, i.e. when
the guest can write MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET directly.

  FAIL: Wanted '0x3f', got 0xc000000000000ff

Bits 59:58 failing is expected, because lack of KVM support for DebugCtl[FPCI]
and DebugCtl[FLBRI] doesn't remove them from hardware.  Disabling interception
of MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET creates a virtualization hole on that
front, but I don't know that it's worth closing.  Letting the guest manually
freeze its counters doesn't seem terribly interesting.

Bits 7:6 being set is _much_ more interesting, at least to me.  They're allegedly
reserved per the APM, and CPUID 0x80000022 says there are only 6 counters, so...

Re: [PATCH] KVM: SVM: Emulate PERF_CNTR_GLOBAL_STATUS_SET for PerfMonV2

[Sandipan Das]

On 7/11/2025 11:08 PM, Sean Christopherson wrote:
> On Fri, Jul 11, 2025, Sean Christopherson wrote:
>> Emulate PERF_CNTR_GLOBAL_STATUS_SET when PerfMonV2 is enumerated to the
>> guest, as the MSR is supposed to exist in all AMD v2 PMUs.
>>
>> Fixes: 4a2771895ca6 ("KVM: x86/svm/pmu: Add AMD PerfMonV2 support")
>> Cc: stable@vger.kernel.org
>> Cc: Sandipan Das <sandipan.das@amd.com>
>> Signed-off-by: Sean Christopherson <seanjc@google.com>
>> ---
> 
> ...
> 
>> @@ -711,6 +712,10 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>>  		if (!msr_info->host_initiated)
>>  			pmu->global_status &= ~data;
>>  		break;
>> +	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:
>> +		if (!msr_info->host_initiated)
>> +			pmu->global_status |= data & ~pmu->global_status_rsvd;
>> +		break;
>>  	default:
>>  		kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index);
>>  		return kvm_pmu_call(set_msr)(vcpu, msr_info);
> 
> Tested with a hacky KUT test to verify I got the semantics correct.  I think I did?
> 
>   static void test_pmu_msrs(void)
>   {
> 	const unsigned long long rsvd = GENMASK_ULL(63, 6);
> 
> 	wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, -1ull);
> 	report(!rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS),
> 	       "Wanted '0', got 0x%" PRIx64, rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS));
> 
> 	wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET, -1ull);
> 	report(rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS) == ~rsvd,
> 	       "Wanted '0x%llx', got 0x%" PRIx64,
> 	       ~rsvd, rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS));
> 
> 	wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, -1ull);
> 	report(!rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS),
> 	       "Wanted '0', got 0x%" PRIx64, rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS));
> 
> 	wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET, 0);
> 	report(!rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS),
> 	       "Wanted '0', got 0x%" PRIx64, rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS));
>   }
> 
> One oddity is that the test fails when run on the mediated PMU on Turin, i.e. when
> the guest can write MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET directly.
> 
>   FAIL: Wanted '0x3f', got 0xc000000000000ff
> 
> Bits 59:58 failing is expected, because lack of KVM support for DebugCtl[FPCI]
> and DebugCtl[FLBRI] doesn't remove them from hardware.  Disabling interception
> of MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET creates a virtualization hole on that
> front, but I don't know that it's worth closing.  Letting the guest manually
> freeze its counters doesn't seem terribly interesting.
> 
> Bits 7:6 being set is _much_ more interesting, at least to me.  They're allegedly
> reserved per the APM, and CPUID 0x80000022 says there are only 6 counters, so...

Some of these reserved bits correspond to internal functionality :)
While it is not ideal for software to be able to toggle them, my understanding is
that these bits can be ignored. Otherwise, KVM has to intercept writes to both
MSR_AMD64_PERF_CNTR_GLOBAL_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET.

Re: [PATCH] KVM: SVM: Emulate PERF_CNTR_GLOBAL_STATUS_SET for PerfMonV2

[Sean Christopherson]

On Fri, 11 Jul 2025 10:27:46 -0700, Sean Christopherson wrote:
> Emulate PERF_CNTR_GLOBAL_STATUS_SET when PerfMonV2 is enumerated to the
> guest, as the MSR is supposed to exist in all AMD v2 PMUs.

Applied to kvm-x86 misc.  I put this in "misc" instead of "fixes" as I want to
get a full cycle of more soak time before sending this to LTS kernels.

[1/1] KVM: SVM: Emulate PERF_CNTR_GLOBAL_STATUS_SET for PerfMonV2
      https://github.com/kvm-x86/linux/commit/68e61f6fd656

--
https://github.com/kvm-x86/linux/tree/next