[PATCH 0/5] Add support for TH1520-integrated GMACs

[PATCH 0/5] Add support for TH1520-integrated GMACs

[Yao Zi]

TH1520 SoC integrates two MAC controllers based on Designware IP that
could operate at 1 Gbps. This series ports the MAC glue driver from
Linux, and then enables networking on the TH1520-based Lichee Pi 4A
board.

The driver could send and receive data correctly under link speed of
10Mbps, 100Mbps and 1Gbps. Under 1Gbps, tftp could transfer data at
more than 10MiB/s.

Note the bug fixed by the first patch doesn't cause any problem with
existing supported peripherals, thus the fix isn't urgent.

Yao Zi (5):
  clk: thead: th1520-ap: Correctly handle flags for dividers
  riscv: cpu: th1520: Limit upper RAM boundary to 4 GiB
  drivers: net: Add T-Head DWMAC glue layer
  riscv: dts: th1520: Describe GMACs and enable them on Lichee Pi 4A
  configs: th1520_lpi4a: Enable network support

 MAINTAINERS                                 |   1 +
 arch/riscv/cpu/th1520/dram.c                |  16 ++
 arch/riscv/dts/th1520-lichee-module-4a.dtsi | 119 ++++++++
 arch/riscv/dts/th1520.dtsi                  |  42 +++
 configs/th1520_lpi4a_defconfig              |   7 +-
 drivers/clk/thead/clk-th1520-ap.c           |   4 +-
 drivers/net/Kconfig                         |   8 +
 drivers/net/Makefile                        |   1 +
 drivers/net/dwmac_thead.c                   | 288 ++++++++++++++++++++
 9 files changed, 484 insertions(+), 2 deletions(-)
 create mode 100644 drivers/net/dwmac_thead.c

-- 
2.50.0

[PATCH 1/5] clk: thead: th1520-ap: Correctly handle flags for dividers

[Yao Zi]

Unlike the gate clocks which make no use of flags, most dividers in
TH1520 SoC are one-based, thus are applied with CLK_DIVIDER_ONE_BASED
flag. We couldn't simply ignore the flag, which causes wrong results
when calculating the clock rates.

Add a member to ccu_div_internal for defining the flags, and pass it to
divider_recalc_rate(). With this fix, frequency of all the clocks match
the Linux kernel's calculation.

Fixes: e6bfa6fc94f ("clk: thead: Port clock controller driver of TH1520 SoC")
Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 drivers/clk/thead/clk-th1520-ap.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c
index b80ad05b8ad..822cf0809d5 100644
--- a/drivers/clk/thead/clk-th1520-ap.c
+++ b/drivers/clk/thead/clk-th1520-ap.c
@@ -32,6 +32,7 @@ struct ccu_internal {
 struct ccu_div_internal {
 	u8 shift;
 	u8 width;
+	unsigned long flags;
 };
 
 struct ccu_common {
@@ -79,6 +80,7 @@ struct ccu_pll {
 	{								\
 		.shift	= _shift,					\
 		.width	= _width,					\
+		.flags	= _flags,					\
 	}
 
 #define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _gate, _flags)	\
@@ -182,7 +184,7 @@ static unsigned long ccu_div_get_rate(struct clk *clk)
 	val = val >> cd->div.shift;
 	val &= GENMASK(cd->div.width - 1, 0);
 	rate = divider_recalc_rate(clk, clk_get_parent_rate(clk), val, NULL,
-				   0, cd->div.width);
+				   cd->div.flags, cd->div.width);
 
 	return rate;
 }
-- 
2.50.0

[PATCH 2/5] riscv: cpu: th1520: Limit upper RAM boundary to 4 GiB

[Yao Zi]

TH1520 SoC ships DMA peripherals that could only reach the first 32-bit
range of memory, for example, the GMAC controllers. Let's limit the
usable top of RAM below 4GiB to ensure DMA allocations are accessible to
all peripherals.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/riscv/cpu/th1520/dram.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/riscv/cpu/th1520/dram.c b/arch/riscv/cpu/th1520/dram.c
index 91007c0a3d3..8a0ca26785e 100644
--- a/arch/riscv/cpu/th1520/dram.c
+++ b/arch/riscv/cpu/th1520/dram.c
@@ -19,3 +19,19 @@ int dram_init_banksize(void)
 {
 	return fdtdec_setup_memory_banksize();
 }
+
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
+{
+	/*
+	 * Ensure that we run from first 4GB so that all
+	 * addresses used by U-Boot are 32bit addresses.
+	 *
+	 * This in-turn ensures that 32bit DMA capable
+	 * devices work fine because DMA mapping APIs will
+	 * provide 32bit DMA addresses only.
+	 */
+	if (gd->ram_top > SZ_4G)
+		return SZ_4G;
+
+	return gd->ram_top;
+}
-- 
2.50.0

[PATCH 3/5] drivers: net: Add T-Head DWMAC glue layer

[Yao Zi]

The Designware IP integrated in TH1520 SoC requires extra clock
configuration to operate correctly. The Linux kernel's T-Head DWMAC glue
driver is ported and adapted to U-Boot's API.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 MAINTAINERS               |   1 +
 drivers/net/Kconfig       |   8 ++
 drivers/net/Makefile      |   1 +
 drivers/net/dwmac_thead.c | 288 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 298 insertions(+)
 create mode 100644 drivers/net/dwmac_thead.c

diff --git a/MAINTAINERS b/MAINTAINERS
index d5264c8f5df..438f24f1ff7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1576,6 +1576,7 @@ M:	Yao Zi <ziyao@disroot.org>
 S:	Maintained
 F:	arch/riscv/cpu/th1520/
 F:	drivers/clk/thead/clk-th1520-ap.c
+F:	drivers/net/dwmac_thead.c
 F:	drivers/pinctrl/pinctrl-th1520.c
 F:	drivers/ram/thead/th1520_ddr.c
 
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 950ed0f25a9..d942fa4e202 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -411,6 +411,14 @@ config ETH_DESIGNWARE_S700
 	  This provides glue layer to use Synopsys Designware Ethernet MAC
 	  present on Actions S700 SoC.
 
+config ETH_DESIGNWARE_THEAD
+	bool "T-Head glue driver for Synopsys Designware Ethernet MAC"
+	depends on ETH_DESIGNWARE
+	select DW_ALTDESCRIPTOR
+	help
+	  This provides glue layer to use Synopsys Designware Ethernet MAC
+	  present on T-Head SoCs.
+
 config DW_ALTDESCRIPTOR
 	bool "Designware Ethernet MAC uses alternate (enhanced) descriptors"
 	depends on ETH_DESIGNWARE
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 67bba3a8536..79cc8b422b0 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
 obj-$(CONFIG_ETH_DESIGNWARE_MESON8B) += dwmac_meson8b.o
 obj-$(CONFIG_ETH_DESIGNWARE_S700) += dwmac_s700.o
 obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o
+obj-$(CONFIG_ETH_DESIGNWARE_THEAD) += dwmac_thead.o
 obj-$(CONFIG_ETH_SANDBOX) += sandbox.o
 obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw-bus.o
 obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o
diff --git a/drivers/net/dwmac_thead.c b/drivers/net/dwmac_thead.c
new file mode 100644
index 00000000000..138d71a6202
--- /dev/null
+++ b/drivers/net/dwmac_thead.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * T-HEAD DWMAC platform driver
+ *
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
+ *
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <linux/bitfield.h>
+#include <phy.h>
+
+#include "designware.h"
+
+#define GMAC_CLK_EN			0x00
+#define  GMAC_TX_CLK_EN			BIT(1)
+#define  GMAC_TX_CLK_N_EN		BIT(2)
+#define  GMAC_TX_CLK_OUT_EN		BIT(3)
+#define  GMAC_RX_CLK_EN			BIT(4)
+#define  GMAC_RX_CLK_N_EN		BIT(5)
+#define  GMAC_EPHY_REF_CLK_EN		BIT(6)
+#define GMAC_RXCLK_DELAY_CTRL		0x04
+#define  GMAC_RXCLK_BYPASS		BIT(15)
+#define  GMAC_RXCLK_INVERT		BIT(14)
+#define  GMAC_RXCLK_DELAY		GENMASK(4, 0)
+#define GMAC_TXCLK_DELAY_CTRL		0x08
+#define  GMAC_TXCLK_BYPASS		BIT(15)
+#define  GMAC_TXCLK_INVERT		BIT(14)
+#define  GMAC_TXCLK_DELAY		GENMASK(4, 0)
+#define GMAC_PLLCLK_DIV			0x0c
+#define  GMAC_PLLCLK_DIV_EN		BIT(31)
+#define  GMAC_PLLCLK_DIV_NUM		GENMASK(7, 0)
+#define GMAC_GTXCLK_SEL			0x18
+#define  GMAC_GTXCLK_SEL_PLL		BIT(0)
+#define GMAC_INTF_CTRL			0x1c
+#define  PHY_INTF_MASK			BIT(0)
+#define  PHY_INTF_RGMII			FIELD_PREP(PHY_INTF_MASK, 1)
+#define  PHY_INTF_MII_GMII		FIELD_PREP(PHY_INTF_MASK, 0)
+#define GMAC_TXCLK_OEN			0x20
+#define  TXCLK_DIR_MASK			BIT(0)
+#define  TXCLK_DIR_OUTPUT		FIELD_PREP(TXCLK_DIR_MASK, 0)
+#define  TXCLK_DIR_INPUT		FIELD_PREP(TXCLK_DIR_MASK, 1)
+
+#define GMAC_RGMII_CLK_RATE		125000000
+
+struct dwmac_thead_plat {
+	struct dw_eth_pdata dw_eth_pdata;
+	void __iomem *apb_base;
+};
+
+static int dwmac_thead_set_phy_if(struct dwmac_thead_plat *plat)
+{
+	u32 phyif;
+
+	switch (plat->dw_eth_pdata.eth_pdata.phy_interface) {
+	case PHY_INTERFACE_MODE_MII:
+		phyif = PHY_INTF_MII_GMII;
+		break;
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+		phyif = PHY_INTF_RGMII;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	writel(phyif, plat->apb_base + GMAC_INTF_CTRL);
+	return 0;
+}
+
+static int dwmac_thead_set_txclk_dir(struct dwmac_thead_plat *plat)
+{
+	u32 txclk_dir;
+
+	switch (plat->dw_eth_pdata.eth_pdata.phy_interface) {
+	case PHY_INTERFACE_MODE_MII:
+		txclk_dir = TXCLK_DIR_INPUT;
+		break;
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+		txclk_dir = TXCLK_DIR_OUTPUT;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	writel(txclk_dir, plat->apb_base + GMAC_TXCLK_OEN);
+	return 0;
+}
+
+static unsigned long dwmac_thead_rgmii_tx_rate(int speed)
+{
+	switch (speed) {
+	case 10:
+		return 2500000;
+	case 100:
+		return 25000000;
+	case 1000:
+		return 125000000;
+	}
+
+	return -EINVAL;
+}
+
+static int dwmac_thead_set_clk_tx_rate(struct dwmac_thead_plat *plat,
+				       struct dw_eth_dev *edev,
+				       unsigned long tx_rate)
+{
+	unsigned long rate;
+	u32 div, reg;
+
+	rate = clk_get_rate(&edev->clocks[0]);
+
+	writel(0, plat->apb_base + GMAC_PLLCLK_DIV);
+
+	div = rate / tx_rate;
+	if (rate != tx_rate * div) {
+		pr_err("invalid gmac rate %lu\n", rate);
+		return -EINVAL;
+	}
+
+	reg = FIELD_PREP(GMAC_PLLCLK_DIV_EN, 1) |
+	      FIELD_PREP(GMAC_PLLCLK_DIV_NUM, div);
+		writel(reg, plat->apb_base + GMAC_PLLCLK_DIV);
+
+	return 0;
+}
+
+static int dwmac_thead_enable_clk(struct dwmac_thead_plat *plat)
+{
+	u32 reg;
+
+	switch (plat->dw_eth_pdata.eth_pdata.phy_interface) {
+	case PHY_INTERFACE_MODE_MII:
+		reg = GMAC_RX_CLK_EN | GMAC_TX_CLK_EN;
+		break;
+
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		/* use pll */
+		writel(GMAC_GTXCLK_SEL_PLL, plat->apb_base + GMAC_GTXCLK_SEL);
+		reg = GMAC_TX_CLK_EN | GMAC_TX_CLK_N_EN | GMAC_TX_CLK_OUT_EN |
+		      GMAC_RX_CLK_EN | GMAC_RX_CLK_N_EN;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	writel(reg, plat->apb_base + GMAC_CLK_EN);
+	return 0;
+}
+
+static int dwmac_thead_eth_start(struct udevice *dev)
+{
+	struct dwmac_thead_plat *plat = dev_get_plat(dev);
+	struct dw_eth_dev *edev = dev_get_priv(dev);
+	phy_interface_t interface;
+	bool is_rgmii;
+	long tx_rate;
+	int ret;
+
+	interface = plat->dw_eth_pdata.eth_pdata.phy_interface;
+	is_rgmii = (interface == PHY_INTERFACE_MODE_RGMII)	|
+		   (interface == PHY_INTERFACE_MODE_RGMII_ID)	|
+		   (interface == PHY_INTERFACE_MODE_RGMII_RXID)	|
+		   (interface == PHY_INTERFACE_MODE_RGMII_TXID);
+
+	/*
+	 * When operating in RGMII mode, the TX clock is generated by an
+	 * internal divider and fed to the MAC. Configure and enable it before
+	 * initializing the MAC.
+	 */
+	if (is_rgmii) {
+		ret = dwmac_thead_set_clk_tx_rate(plat, edev,
+						  GMAC_RGMII_CLK_RATE);
+		if (ret)
+			return ret;
+	}
+
+	ret = designware_eth_init(edev, plat->dw_eth_pdata.eth_pdata.enetaddr);
+	if (ret)
+		return ret;
+
+	if (is_rgmii) {
+		tx_rate = dwmac_thead_rgmii_tx_rate(edev->phydev->speed);
+		if (tx_rate < 0)
+			return tx_rate;
+
+		ret = dwmac_thead_set_clk_tx_rate(plat, edev, tx_rate);
+		if (ret)
+			return ret;
+	}
+
+	ret = designware_eth_enable(edev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int dwmac_thead_probe(struct udevice *dev)
+{
+	struct dwmac_thead_plat *plat = dev_get_plat(dev);
+	unsigned int reg;
+	int ret;
+
+	ret = designware_eth_probe(dev);
+	if (ret)
+		return ret;
+
+	ret = dwmac_thead_set_phy_if(plat);
+	if (ret) {
+		pr_err("failed to set phy interface: %d\n", ret);
+		return ret;
+	}
+
+	ret = dwmac_thead_set_txclk_dir(plat);
+	if (ret) {
+		pr_err("failed to set TX clock direction: %d\n", ret);
+		return ret;
+	}
+
+	reg = readl(plat->apb_base + GMAC_RXCLK_DELAY_CTRL);
+	reg &= ~(GMAC_RXCLK_DELAY);
+	reg |= FIELD_PREP(GMAC_RXCLK_DELAY, 0);
+	writel(reg, plat->apb_base + GMAC_RXCLK_DELAY_CTRL);
+
+	reg = readl(plat->apb_base + GMAC_TXCLK_DELAY_CTRL);
+	reg &= ~(GMAC_TXCLK_DELAY);
+	reg |= FIELD_PREP(GMAC_TXCLK_DELAY, 0);
+	writel(reg, plat->apb_base + GMAC_TXCLK_DELAY_CTRL);
+
+	ret = dwmac_thead_enable_clk(plat);
+	if (ret)
+		pr_err("failed to enable clock: %d\n", ret);
+
+	return ret;
+}
+
+static int dwmac_thead_of_to_plat(struct udevice *dev)
+{
+	struct dwmac_thead_plat *pdata = dev_get_plat(dev);
+
+	pdata->apb_base = dev_read_addr_index_ptr(dev, 1);
+	if (!pdata->apb_base) {
+		pr_err("failed to get apb registers\n");
+		return -ENOENT;
+	}
+
+	return designware_eth_of_to_plat(dev);
+}
+
+static const struct eth_ops dwmac_thead_eth_ops = {
+	.start                  = dwmac_thead_eth_start,
+	.send                   = designware_eth_send,
+	.recv                   = designware_eth_recv,
+	.free_pkt               = designware_eth_free_pkt,
+	.stop                   = designware_eth_stop,
+	.write_hwaddr           = designware_eth_write_hwaddr,
+};
+
+static const struct udevice_id dwmac_thead_match[] = {
+	{ .compatible = "thead,th1520-gmac" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(dwmac_thead) = {
+	.name		= "dwmac_thead",
+	.id		= UCLASS_ETH,
+	.of_match	= dwmac_thead_match,
+	.of_to_plat	= dwmac_thead_of_to_plat,
+	.probe		= dwmac_thead_probe,
+	.ops		= &dwmac_thead_eth_ops,
+	.priv_auto	= sizeof(struct dw_eth_dev),
+	.plat_auto	= sizeof(struct dwmac_thead_plat),
+	.flags		= DM_FLAG_ALLOC_PRIV_DMA,
+};
-- 
2.50.0

[PATCH 4/5] riscv: dts: th1520: Describe GMACs and enable them on Lichee Pi 4A

[Yao Zi]

TH1520 SoC ships two MAC controllers based on Designware Ethernet IP
that are capable of Gigabit operation. Describe them in SoC devicetree
and enable them for Lichee Pi 4A.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/riscv/dts/th1520-lichee-module-4a.dtsi | 119 ++++++++++++++++++++
 arch/riscv/dts/th1520.dtsi                  |  42 +++++++
 2 files changed, 161 insertions(+)

diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi
index 9b255f8243c..eecd3e9832a 100644
--- a/arch/riscv/dts/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi
@@ -11,6 +11,11 @@
 	model = "Sipeed Lichee Module 4A";
 	compatible = "sipeed,lichee-module-4a", "thead,th1520";
 
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+	};
+
 	memory@0 {
 		device_type = "memory";
 		reg = <0x0 0x00000000 0x2 0x00000000>;
@@ -38,6 +43,120 @@
 	status = "okay";
 };
 
+&gmac0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_pins>, <&mdio0_pins>;
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+};
+
+&gmac1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1_pins>;
+	phy-handle = <&phy1>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+};
+
+&mdio0 {
+	phy0: ethernet-phy@1 {
+		reg = <1>;
+	};
+
+	phy1: ethernet-phy@2 {
+		reg = <2>;
+	};
+};
+
+&padctrl0_apsys {
+	gmac0_pins: gmac0-0 {
+		tx-pins {
+			pins = "GMAC0_TX_CLK",
+			       "GMAC0_TXEN",
+			       "GMAC0_TXD0",
+			       "GMAC0_TXD1",
+			       "GMAC0_TXD2",
+			       "GMAC0_TXD3";
+			function = "gmac0";
+			bias-disable;
+			drive-strength = <25>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+
+		rx-pins {
+			pins = "GMAC0_RX_CLK",
+			       "GMAC0_RXDV",
+			       "GMAC0_RXD0",
+			       "GMAC0_RXD1",
+			       "GMAC0_RXD2",
+			       "GMAC0_RXD3";
+			function = "gmac0";
+			bias-disable;
+			drive-strength = <1>;
+			input-enable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	gmac1_pins: gmac1-0 {
+		tx-pins {
+			pins = "GPIO2_18", /* GMAC1_TX_CLK */
+			       "GPIO2_20", /* GMAC1_TXEN */
+			       "GPIO2_21", /* GMAC1_TXD0 */
+			       "GPIO2_22", /* GMAC1_TXD1 */
+			       "GPIO2_23", /* GMAC1_TXD2 */
+			       "GPIO2_24"; /* GMAC1_TXD3 */
+			function = "gmac1";
+			bias-disable;
+			drive-strength = <25>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+
+		rx-pins {
+			pins = "GPIO2_19", /* GMAC1_RX_CLK */
+			       "GPIO2_25", /* GMAC1_RXDV */
+			       "GPIO2_30", /* GMAC1_RXD0 */
+			       "GPIO2_31", /* GMAC1_RXD1 */
+			       "GPIO3_0",  /* GMAC1_RXD2 */
+			       "GPIO3_1";  /* GMAC1_RXD3 */
+			function = "gmac1";
+			bias-disable;
+			drive-strength = <1>;
+			input-enable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	mdio0_pins: mdio0-0 {
+		mdc-pins {
+			pins = "GMAC0_MDC";
+			function = "gmac0";
+			bias-disable;
+			drive-strength = <13>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+
+		mdio-pins {
+			pins = "GMAC0_MDIO";
+			function = "gmac0";
+			bias-disable;
+			drive-strength = <13>;
+			input-enable;
+			input-schmitt-enable;
+			slew-rate = <0>;
+		};
+	};
+};
+
 &sdio0 {
 	bus-width = <4>;
 	max-frequency = <198000000>;
diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
index 8306eda5521..c46925a132a 100644
--- a/arch/riscv/dts/th1520.dtsi
+++ b/arch/riscv/dts/th1520.dtsi
@@ -177,6 +177,48 @@
 			status = "disabled";
 		};
 
+		gmac1: ethernet@ffe7060000 {
+			compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
+			reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>;
+			reg-names = "dwmac", "apb";
+			interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>;
+			clock-names = "stmmaceth", "pclk";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+			snps,multicast-filter-bins = <64>;
+			snps,perfect-filter-entries = <32>;
+			status = "disabled";
+
+			mdio1: mdio {
+				compatible = "snps,dwmac-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		gmac0: ethernet@ffe7070000 {
+			compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
+			reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>;
+			reg-names = "dwmac", "apb";
+			interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>;
+			clock-names = "stmmaceth", "pclk";
+			snps,pbl = <32>;
+			snps,fixed-burst;
+			snps,multicast-filter-bins = <64>;
+			snps,perfect-filter-entries = <32>;
+			status = "disabled";
+
+			mdio0: mdio {
+				compatible = "snps,dwmac-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
 		emmc: mmc@ffe7080000 {
 			compatible = "thead,th1520-dwcmshc";
 			reg = <0xff 0xe7080000 0x0 0x10000>;
-- 
2.50.0

[PATCH 5/5] configs: th1520_lpi4a: Enable network support

[Yao Zi]

Enable the network stack, the designware ethernet driver and
corresponding glue driver. The Lichee Pi 4A board ships two RTL8211F
phys, both attached to GMAC 0, thus support for Realtek phys and DM
support for MDIO devices are enabled as well.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 configs/th1520_lpi4a_defconfig | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig
index 78e3b25ab82..2763cbb428a 100644
--- a/configs/th1520_lpi4a_defconfig
+++ b/configs/th1520_lpi4a_defconfig
@@ -76,7 +76,7 @@ CONFIG_MMC_SPEED_MODE_SET=y
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_ENV_RELOC_GD_ENV_ADDR=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NO_NET=y
+CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_BLOCK_CACHE is not set
 CONFIG_DWAPB_GPIO=y
 # CONFIG_I2C is not set
@@ -90,6 +90,11 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_SNPS=y
 # CONFIG_MTD is not set
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_ETH_DESIGNWARE_THEAD=y
 CONFIG_PINCTRL=y
 # CONFIG_POWER is not set
 CONFIG_RAM=y
-- 
2.50.0

Re: [PATCH 1/5] clk: thead: th1520-ap: Correctly handle flags for dividers

[Leo Liang]

On Thu, Jul 10, 2025 at 03:41:57AM +0000, Yao Zi wrote:
> Unlike the gate clocks which make no use of flags, most dividers in
> TH1520 SoC are one-based, thus are applied with CLK_DIVIDER_ONE_BASED
> flag. We couldn't simply ignore the flag, which causes wrong results
> when calculating the clock rates.
> 
> Add a member to ccu_div_internal for defining the flags, and pass it to
> divider_recalc_rate(). With this fix, frequency of all the clocks match
> the Linux kernel's calculation.
> 
> Fixes: e6bfa6fc94f ("clk: thead: Port clock controller driver of TH1520 SoC")
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  drivers/clk/thead/clk-th1520-ap.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)

Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Re: [PATCH 2/5] riscv: cpu: th1520: Limit upper RAM boundary to 4 GiB

[Leo Liang]

On Thu, Jul 10, 2025 at 03:41:58AM +0000, Yao Zi wrote:
> TH1520 SoC ships DMA peripherals that could only reach the first 32-bit
> range of memory, for example, the GMAC controllers. Let's limit the
> usable top of RAM below 4GiB to ensure DMA allocations are accessible to
> all peripherals.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/riscv/cpu/th1520/dram.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Re: [PATCH 3/5] drivers: net: Add T-Head DWMAC glue layer

[Leo Liang]

On Thu, Jul 10, 2025 at 03:41:59AM +0000, Yao Zi wrote:
> The Designware IP integrated in TH1520 SoC requires extra clock
> configuration to operate correctly. The Linux kernel's T-Head DWMAC glue
> driver is ported and adapted to U-Boot's API.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  MAINTAINERS               |   1 +
>  drivers/net/Kconfig       |   8 ++
>  drivers/net/Makefile      |   1 +
>  drivers/net/dwmac_thead.c | 288 ++++++++++++++++++++++++++++++++++++++
>  4 files changed, 298 insertions(+)
>  create mode 100644 drivers/net/dwmac_thead.c

Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Re: [PATCH 4/5] riscv: dts: th1520: Describe GMACs and enable them on Lichee Pi 4A

[Leo Liang]

On Thu, Jul 10, 2025 at 03:42:00AM +0000, Yao Zi wrote:
> TH1520 SoC ships two MAC controllers based on Designware Ethernet IP
> that are capable of Gigabit operation. Describe them in SoC devicetree
> and enable them for Lichee Pi 4A.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/riscv/dts/th1520-lichee-module-4a.dtsi | 119 ++++++++++++++++++++
>  arch/riscv/dts/th1520.dtsi                  |  42 +++++++
>  2 files changed, 161 insertions(+)

Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Re: [PATCH 5/5] configs: th1520_lpi4a: Enable network support

[Leo Liang]

On Thu, Jul 10, 2025 at 03:42:01AM +0000, Yao Zi wrote:
> Enable the network stack, the designware ethernet driver and
> corresponding glue driver. The Lichee Pi 4A board ships two RTL8211F
> phys, both attached to GMAC 0, thus support for Realtek phys and DM
> support for MDIO devices are enabled as well.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  configs/th1520_lpi4a_defconfig | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>