[PATCH v2 00/11] Various V3/S3/V3s fixes and improvements

All of lore.kernel.org
 help / color / mirror / Atom feed

* [PATCH v2 00/11] Various V3/S3/V3s fixes and improvements
@ 2025-08-05 17:48 Paul Kocialkowski
  2025-08-05 17:48 ` [PATCH v2 01/11] sunxi: Kconfig: Fix default order for V3s DRAM clock Paul Kocialkowski
                   ` (10 more replies)
  0 siblings, 11 replies; 19+ messages in thread
From: Paul Kocialkowski @ 2025-08-05 17:48 UTC (permalink / raw)
  To: u-boot
  Cc: Tom Rini, Jagan Teki, Andre Przywara, Chen-Yu Tsai, Icenowy Zheng,
	Paul Kocialkowski

Changes since v1:
- Added a common MACH_SUN8I_V3_V3S option;
- Disabled secure RAM;
- Switched to OF_UPSTREAM;
- Added some pinmux support.
- Removed internal PHY default value;

Paul Kocialkowski (11):
  sunxi: Kconfig: Fix default order for V3s DRAM clock
  sunxi: Split V3 and V3s support with a common option
  sunxi: Disable secure SRAM on sun8i platforms missing it
  power: axp: Add default voltages for V3/S3
  sunxi: Switch V3/V3s device-tree source to OF_UPSTREAM
  sunxi: Add support for I2C1 on PB pins for the V3/V3s
  sunxi: Add support for UART1 on PG pins for the V3/S3
  sunxi: pinecube: Enable EMAC and network support
  sunxi: Add support for the Lichee Pi Zero with Dock
  net: sun8i-emac: Remove internal PHY config default value
  net: sun8i-emac: Add support for active-low leds with internal PHY

 arch/arm/cpu/armv7/Kconfig                    |   6 +-
 arch/arm/dts/Makefile                         |   5 -
 arch/arm/dts/sun8i-s3-elimo-impetus.dtsi      |  44 --
 arch/arm/dts/sun8i-s3-elimo-initium.dts       |  29 -
 arch/arm/dts/sun8i-s3-lichee-zero-plus.dts    |  53 --
 arch/arm/dts/sun8i-s3-pinecube.dts            | 228 ------
 arch/arm/dts/sun8i-v3-sl631-imx179.dts        |  12 -
 arch/arm/dts/sun8i-v3-sl631.dtsi              | 138 ----
 arch/arm/dts/sun8i-v3.dtsi                    |  63 --
 arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts   | 276 --------
 arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts | 105 ---
 arch/arm/dts/sun8i-v3s-licheepi-zero.dts      | 101 ---
 arch/arm/dts/sun8i-v3s.dtsi                   | 656 ------------------
 arch/arm/include/asm/arch-sunxi/cpu.h         |   2 +-
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h   |   2 +-
 arch/arm/mach-sunxi/Kconfig                   |  44 +-
 arch/arm/mach-sunxi/board.c                   |   6 +-
 arch/arm/mach-sunxi/cpu_info.c                |   2 +
 arch/arm/mach-sunxi/dram_sunxi_dw.c           |  18 +-
 arch/arm/mach-sunxi/spl_spi_sunxi.c           |   2 +-
 board/sunxi/board.c                           |   6 +-
 configs/Bananapi_M2_Ultra_defconfig           |   1 -
 configs/LicheePi_Zero_Dock_defconfig          |   6 +
 configs/LicheePi_Zero_defconfig               |   4 +-
 configs/bananapi_m2_berry_defconfig           |   1 -
 configs/pinecube_defconfig                    |  10 +-
 drivers/clk/sunxi/Kconfig                     |   2 +-
 drivers/net/sun8i_emac.c                      |  40 +-
 drivers/phy/allwinner/Kconfig                 |   2 +-
 drivers/pinctrl/sunxi/Kconfig                 |   2 +-
 drivers/power/Kconfig                         |  10 +-
 include/sunxi_gpio.h                          |   2 +
 32 files changed, 94 insertions(+), 1784 deletions(-)
 delete mode 100644 arch/arm/dts/sun8i-s3-elimo-impetus.dtsi
 delete mode 100644 arch/arm/dts/sun8i-s3-elimo-initium.dts
 delete mode 100644 arch/arm/dts/sun8i-s3-lichee-zero-plus.dts
 delete mode 100644 arch/arm/dts/sun8i-s3-pinecube.dts
 delete mode 100644 arch/arm/dts/sun8i-v3-sl631-imx179.dts
 delete mode 100644 arch/arm/dts/sun8i-v3-sl631.dtsi
 delete mode 100644 arch/arm/dts/sun8i-v3.dtsi
 delete mode 100644 arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts
 delete mode 100644 arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
 delete mode 100644 arch/arm/dts/sun8i-v3s-licheepi-zero.dts
 delete mode 100644 arch/arm/dts/sun8i-v3s.dtsi
 create mode 100644 configs/LicheePi_Zero_Dock_defconfig

-- 
2.49.0


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v2 01/11] sunxi: Kconfig: Fix default order for V3s DRAM clock
  2025-08-05 17:48 [PATCH v2 00/11] Various V3/S3/V3s fixes and improvements Paul Kocialkowski
@ 2025-08-05 17:48 ` Paul Kocialkowski
  2025-08-05 17:48 ` [PATCH v2 02/11] sunxi: Split V3 and V3s support with a common option Paul Kocialkowski
                   ` (9 subsequent siblings)
  10 siblings, 0 replies; 19+ messages in thread
From: Paul Kocialkowski @ 2025-08-05 17:48 UTC (permalink / raw)
  To: u-boot
  Cc: Tom Rini, Jagan Teki, Andre Przywara, Chen-Yu Tsai, Icenowy Zheng,
	Paul Kocialkowski

From: Paul Kocialkowski <contact@paulk.fr>

The V3s (using co-packaged DRAM) runs at 360 MHz, which is specified in
the common platform Kconfig file. However the value for MACH_SUN8I will
be picked up instead due to ordering.

Re-order the defaults to have MACH_SUN8I_V3S before MACH_SUN8I and let
it select the correct default. Also update the LicheePi Zero Dock
defconfig to remove the value, which is now correctly selected.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/mach-sunxi/Kconfig     | 2 +-
 configs/LicheePi_Zero_defconfig | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 6a511c4fd396..5a696095586e 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -718,9 +718,9 @@ config DRAM_CLK
 	int "sunxi dram clock speed"
 	default 792 if MACH_SUN9I
 	default 648 if MACH_SUN8I_R40
-	default 312 if MACH_SUN6I || MACH_SUN8I
 	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
 		       MACH_SUN8I_V3S
+	default 312 if MACH_SUN6I || MACH_SUN8I
 	default 672 if MACH_SUN50I
 	default 744 if MACH_SUN50I_H6
 	default 720 if MACH_SUN50I_H616 || MACH_SUN50I_A133
diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig
index c37c49ccbb16..b2cf0a018c7f 100644
--- a/configs/LicheePi_Zero_defconfig
+++ b/configs/LicheePi_Zero_defconfig
@@ -3,6 +3,5 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero"
 CONFIG_SPL=y
 CONFIG_MACH_SUN8I_V3S=y
-CONFIG_DRAM_CLK=360
 # CONFIG_HAS_ARMV7_SECURE_BASE is not set
 CONFIG_NO_NET=y
-- 
2.49.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v2 02/11] sunxi: Split V3 and V3s support with a common option
  2025-08-05 17:48 [PATCH v2 00/11] Various V3/S3/V3s fixes and improvements Paul Kocialkowski
  2025-08-05 17:48 ` [PATCH v2 01/11] sunxi: Kconfig: Fix default order for V3s DRAM clock Paul Kocialkowski
@ 2025-08-05 17:48 ` Paul Kocialkowski
  2025-08-06  0:21   ` Andre Przywara
  2025-08-05 17:48 ` [PATCH v2 03/11] sunxi: Disable secure SRAM on sun8i platforms missing it Paul Kocialkowski
                   ` (8 subsequent siblings)
  10 siblings, 1 reply; 19+ messages in thread
From: Paul Kocialkowski @ 2025-08-05 17:48 UTC (permalink / raw)
  To: u-boot
  Cc: Tom Rini, Jagan Teki, Andre Przywara, Chen-Yu Tsai, Icenowy Zheng,
	Paul Kocialkowski

From: Paul Kocialkowski <contact@paulk.fr>

There are a few notable differences that are relevant to U-Boot, including:
- different DRAM configuration due to the co-packaged DRAM chip in V3s;
- use of an external PMIC (typically an AXP209) on V3;
- extra pins available on V3, e.g. for UART1.

Move the exiting V3s config to a common option and introduce specific options
for V3s and V3 to set specific aspects and reflect this all round the tree.

Also update the pinecube config to reflect the updated defaults.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 arch/arm/dts/Makefile                       |  2 +-
 arch/arm/include/asm/arch-sunxi/cpu.h       |  2 +-
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |  2 +-
 arch/arm/mach-sunxi/Kconfig                 | 41 +++++++++++++--------
 arch/arm/mach-sunxi/board.c                 |  2 +-
 arch/arm/mach-sunxi/cpu_info.c              |  2 +
 arch/arm/mach-sunxi/dram_sunxi_dw.c         | 18 ++++-----
 arch/arm/mach-sunxi/spl_spi_sunxi.c         |  2 +-
 board/sunxi/board.c                         |  2 +-
 configs/pinecube_defconfig                  |  3 +-
 drivers/clk/sunxi/Kconfig                   |  2 +-
 drivers/phy/allwinner/Kconfig               |  2 +-
 drivers/pinctrl/sunxi/Kconfig               |  2 +-
 drivers/power/Kconfig                       |  2 +-
 14 files changed, 47 insertions(+), 37 deletions(-)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0dc7e190eb93..3d93679058c8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -646,7 +646,7 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
 	sun8i-r40-oka40i-c.dtb \
 	sun8i-t3-cqa3t-bv3.dtb \
 	sun8i-v40-bananapi-m2-berry.dtb
-dtb-$(CONFIG_MACH_SUN8I_V3S) += \
+dtb-$(CONFIG_MACH_SUN8I_V3_V3S) += \
 	sun8i-s3-elimo-initium.dtb \
 	sun8i-s3-pinecube.dtb \
 	sun8i-v3-sl631-imx179.dtb \
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index 768c6572d6b7..bd9dd97b890b 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -18,7 +18,7 @@
 
 #define SOCID_A64	0x1689
 #define SOCID_H3	0x1680
-#define SOCID_V3S	0x1681
+#define SOCID_V3_V3S	0x1681
 #define SOCID_H5	0x1718
 #define SOCID_R40	0x1701
 
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index f023a4cfd934..3212b818286c 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -13,7 +13,7 @@
 
 #if defined(CONFIG_SUNXI_GEN_SUN6I) && \
     !defined(CONFIG_MACH_SUN8I_R40) && \
-    !defined(CONFIG_MACH_SUN8I_V3S)
+    !defined(CONFIG_MACH_SUN8I_V3_V3S)
 #define SUNXI_SRAM_A2_BASE		0x00040000
 #ifdef CONFIG_MACH_SUN8I_H3
 #define SUNXI_SRAM_A2_SIZE		(48 * 1024)	/* 16+32 kiB */
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 5a696095586e..f0faa9f80a23 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -476,17 +476,13 @@ config MACH_SUN8I_R528
 	select SUPPORT_SPL
 	select DRAM_SUN20I_D1
 
+config MACH_SUN8I_V3
+	bool "sun8i (Allwinner V3/S3/S3L)"
+	select MACH_SUN8I_V3_V3S
+
 config MACH_SUN8I_V3S
-	bool "sun8i (Allwinner V3/V3s/S3/S3L)"
-	select CPU_V7A
-	select CPU_V7_HAS_NONSEC
-	select CPU_V7_HAS_VIRT
-	select ARCH_SUPPORT_PSCI
-	select SUNXI_GEN_SUN6I
-	select SUNXI_DRAM_DW
-	select SUNXI_DRAM_DW_16BIT
-	select SUPPORT_SPL
-	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+	bool "sun8i (Allwinner V3s)"
+	select MACH_SUN8I_V3_V3S
 
 config MACH_SUN9I
 	bool "sun9i (Allwinner A80)"
@@ -562,7 +558,20 @@ config MACH_SUN8I
 	default y if MACH_SUN8I_A83T
 	default y if MACH_SUNXI_H3_H5
 	default y if MACH_SUN8I_R40
-	default y if MACH_SUN8I_V3S
+	default y if MACH_SUN8I_V3_V3S
+
+config MACH_SUN8I_V3_V3S
+	bool "sun8i (Allwinner V3/V3s/S3/S3L)"
+	depends on MACH_SUN8I_V3 || MACH_SUN8I_V3S
+	select CPU_V7A
+	select CPU_V7_HAS_NONSEC
+	select CPU_V7_HAS_VIRT
+	select ARCH_SUPPORT_PSCI
+	select SUNXI_GEN_SUN6I
+	select SUNXI_DRAM_DW
+	select SUNXI_DRAM_DW_16BIT
+	select SUPPORT_SPL
+	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
 config RESERVE_ALLWINNER_BOOT0_HEADER
 	bool "reserve space for Allwinner boot0 header"
@@ -719,7 +728,7 @@ config DRAM_CLK
 	default 792 if MACH_SUN9I
 	default 648 if MACH_SUN8I_R40
 	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
-		       MACH_SUN8I_V3S
+		       MACH_SUN8I_V3_V3S
 	default 312 if MACH_SUN6I || MACH_SUN8I
 	default 672 if MACH_SUN50I
 	default 744 if MACH_SUN50I_H6
@@ -747,7 +756,7 @@ config DRAM_ZQ
 	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
 		       MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
 	default 127 if MACH_SUN7I
-	default 14779 if MACH_SUN8I_V3S
+	default 14779 if MACH_SUN8I_V3_V3S
 	default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
 	default 4145117 if MACH_SUN9I
 	default 3881915 if MACH_SUN50I
@@ -877,7 +886,7 @@ config SYS_SOC
 config SUNXI_MINIMUM_DRAM_MB
 	int "minimum DRAM size"
 	default 32 if MACH_SUNIV
-	default 64 if MACH_SUN8I_V3S
+	default 64 if MACH_SUN8I_V3_V3S
 	default 256
 	---help---
 	Minimum DRAM size expected on the board. Traditionally we assumed
@@ -963,7 +972,7 @@ config VIDEO_SUNXI
 	depends on !MACH_SUN8I_A83T
 	depends on !MACH_SUNXI_H3_H5
 	depends on !MACH_SUN8I_R40
-	depends on !MACH_SUN8I_V3S
+	depends on !MACH_SUN8I_V3_V3S
 	depends on !MACH_SUN9I
 	depends on !MACH_SUN50I
 	depends on !SUN50I_GEN_H6
@@ -1186,7 +1195,7 @@ config SPL_STACK_R_ADDR
 
 config SPL_SPI_SUNXI
 	bool "Support for SPI Flash on Allwinner SoCs in SPL"
-	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN8I_V3S || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2
+	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN8I_V3_V3S || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2
 	help
 	  Enable support for SPI Flash. This option allows SPL to read from
 	  sunxi SPI Flash. It uses the same method as the boot ROM, so does
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index fb4837c2082d..a1a02b0fae50 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -149,7 +149,7 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3_V3S)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index c3a51d9956ec..5b03dcdc354d 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -90,6 +90,8 @@ int print_cpuinfo(void)
 	printf("CPU:   Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
 #elif defined CONFIG_MACH_SUN8I_R40
 	printf("CPU:   Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
+#elif defined CONFIG_MACH_SUN8I_V3
+	printf("CPU:   Allwinner V3/S3/S3L (SUN8I %04x)\n", sunxi_get_sram_id());
 #elif defined CONFIG_MACH_SUN8I_V3S
 	printf("CPU:   Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
 #elif defined CONFIG_MACH_SUN8I_R528
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index 4ed295909ceb..56d03027b933 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -254,7 +254,7 @@ static void mctl_set_master_priority(uint16_t socid)
 	case SOCID_H3:
 		mctl_set_master_priority_h3();
 		return;
-	case SOCID_V3S:
+	case SOCID_V3_V3S:
 		mctl_set_master_priority_v3s();
 		return;
 	case SOCID_A64:
@@ -445,7 +445,7 @@ static void mctl_sys_init(uint16_t socid, struct dram_para *para)
 				CCM_DRAMCLK_CFG_DIV(1) |
 				CCM_DRAMCLK_CFG_SRC_PLL11 |
 				CCM_DRAMCLK_CFG_UPD);
-	} else if (socid == SOCID_H3 || socid == SOCID_H5 || socid == SOCID_V3S) {
+	} else if (socid == SOCID_H3 || socid == SOCID_H5 || socid == SOCID_V3_V3S) {
 		clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
 		clrsetbits_le32(&ccm->dram_clk_cfg,
 				CCM_DRAMCLK_CFG_DIV_MASK |
@@ -528,7 +528,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 		/* dphy & aphy phase select 270 degree */
 		clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
 				(0x1 << 10) | (0x2 << 8));
-	} else if (socid == SOCID_V3S) {
+	} else if (socid == SOCID_V3_V3S) {
 		/* dx ddr_clk & hdr_clk dynamic mode */
 		clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
 
@@ -567,7 +567,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 	mctl_set_bit_delays(para);
 	udelay(50);
 
-	if (socid == SOCID_V3S) {
+	if (socid == SOCID_V3_V3S) {
 		mctl_v3s_zq_calibration_quirk(para);
 
 		mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
@@ -636,7 +636,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 	udelay(10);
 
 	/* set PGCR3, CKE polarity */
-	if (socid == SOCID_H3 || socid == SOCID_V3S)
+	if (socid == SOCID_H3 || socid == SOCID_V3_V3S)
 		writel(0x00aa0060, &mctl_ctl->pgcr[3]);
 	else if (socid == SOCID_A64 || socid == SOCID_H5 || socid == SOCID_R40)
 		writel(0xc0aa0060, &mctl_ctl->pgcr[3]);
@@ -758,7 +758,7 @@ static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
 	   0,  0,  0,  0,  0,  0,  0,  0,			\
 	   0,  0,  0,  0,  0,  0,  0      }
 
-#define SUN8I_V3S_DX_READ_DELAYS					\
+#define SUN8I_V3S_DX_READ_DELAYS				\
 	{{  8,  8,  8,  8,  8,  8,  8,  8,  8,  0,  0 },	\
 	 {  7,  7,  7,  7,  7,  7,  7,  7,  7,  0,  0 },	\
 	 {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },	\
@@ -851,7 +851,7 @@ unsigned long sunxi_dram_init(void)
 		.dx_read_delays  = SUN8I_H3_DX_READ_DELAYS,
 		.dx_write_delays = SUN8I_H3_DX_WRITE_DELAYS,
 		.ac_delays	 = SUN8I_H3_AC_DELAYS,
-#elif defined(CONFIG_MACH_SUN8I_V3S)
+#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
 		.dx_read_delays  = SUN8I_V3S_DX_READ_DELAYS,
 		.dx_write_delays = SUN8I_V3S_DX_WRITE_DELAYS,
 		.ac_delays	 = SUN8I_V3S_AC_DELAYS,
@@ -878,8 +878,8 @@ unsigned long sunxi_dram_init(void)
 	uint16_t socid = SOCID_H3;
 #elif defined(CONFIG_MACH_SUN8I_R40)
 	uint16_t socid = SOCID_R40;
-#elif defined(CONFIG_MACH_SUN8I_V3S)
-	uint16_t socid = SOCID_V3S;
+#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
+	uint16_t socid = SOCID_V3_V3S;
 #elif defined(CONFIG_MACH_SUN50I)
 	uint16_t socid = SOCID_A64;
 #elif defined(CONFIG_MACH_SUN50I_H5)
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 5f72e809952b..f6650652b42a 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -141,7 +141,7 @@ static bool is_sun6i_gen_spi(void)
 	return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
 	       IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
 	       IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) ||
-	       IS_ENABLED(CONFIG_MACH_SUN8I_V3S);
+	       IS_ENABLED(CONFIG_MACH_SUN8I_V3_V3S);
 }
 
 static uintptr_t spi0_base_address(void)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 2929bc17f084..6520636ffab5 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -68,7 +68,7 @@ void i2c_init_board(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
 	clock_twi_onoff(0, 1);
-#elif defined(CONFIG_MACH_SUN8I_V3S)
+#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
 	clock_twi_onoff(0, 1);
diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig
index 7567a6aa7394..088dd6f8630a 100644
--- a/configs/pinecube_defconfig
+++ b/configs/pinecube_defconfig
@@ -2,8 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube"
 CONFIG_SPL=y
-CONFIG_MACH_SUN8I_V3S=y
-CONFIG_SUNXI_DRAM_DDR3_1333=y
+CONFIG_MACH_SUN8I_V3=y
 CONFIG_DRAM_CLK=504
 CONFIG_DRAM_ODT_EN=y
 CONFIG_I2C0_ENABLE=y
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index 1c1cc82719cd..207d3bed7922 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -68,7 +68,7 @@ config CLK_SUN8I_R40
 
 config CLK_SUN8I_V3S
 	bool "Clock driver for Allwinner V3S"
-	default MACH_SUN8I_V3S
+	default MACH_SUN8I_V3_V3S
 	help
 	  This enables common clock driver support for platforms based
 	  on Allwinner V3S SoC.
diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
index bb0bd8d5f812..335eff0a8bac 100644
--- a/drivers/phy/allwinner/Kconfig
+++ b/drivers/phy/allwinner/Kconfig
@@ -5,7 +5,7 @@ config PHY_SUN4I_USB
 	bool "Allwinner Sun4I USB PHY driver"
 	depends on ARCH_SUNXI
 	depends on !MACH_SUN9I
-	default n if MACH_SUN8I_V3S
+	default n if MACH_SUN8I_V3_V3S
 	default y
 	select DM_REGULATOR
 	select PHY
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 543149922998..59039917158e 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -76,7 +76,7 @@ config PINCTRL_SUN8I_H3_R
 
 config PINCTRL_SUN8I_V3S
 	bool "Support for the Allwinner V3s PIO"
-	default MACH_SUN8I_V3S
+	default MACH_SUN8I_V3_V3S
 	select PINCTRL_SUNXI
 
 config PINCTRL_SUN9I_A80
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index eed65058e667..cdb3d712389c 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -75,7 +75,7 @@ config AXP152_POWER
 
 config AXP209_POWER
 	bool "axp209 pmic support"
-	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3S
+	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3
 	select AXP_PMIC_BUS
 	select CMD_POWEROFF
 	---help---
-- 
2.49.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 02/11] sunxi: Split V3 and V3s support with a common option
  2025-08-05 17:48 ` [PATCH v2 02/11] sunxi: Split V3 and V3s support with a common option Paul Kocialkowski
@ 2025-08-06  0:21   ` Andre Przywara
  2025-08-06 17:24     ` Paul Kocialkowski
  0 siblings, 1 reply; 19+ messages in thread
From: Andre Przywara @ 2025-08-06  0:21 UTC (permalink / raw)
  To: Paul Kocialkowski, linux-sunxi
  Cc: u-boot, Tom Rini, Jagan Teki, Chen-Yu Tsai, Icenowy Zheng,
	Paul Kocialkowski

On Tue,  5 Aug 2025 19:48:18 +0200
Paul Kocialkowski <paulk@sys-base.io> wrote:

Hi Paul,

> From: Paul Kocialkowski <contact@paulk.fr>
> 
> There are a few notable differences that are relevant to U-Boot, including:
> - different DRAM configuration due to the co-packaged DRAM chip in V3s;
> - use of an external PMIC (typically an AXP209) on V3;
> - extra pins available on V3, e.g. for UART1.

Mmmh, to be honest I am not really convinced this is useful. The patch
below looks roughly like a big s/MACH_SUN8I_V3S/MACH_SUN8I_V3_V3S/,
which I am not sure is really worth it. We had not super accurate names
before, after all those are just marketing names that Allwinner once
came up with. So we use MACH_SUN55I_A523, even though it's mostly
A527 or T527 chips, really, for instance.
For the three actually differing items you mention above: I think we
can treat the DRAM and external PMIC like board options, and could
describe the extra pins either unconditionally or drop them at all (see
my comment there).

What do you think? Is that distinction on the Kconfig level really
necessary?

Cheers,
Andre

> Move the exiting V3s config to a common option and introduce specific options
> for V3s and V3 to set specific aspects and reflect this all round the tree.
> 
> Also update the pinecube config to reflect the updated defaults.
> 
> Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
> ---
>  arch/arm/dts/Makefile                       |  2 +-
>  arch/arm/include/asm/arch-sunxi/cpu.h       |  2 +-
>  arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |  2 +-
>  arch/arm/mach-sunxi/Kconfig                 | 41 +++++++++++++--------
>  arch/arm/mach-sunxi/board.c                 |  2 +-
>  arch/arm/mach-sunxi/cpu_info.c              |  2 +
>  arch/arm/mach-sunxi/dram_sunxi_dw.c         | 18 ++++-----
>  arch/arm/mach-sunxi/spl_spi_sunxi.c         |  2 +-
>  board/sunxi/board.c                         |  2 +-
>  configs/pinecube_defconfig                  |  3 +-
>  drivers/clk/sunxi/Kconfig                   |  2 +-
>  drivers/phy/allwinner/Kconfig               |  2 +-
>  drivers/pinctrl/sunxi/Kconfig               |  2 +-
>  drivers/power/Kconfig                       |  2 +-
>  14 files changed, 47 insertions(+), 37 deletions(-)
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 0dc7e190eb93..3d93679058c8 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -646,7 +646,7 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
>  	sun8i-r40-oka40i-c.dtb \
>  	sun8i-t3-cqa3t-bv3.dtb \
>  	sun8i-v40-bananapi-m2-berry.dtb
> -dtb-$(CONFIG_MACH_SUN8I_V3S) += \
> +dtb-$(CONFIG_MACH_SUN8I_V3_V3S) += \
>  	sun8i-s3-elimo-initium.dtb \
>  	sun8i-s3-pinecube.dtb \
>  	sun8i-v3-sl631-imx179.dtb \
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
> index 768c6572d6b7..bd9dd97b890b 100644
> --- a/arch/arm/include/asm/arch-sunxi/cpu.h
> +++ b/arch/arm/include/asm/arch-sunxi/cpu.h
> @@ -18,7 +18,7 @@
>  
>  #define SOCID_A64	0x1689
>  #define SOCID_H3	0x1680
> -#define SOCID_V3S	0x1681
> +#define SOCID_V3_V3S	0x1681
>  #define SOCID_H5	0x1718
>  #define SOCID_R40	0x1701
>  
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> index f023a4cfd934..3212b818286c 100644
> --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> @@ -13,7 +13,7 @@
>  
>  #if defined(CONFIG_SUNXI_GEN_SUN6I) && \
>      !defined(CONFIG_MACH_SUN8I_R40) && \
> -    !defined(CONFIG_MACH_SUN8I_V3S)
> +    !defined(CONFIG_MACH_SUN8I_V3_V3S)
>  #define SUNXI_SRAM_A2_BASE		0x00040000
>  #ifdef CONFIG_MACH_SUN8I_H3
>  #define SUNXI_SRAM_A2_SIZE		(48 * 1024)	/* 16+32 kiB */
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index 5a696095586e..f0faa9f80a23 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -476,17 +476,13 @@ config MACH_SUN8I_R528
>  	select SUPPORT_SPL
>  	select DRAM_SUN20I_D1
>  
> +config MACH_SUN8I_V3
> +	bool "sun8i (Allwinner V3/S3/S3L)"
> +	select MACH_SUN8I_V3_V3S
> +
>  config MACH_SUN8I_V3S
> -	bool "sun8i (Allwinner V3/V3s/S3/S3L)"
> -	select CPU_V7A
> -	select CPU_V7_HAS_NONSEC
> -	select CPU_V7_HAS_VIRT
> -	select ARCH_SUPPORT_PSCI
> -	select SUNXI_GEN_SUN6I
> -	select SUNXI_DRAM_DW
> -	select SUNXI_DRAM_DW_16BIT
> -	select SUPPORT_SPL
> -	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
> +	bool "sun8i (Allwinner V3s)"
> +	select MACH_SUN8I_V3_V3S
>  
>  config MACH_SUN9I
>  	bool "sun9i (Allwinner A80)"
> @@ -562,7 +558,20 @@ config MACH_SUN8I
>  	default y if MACH_SUN8I_A83T
>  	default y if MACH_SUNXI_H3_H5
>  	default y if MACH_SUN8I_R40
> -	default y if MACH_SUN8I_V3S
> +	default y if MACH_SUN8I_V3_V3S
> +
> +config MACH_SUN8I_V3_V3S
> +	bool "sun8i (Allwinner V3/V3s/S3/S3L)"
> +	depends on MACH_SUN8I_V3 || MACH_SUN8I_V3S
> +	select CPU_V7A
> +	select CPU_V7_HAS_NONSEC
> +	select CPU_V7_HAS_VIRT
> +	select ARCH_SUPPORT_PSCI
> +	select SUNXI_GEN_SUN6I
> +	select SUNXI_DRAM_DW
> +	select SUNXI_DRAM_DW_16BIT
> +	select SUPPORT_SPL
> +	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
>  
>  config RESERVE_ALLWINNER_BOOT0_HEADER
>  	bool "reserve space for Allwinner boot0 header"
> @@ -719,7 +728,7 @@ config DRAM_CLK
>  	default 792 if MACH_SUN9I
>  	default 648 if MACH_SUN8I_R40
>  	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
> -		       MACH_SUN8I_V3S
> +		       MACH_SUN8I_V3_V3S
>  	default 312 if MACH_SUN6I || MACH_SUN8I
>  	default 672 if MACH_SUN50I
>  	default 744 if MACH_SUN50I_H6
> @@ -747,7 +756,7 @@ config DRAM_ZQ
>  	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
>  		       MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
>  	default 127 if MACH_SUN7I
> -	default 14779 if MACH_SUN8I_V3S
> +	default 14779 if MACH_SUN8I_V3_V3S
>  	default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
>  	default 4145117 if MACH_SUN9I
>  	default 3881915 if MACH_SUN50I
> @@ -877,7 +886,7 @@ config SYS_SOC
>  config SUNXI_MINIMUM_DRAM_MB
>  	int "minimum DRAM size"
>  	default 32 if MACH_SUNIV
> -	default 64 if MACH_SUN8I_V3S
> +	default 64 if MACH_SUN8I_V3_V3S
>  	default 256
>  	---help---
>  	Minimum DRAM size expected on the board. Traditionally we assumed
> @@ -963,7 +972,7 @@ config VIDEO_SUNXI
>  	depends on !MACH_SUN8I_A83T
>  	depends on !MACH_SUNXI_H3_H5
>  	depends on !MACH_SUN8I_R40
> -	depends on !MACH_SUN8I_V3S
> +	depends on !MACH_SUN8I_V3_V3S
>  	depends on !MACH_SUN9I
>  	depends on !MACH_SUN50I
>  	depends on !SUN50I_GEN_H6
> @@ -1186,7 +1195,7 @@ config SPL_STACK_R_ADDR
>  
>  config SPL_SPI_SUNXI
>  	bool "Support for SPI Flash on Allwinner SoCs in SPL"
> -	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN8I_V3S || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2
> +	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN8I_V3_V3S || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2
>  	help
>  	  Enable support for SPI Flash. This option allows SPL to read from
>  	  sunxi SPI Flash. It uses the same method as the boot ROM, so does
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> index fb4837c2082d..a1a02b0fae50 100644
> --- a/arch/arm/mach-sunxi/board.c
> +++ b/arch/arm/mach-sunxi/board.c
> @@ -149,7 +149,7 @@ static int gpio_init(void)
>  	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
>  	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
>  	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
> -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
> +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3_V3S)
>  	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
>  	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
>  	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
> diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
> index c3a51d9956ec..5b03dcdc354d 100644
> --- a/arch/arm/mach-sunxi/cpu_info.c
> +++ b/arch/arm/mach-sunxi/cpu_info.c
> @@ -90,6 +90,8 @@ int print_cpuinfo(void)
>  	printf("CPU:   Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
>  #elif defined CONFIG_MACH_SUN8I_R40
>  	printf("CPU:   Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
> +#elif defined CONFIG_MACH_SUN8I_V3
> +	printf("CPU:   Allwinner V3/S3/S3L (SUN8I %04x)\n", sunxi_get_sram_id());
>  #elif defined CONFIG_MACH_SUN8I_V3S
>  	printf("CPU:   Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
>  #elif defined CONFIG_MACH_SUN8I_R528
> diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
> index 4ed295909ceb..56d03027b933 100644
> --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
> +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
> @@ -254,7 +254,7 @@ static void mctl_set_master_priority(uint16_t socid)
>  	case SOCID_H3:
>  		mctl_set_master_priority_h3();
>  		return;
> -	case SOCID_V3S:
> +	case SOCID_V3_V3S:
>  		mctl_set_master_priority_v3s();
>  		return;
>  	case SOCID_A64:
> @@ -445,7 +445,7 @@ static void mctl_sys_init(uint16_t socid, struct dram_para *para)
>  				CCM_DRAMCLK_CFG_DIV(1) |
>  				CCM_DRAMCLK_CFG_SRC_PLL11 |
>  				CCM_DRAMCLK_CFG_UPD);
> -	} else if (socid == SOCID_H3 || socid == SOCID_H5 || socid == SOCID_V3S) {
> +	} else if (socid == SOCID_H3 || socid == SOCID_H5 || socid == SOCID_V3_V3S) {
>  		clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
>  		clrsetbits_le32(&ccm->dram_clk_cfg,
>  				CCM_DRAMCLK_CFG_DIV_MASK |
> @@ -528,7 +528,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
>  		/* dphy & aphy phase select 270 degree */
>  		clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
>  				(0x1 << 10) | (0x2 << 8));
> -	} else if (socid == SOCID_V3S) {
> +	} else if (socid == SOCID_V3_V3S) {
>  		/* dx ddr_clk & hdr_clk dynamic mode */
>  		clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
>  
> @@ -567,7 +567,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
>  	mctl_set_bit_delays(para);
>  	udelay(50);
>  
> -	if (socid == SOCID_V3S) {
> +	if (socid == SOCID_V3_V3S) {
>  		mctl_v3s_zq_calibration_quirk(para);
>  
>  		mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
> @@ -636,7 +636,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
>  	udelay(10);
>  
>  	/* set PGCR3, CKE polarity */
> -	if (socid == SOCID_H3 || socid == SOCID_V3S)
> +	if (socid == SOCID_H3 || socid == SOCID_V3_V3S)
>  		writel(0x00aa0060, &mctl_ctl->pgcr[3]);
>  	else if (socid == SOCID_A64 || socid == SOCID_H5 || socid == SOCID_R40)
>  		writel(0xc0aa0060, &mctl_ctl->pgcr[3]);
> @@ -758,7 +758,7 @@ static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
>  	   0,  0,  0,  0,  0,  0,  0,  0,			\
>  	   0,  0,  0,  0,  0,  0,  0      }
>  
> -#define SUN8I_V3S_DX_READ_DELAYS					\
> +#define SUN8I_V3S_DX_READ_DELAYS				\
>  	{{  8,  8,  8,  8,  8,  8,  8,  8,  8,  0,  0 },	\
>  	 {  7,  7,  7,  7,  7,  7,  7,  7,  7,  0,  0 },	\
>  	 {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },	\
> @@ -851,7 +851,7 @@ unsigned long sunxi_dram_init(void)
>  		.dx_read_delays  = SUN8I_H3_DX_READ_DELAYS,
>  		.dx_write_delays = SUN8I_H3_DX_WRITE_DELAYS,
>  		.ac_delays	 = SUN8I_H3_AC_DELAYS,
> -#elif defined(CONFIG_MACH_SUN8I_V3S)
> +#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
>  		.dx_read_delays  = SUN8I_V3S_DX_READ_DELAYS,
>  		.dx_write_delays = SUN8I_V3S_DX_WRITE_DELAYS,
>  		.ac_delays	 = SUN8I_V3S_AC_DELAYS,
> @@ -878,8 +878,8 @@ unsigned long sunxi_dram_init(void)
>  	uint16_t socid = SOCID_H3;
>  #elif defined(CONFIG_MACH_SUN8I_R40)
>  	uint16_t socid = SOCID_R40;
> -#elif defined(CONFIG_MACH_SUN8I_V3S)
> -	uint16_t socid = SOCID_V3S;
> +#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
> +	uint16_t socid = SOCID_V3_V3S;
>  #elif defined(CONFIG_MACH_SUN50I)
>  	uint16_t socid = SOCID_A64;
>  #elif defined(CONFIG_MACH_SUN50I_H5)
> diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
> index 5f72e809952b..f6650652b42a 100644
> --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
> +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
> @@ -141,7 +141,7 @@ static bool is_sun6i_gen_spi(void)
>  	return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
>  	       IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
>  	       IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) ||
> -	       IS_ENABLED(CONFIG_MACH_SUN8I_V3S);
> +	       IS_ENABLED(CONFIG_MACH_SUN8I_V3_V3S);
>  }
>  
>  static uintptr_t spi0_base_address(void)
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index 2929bc17f084..6520636ffab5 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -68,7 +68,7 @@ void i2c_init_board(void)
>  	sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
>  	sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
>  	clock_twi_onoff(0, 1);
> -#elif defined(CONFIG_MACH_SUN8I_V3S)
> +#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
>  	sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
>  	sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
>  	clock_twi_onoff(0, 1);
> diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig
> index 7567a6aa7394..088dd6f8630a 100644
> --- a/configs/pinecube_defconfig
> +++ b/configs/pinecube_defconfig
> @@ -2,8 +2,7 @@ CONFIG_ARM=y
>  CONFIG_ARCH_SUNXI=y
>  CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube"
>  CONFIG_SPL=y
> -CONFIG_MACH_SUN8I_V3S=y
> -CONFIG_SUNXI_DRAM_DDR3_1333=y
> +CONFIG_MACH_SUN8I_V3=y
>  CONFIG_DRAM_CLK=504
>  CONFIG_DRAM_ODT_EN=y
>  CONFIG_I2C0_ENABLE=y
> diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
> index 1c1cc82719cd..207d3bed7922 100644
> --- a/drivers/clk/sunxi/Kconfig
> +++ b/drivers/clk/sunxi/Kconfig
> @@ -68,7 +68,7 @@ config CLK_SUN8I_R40
>  
>  config CLK_SUN8I_V3S
>  	bool "Clock driver for Allwinner V3S"
> -	default MACH_SUN8I_V3S
> +	default MACH_SUN8I_V3_V3S
>  	help
>  	  This enables common clock driver support for platforms based
>  	  on Allwinner V3S SoC.
> diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
> index bb0bd8d5f812..335eff0a8bac 100644
> --- a/drivers/phy/allwinner/Kconfig
> +++ b/drivers/phy/allwinner/Kconfig
> @@ -5,7 +5,7 @@ config PHY_SUN4I_USB
>  	bool "Allwinner Sun4I USB PHY driver"
>  	depends on ARCH_SUNXI
>  	depends on !MACH_SUN9I
> -	default n if MACH_SUN8I_V3S
> +	default n if MACH_SUN8I_V3_V3S
>  	default y
>  	select DM_REGULATOR
>  	select PHY
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index 543149922998..59039917158e 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -76,7 +76,7 @@ config PINCTRL_SUN8I_H3_R
>  
>  config PINCTRL_SUN8I_V3S
>  	bool "Support for the Allwinner V3s PIO"
> -	default MACH_SUN8I_V3S
> +	default MACH_SUN8I_V3_V3S
>  	select PINCTRL_SUNXI
>  
>  config PINCTRL_SUN9I_A80
> diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
> index eed65058e667..cdb3d712389c 100644
> --- a/drivers/power/Kconfig
> +++ b/drivers/power/Kconfig
> @@ -75,7 +75,7 @@ config AXP152_POWER
>  
>  config AXP209_POWER
>  	bool "axp209 pmic support"
> -	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3S
> +	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3
>  	select AXP_PMIC_BUS
>  	select CMD_POWEROFF
>  	---help---


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 02/11] sunxi: Split V3 and V3s support with a common option
  2025-08-06  0:21   ` Andre Przywara
@ 2025-08-06 17:24     ` Paul Kocialkowski
  2025-08-08  3:48       ` Icenowy Zheng
  2025-10-21 14:02       ` Andre Przywara
  0 siblings, 2 replies; 19+ messages in thread
From: Paul Kocialkowski @ 2025-08-06 17:24 UTC (permalink / raw)
  To: Andre Przywara
  Cc: linux-sunxi, u-boot, Tom Rini, Jagan Teki, Chen-Yu Tsai,
	Icenowy Zheng, Paul Kocialkowski

[-- Attachment #1: Type: text/plain, Size: 17914 bytes --]

Hi,

Le Wed 06 Aug 25, 01:21, Andre Przywara a écrit :
> On Tue,  5 Aug 2025 19:48:18 +0200
> Paul Kocialkowski <paulk@sys-base.io> wrote:
> 
> Hi Paul,
> 
> > From: Paul Kocialkowski <contact@paulk.fr>
> > 
> > There are a few notable differences that are relevant to U-Boot, including:
> > - different DRAM configuration due to the co-packaged DRAM chip in V3s;
> > - use of an external PMIC (typically an AXP209) on V3;
> > - extra pins available on V3, e.g. for UART1.
> 
> Mmmh, to be honest I am not really convinced this is useful. The patch
> below looks roughly like a big s/MACH_SUN8I_V3S/MACH_SUN8I_V3_V3S/,
> which I am not sure is really worth it. We had not super accurate names
> before, after all those are just marketing names that Allwinner once
> came up with. So we use MACH_SUN55I_A523, even though it's mostly
> A527 or T527 chips, really, for instance.

Yes I think this case is a bit different because there is actually a difference
not just in the packaging and pins available but also because a dram die is
co-packaged with the sun8i chip.

> For the three actually differing items you mention above: I think we
> can treat the DRAM and external PMIC like board options, and could
> describe the extra pins either unconditionally or drop them at all (see
> my comment there).
> 
> What do you think? Is that distinction on the Kconfig level really
> necessary?

I think it is preferable because the DRAM die co-packaged with the chip is
definitely not a board-specific choice, so I would rather see the DRAM-related
details handled by the common Kconfig rather than duplicated over each V3s
board.

For the PMIC it mostly remains a board-specific option and is not enabled by
default anyway, it's just the defaults that are updated. Apparently there are
designs with V3s that use an AXP209 PMIC so the defaults could actually go
to the common option.

Another approach here could be to keep a single MACH_SUN8I_V3 option and have
an extra one to select the co-packaged DRAM that only V3s boards would select
in their config. If it's the rename that bothers you we could keep the
MACH_SUN8I_V3S name but I think it would be significantly more confusing.

What do you think?

Paul

> Cheers,
> Andre
> 
> > Move the exiting V3s config to a common option and introduce specific options
> > for V3s and V3 to set specific aspects and reflect this all round the tree.
> > 
> > Also update the pinecube config to reflect the updated defaults.
> > 
> > Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
> > ---
> >  arch/arm/dts/Makefile                       |  2 +-
> >  arch/arm/include/asm/arch-sunxi/cpu.h       |  2 +-
> >  arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |  2 +-
> >  arch/arm/mach-sunxi/Kconfig                 | 41 +++++++++++++--------
> >  arch/arm/mach-sunxi/board.c                 |  2 +-
> >  arch/arm/mach-sunxi/cpu_info.c              |  2 +
> >  arch/arm/mach-sunxi/dram_sunxi_dw.c         | 18 ++++-----
> >  arch/arm/mach-sunxi/spl_spi_sunxi.c         |  2 +-
> >  board/sunxi/board.c                         |  2 +-
> >  configs/pinecube_defconfig                  |  3 +-
> >  drivers/clk/sunxi/Kconfig                   |  2 +-
> >  drivers/phy/allwinner/Kconfig               |  2 +-
> >  drivers/pinctrl/sunxi/Kconfig               |  2 +-
> >  drivers/power/Kconfig                       |  2 +-
> >  14 files changed, 47 insertions(+), 37 deletions(-)
> > 
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 0dc7e190eb93..3d93679058c8 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -646,7 +646,7 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
> >  	sun8i-r40-oka40i-c.dtb \
> >  	sun8i-t3-cqa3t-bv3.dtb \
> >  	sun8i-v40-bananapi-m2-berry.dtb
> > -dtb-$(CONFIG_MACH_SUN8I_V3S) += \
> > +dtb-$(CONFIG_MACH_SUN8I_V3_V3S) += \
> >  	sun8i-s3-elimo-initium.dtb \
> >  	sun8i-s3-pinecube.dtb \
> >  	sun8i-v3-sl631-imx179.dtb \
> > diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
> > index 768c6572d6b7..bd9dd97b890b 100644
> > --- a/arch/arm/include/asm/arch-sunxi/cpu.h
> > +++ b/arch/arm/include/asm/arch-sunxi/cpu.h
> > @@ -18,7 +18,7 @@
> >  
> >  #define SOCID_A64	0x1689
> >  #define SOCID_H3	0x1680
> > -#define SOCID_V3S	0x1681
> > +#define SOCID_V3_V3S	0x1681
> >  #define SOCID_H5	0x1718
> >  #define SOCID_R40	0x1701
> >  
> > diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> > index f023a4cfd934..3212b818286c 100644
> > --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> > +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> > @@ -13,7 +13,7 @@
> >  
> >  #if defined(CONFIG_SUNXI_GEN_SUN6I) && \
> >      !defined(CONFIG_MACH_SUN8I_R40) && \
> > -    !defined(CONFIG_MACH_SUN8I_V3S)
> > +    !defined(CONFIG_MACH_SUN8I_V3_V3S)
> >  #define SUNXI_SRAM_A2_BASE		0x00040000
> >  #ifdef CONFIG_MACH_SUN8I_H3
> >  #define SUNXI_SRAM_A2_SIZE		(48 * 1024)	/* 16+32 kiB */
> > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> > index 5a696095586e..f0faa9f80a23 100644
> > --- a/arch/arm/mach-sunxi/Kconfig
> > +++ b/arch/arm/mach-sunxi/Kconfig
> > @@ -476,17 +476,13 @@ config MACH_SUN8I_R528
> >  	select SUPPORT_SPL
> >  	select DRAM_SUN20I_D1
> >  
> > +config MACH_SUN8I_V3
> > +	bool "sun8i (Allwinner V3/S3/S3L)"
> > +	select MACH_SUN8I_V3_V3S
> > +
> >  config MACH_SUN8I_V3S
> > -	bool "sun8i (Allwinner V3/V3s/S3/S3L)"
> > -	select CPU_V7A
> > -	select CPU_V7_HAS_NONSEC
> > -	select CPU_V7_HAS_VIRT
> > -	select ARCH_SUPPORT_PSCI
> > -	select SUNXI_GEN_SUN6I
> > -	select SUNXI_DRAM_DW
> > -	select SUNXI_DRAM_DW_16BIT
> > -	select SUPPORT_SPL
> > -	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
> > +	bool "sun8i (Allwinner V3s)"
> > +	select MACH_SUN8I_V3_V3S
> >  
> >  config MACH_SUN9I
> >  	bool "sun9i (Allwinner A80)"
> > @@ -562,7 +558,20 @@ config MACH_SUN8I
> >  	default y if MACH_SUN8I_A83T
> >  	default y if MACH_SUNXI_H3_H5
> >  	default y if MACH_SUN8I_R40
> > -	default y if MACH_SUN8I_V3S
> > +	default y if MACH_SUN8I_V3_V3S
> > +
> > +config MACH_SUN8I_V3_V3S
> > +	bool "sun8i (Allwinner V3/V3s/S3/S3L)"
> > +	depends on MACH_SUN8I_V3 || MACH_SUN8I_V3S
> > +	select CPU_V7A
> > +	select CPU_V7_HAS_NONSEC
> > +	select CPU_V7_HAS_VIRT
> > +	select ARCH_SUPPORT_PSCI
> > +	select SUNXI_GEN_SUN6I
> > +	select SUNXI_DRAM_DW
> > +	select SUNXI_DRAM_DW_16BIT
> > +	select SUPPORT_SPL
> > +	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
> >  
> >  config RESERVE_ALLWINNER_BOOT0_HEADER
> >  	bool "reserve space for Allwinner boot0 header"
> > @@ -719,7 +728,7 @@ config DRAM_CLK
> >  	default 792 if MACH_SUN9I
> >  	default 648 if MACH_SUN8I_R40
> >  	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
> > -		       MACH_SUN8I_V3S
> > +		       MACH_SUN8I_V3_V3S
> >  	default 312 if MACH_SUN6I || MACH_SUN8I
> >  	default 672 if MACH_SUN50I
> >  	default 744 if MACH_SUN50I_H6
> > @@ -747,7 +756,7 @@ config DRAM_ZQ
> >  	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
> >  		       MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
> >  	default 127 if MACH_SUN7I
> > -	default 14779 if MACH_SUN8I_V3S
> > +	default 14779 if MACH_SUN8I_V3_V3S
> >  	default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
> >  	default 4145117 if MACH_SUN9I
> >  	default 3881915 if MACH_SUN50I
> > @@ -877,7 +886,7 @@ config SYS_SOC
> >  config SUNXI_MINIMUM_DRAM_MB
> >  	int "minimum DRAM size"
> >  	default 32 if MACH_SUNIV
> > -	default 64 if MACH_SUN8I_V3S
> > +	default 64 if MACH_SUN8I_V3_V3S
> >  	default 256
> >  	---help---
> >  	Minimum DRAM size expected on the board. Traditionally we assumed
> > @@ -963,7 +972,7 @@ config VIDEO_SUNXI
> >  	depends on !MACH_SUN8I_A83T
> >  	depends on !MACH_SUNXI_H3_H5
> >  	depends on !MACH_SUN8I_R40
> > -	depends on !MACH_SUN8I_V3S
> > +	depends on !MACH_SUN8I_V3_V3S
> >  	depends on !MACH_SUN9I
> >  	depends on !MACH_SUN50I
> >  	depends on !SUN50I_GEN_H6
> > @@ -1186,7 +1195,7 @@ config SPL_STACK_R_ADDR
> >  
> >  config SPL_SPI_SUNXI
> >  	bool "Support for SPI Flash on Allwinner SoCs in SPL"
> > -	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN8I_V3S || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2
> > +	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN8I_V3_V3S || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2
> >  	help
> >  	  Enable support for SPI Flash. This option allows SPL to read from
> >  	  sunxi SPI Flash. It uses the same method as the boot ROM, so does
> > diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> > index fb4837c2082d..a1a02b0fae50 100644
> > --- a/arch/arm/mach-sunxi/board.c
> > +++ b/arch/arm/mach-sunxi/board.c
> > @@ -149,7 +149,7 @@ static int gpio_init(void)
> >  	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
> >  	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
> >  	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
> > -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
> > +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3_V3S)
> >  	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
> >  	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
> >  	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
> > diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
> > index c3a51d9956ec..5b03dcdc354d 100644
> > --- a/arch/arm/mach-sunxi/cpu_info.c
> > +++ b/arch/arm/mach-sunxi/cpu_info.c
> > @@ -90,6 +90,8 @@ int print_cpuinfo(void)
> >  	printf("CPU:   Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
> >  #elif defined CONFIG_MACH_SUN8I_R40
> >  	printf("CPU:   Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
> > +#elif defined CONFIG_MACH_SUN8I_V3
> > +	printf("CPU:   Allwinner V3/S3/S3L (SUN8I %04x)\n", sunxi_get_sram_id());
> >  #elif defined CONFIG_MACH_SUN8I_V3S
> >  	printf("CPU:   Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
> >  #elif defined CONFIG_MACH_SUN8I_R528
> > diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
> > index 4ed295909ceb..56d03027b933 100644
> > --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
> > +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
> > @@ -254,7 +254,7 @@ static void mctl_set_master_priority(uint16_t socid)
> >  	case SOCID_H3:
> >  		mctl_set_master_priority_h3();
> >  		return;
> > -	case SOCID_V3S:
> > +	case SOCID_V3_V3S:
> >  		mctl_set_master_priority_v3s();
> >  		return;
> >  	case SOCID_A64:
> > @@ -445,7 +445,7 @@ static void mctl_sys_init(uint16_t socid, struct dram_para *para)
> >  				CCM_DRAMCLK_CFG_DIV(1) |
> >  				CCM_DRAMCLK_CFG_SRC_PLL11 |
> >  				CCM_DRAMCLK_CFG_UPD);
> > -	} else if (socid == SOCID_H3 || socid == SOCID_H5 || socid == SOCID_V3S) {
> > +	} else if (socid == SOCID_H3 || socid == SOCID_H5 || socid == SOCID_V3_V3S) {
> >  		clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
> >  		clrsetbits_le32(&ccm->dram_clk_cfg,
> >  				CCM_DRAMCLK_CFG_DIV_MASK |
> > @@ -528,7 +528,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
> >  		/* dphy & aphy phase select 270 degree */
> >  		clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
> >  				(0x1 << 10) | (0x2 << 8));
> > -	} else if (socid == SOCID_V3S) {
> > +	} else if (socid == SOCID_V3_V3S) {
> >  		/* dx ddr_clk & hdr_clk dynamic mode */
> >  		clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
> >  
> > @@ -567,7 +567,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
> >  	mctl_set_bit_delays(para);
> >  	udelay(50);
> >  
> > -	if (socid == SOCID_V3S) {
> > +	if (socid == SOCID_V3_V3S) {
> >  		mctl_v3s_zq_calibration_quirk(para);
> >  
> >  		mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
> > @@ -636,7 +636,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
> >  	udelay(10);
> >  
> >  	/* set PGCR3, CKE polarity */
> > -	if (socid == SOCID_H3 || socid == SOCID_V3S)
> > +	if (socid == SOCID_H3 || socid == SOCID_V3_V3S)
> >  		writel(0x00aa0060, &mctl_ctl->pgcr[3]);
> >  	else if (socid == SOCID_A64 || socid == SOCID_H5 || socid == SOCID_R40)
> >  		writel(0xc0aa0060, &mctl_ctl->pgcr[3]);
> > @@ -758,7 +758,7 @@ static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
> >  	   0,  0,  0,  0,  0,  0,  0,  0,			\
> >  	   0,  0,  0,  0,  0,  0,  0      }
> >  
> > -#define SUN8I_V3S_DX_READ_DELAYS					\
> > +#define SUN8I_V3S_DX_READ_DELAYS				\
> >  	{{  8,  8,  8,  8,  8,  8,  8,  8,  8,  0,  0 },	\
> >  	 {  7,  7,  7,  7,  7,  7,  7,  7,  7,  0,  0 },	\
> >  	 {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },	\
> > @@ -851,7 +851,7 @@ unsigned long sunxi_dram_init(void)
> >  		.dx_read_delays  = SUN8I_H3_DX_READ_DELAYS,
> >  		.dx_write_delays = SUN8I_H3_DX_WRITE_DELAYS,
> >  		.ac_delays	 = SUN8I_H3_AC_DELAYS,
> > -#elif defined(CONFIG_MACH_SUN8I_V3S)
> > +#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
> >  		.dx_read_delays  = SUN8I_V3S_DX_READ_DELAYS,
> >  		.dx_write_delays = SUN8I_V3S_DX_WRITE_DELAYS,
> >  		.ac_delays	 = SUN8I_V3S_AC_DELAYS,
> > @@ -878,8 +878,8 @@ unsigned long sunxi_dram_init(void)
> >  	uint16_t socid = SOCID_H3;
> >  #elif defined(CONFIG_MACH_SUN8I_R40)
> >  	uint16_t socid = SOCID_R40;
> > -#elif defined(CONFIG_MACH_SUN8I_V3S)
> > -	uint16_t socid = SOCID_V3S;
> > +#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
> > +	uint16_t socid = SOCID_V3_V3S;
> >  #elif defined(CONFIG_MACH_SUN50I)
> >  	uint16_t socid = SOCID_A64;
> >  #elif defined(CONFIG_MACH_SUN50I_H5)
> > diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
> > index 5f72e809952b..f6650652b42a 100644
> > --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
> > +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
> > @@ -141,7 +141,7 @@ static bool is_sun6i_gen_spi(void)
> >  	return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
> >  	       IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
> >  	       IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) ||
> > -	       IS_ENABLED(CONFIG_MACH_SUN8I_V3S);
> > +	       IS_ENABLED(CONFIG_MACH_SUN8I_V3_V3S);
> >  }
> >  
> >  static uintptr_t spi0_base_address(void)
> > diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> > index 2929bc17f084..6520636ffab5 100644
> > --- a/board/sunxi/board.c
> > +++ b/board/sunxi/board.c
> > @@ -68,7 +68,7 @@ void i2c_init_board(void)
> >  	sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
> >  	sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
> >  	clock_twi_onoff(0, 1);
> > -#elif defined(CONFIG_MACH_SUN8I_V3S)
> > +#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
> >  	sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
> >  	sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
> >  	clock_twi_onoff(0, 1);
> > diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig
> > index 7567a6aa7394..088dd6f8630a 100644
> > --- a/configs/pinecube_defconfig
> > +++ b/configs/pinecube_defconfig
> > @@ -2,8 +2,7 @@ CONFIG_ARM=y
> >  CONFIG_ARCH_SUNXI=y
> >  CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube"
> >  CONFIG_SPL=y
> > -CONFIG_MACH_SUN8I_V3S=y
> > -CONFIG_SUNXI_DRAM_DDR3_1333=y
> > +CONFIG_MACH_SUN8I_V3=y
> >  CONFIG_DRAM_CLK=504
> >  CONFIG_DRAM_ODT_EN=y
> >  CONFIG_I2C0_ENABLE=y
> > diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
> > index 1c1cc82719cd..207d3bed7922 100644
> > --- a/drivers/clk/sunxi/Kconfig
> > +++ b/drivers/clk/sunxi/Kconfig
> > @@ -68,7 +68,7 @@ config CLK_SUN8I_R40
> >  
> >  config CLK_SUN8I_V3S
> >  	bool "Clock driver for Allwinner V3S"
> > -	default MACH_SUN8I_V3S
> > +	default MACH_SUN8I_V3_V3S
> >  	help
> >  	  This enables common clock driver support for platforms based
> >  	  on Allwinner V3S SoC.
> > diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
> > index bb0bd8d5f812..335eff0a8bac 100644
> > --- a/drivers/phy/allwinner/Kconfig
> > +++ b/drivers/phy/allwinner/Kconfig
> > @@ -5,7 +5,7 @@ config PHY_SUN4I_USB
> >  	bool "Allwinner Sun4I USB PHY driver"
> >  	depends on ARCH_SUNXI
> >  	depends on !MACH_SUN9I
> > -	default n if MACH_SUN8I_V3S
> > +	default n if MACH_SUN8I_V3_V3S
> >  	default y
> >  	select DM_REGULATOR
> >  	select PHY
> > diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> > index 543149922998..59039917158e 100644
> > --- a/drivers/pinctrl/sunxi/Kconfig
> > +++ b/drivers/pinctrl/sunxi/Kconfig
> > @@ -76,7 +76,7 @@ config PINCTRL_SUN8I_H3_R
> >  
> >  config PINCTRL_SUN8I_V3S
> >  	bool "Support for the Allwinner V3s PIO"
> > -	default MACH_SUN8I_V3S
> > +	default MACH_SUN8I_V3_V3S
> >  	select PINCTRL_SUNXI
> >  
> >  config PINCTRL_SUN9I_A80
> > diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
> > index eed65058e667..cdb3d712389c 100644
> > --- a/drivers/power/Kconfig
> > +++ b/drivers/power/Kconfig
> > @@ -75,7 +75,7 @@ config AXP152_POWER
> >  
> >  config AXP209_POWER
> >  	bool "axp209 pmic support"
> > -	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3S
> > +	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3
> >  	select AXP_PMIC_BUS
> >  	select CMD_POWEROFF
> >  	---help---
> 

-- 
Paul Kocialkowski,

Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/

Expert in multimedia, graphics and embedded hardware support with Linux.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 02/11] sunxi: Split V3 and V3s support with a common option
  2025-08-06 17:24     ` Paul Kocialkowski
@ 2025-08-08  3:48       ` Icenowy Zheng
  2025-10-21 14:02       ` Andre Przywara
  1 sibling, 0 replies; 19+ messages in thread
From: Icenowy Zheng @ 2025-08-08  3:48 UTC (permalink / raw)
  To: Paul Kocialkowski, Andre Przywara
  Cc: linux-sunxi, u-boot, Tom Rini, Jagan Teki, Chen-Yu Tsai,
	Icenowy Zheng, Paul Kocialkowski

在 2025-08-06星期三的 19:24 +0200，Paul Kocialkowski写道：
> Hi,
> 
> Le Wed 06 Aug 25, 01:21, Andre Przywara a écrit :
> > On Tue,  5 Aug 2025 19:48:18 +0200
> > Paul Kocialkowski <paulk@sys-base.io> wrote:
> > 
> > Hi Paul,
> > 
> > > From: Paul Kocialkowski <contact@paulk.fr>
> > > 
> > > There are a few notable differences that are relevant to U-Boot,
> > > including:
> > > - different DRAM configuration due to the co-packaged DRAM chip
> > > in V3s;
> > > - use of an external PMIC (typically an AXP209) on V3;
> > > - extra pins available on V3, e.g. for UART1.
> > 
> > Mmmh, to be honest I am not really convinced this is useful. The
> > patch
> > below looks roughly like a big s/MACH_SUN8I_V3S/MACH_SUN8I_V3_V3S/,
> > which I am not sure is really worth it. We had not super accurate
> > names
> > before, after all those are just marketing names that Allwinner
> > once
> > came up with. So we use MACH_SUN55I_A523, even though it's mostly
> > A527 or T527 chips, really, for instance.
> 
> Yes I think this case is a bit different because there is actually a
> difference
> not just in the packaging and pins available but also because a dram
> die is
> co-packaged with the sun8i chip.
> 
> > For the three actually differing items you mention above: I think
> > we
> > can treat the DRAM and external PMIC like board options, and could
> > describe the extra pins either unconditionally or drop them at all
> > (see
> > my comment there).
> > 
> > What do you think? Is that distinction on the Kconfig level really
> > necessary?
> 
> I think it is preferable because the DRAM die co-packaged with the
> chip is
> definitely not a board-specific choice, so I would rather see the
> DRAM-related
> details handled by the common Kconfig rather than duplicated over
> each V3s
> board.

I think we have a similar case here -- F1C100s vs F1C200s, copackaged
32M or 64M DRAM.

Existing F1C200s board (LcTech Pi) just overrides SUNXI_MINIMUM_DRAM_MB
in defconfig.

> 
> For the PMIC it mostly remains a board-specific option and is not
> enabled by
> default anyway, it's just the defaults that are updated. Apparently
> there are
> designs with V3s that use an AXP209 PMIC so the defaults could
> actually go
> to the common option.

Allwinner suggests V3s to be used with PMIC, it's just Sipeed being
crazy here to make a pill-sized board (and omitted PMIC as a tradeoff).

> 
> Another approach here could be to keep a single MACH_SUN8I_V3 option
> and have
> an extra one to select the co-packaged DRAM that only V3s boards
> would select
> in their config. If it's the rename that bothers you we could keep
> the
> MACH_SUN8I_V3S name but I think it would be significantly more
> confusing.
> 
> What do you think?
> 
> Paul
> 
> > Cheers,
> > Andre
> > 
> > > Move the exiting V3s config to a common option and introduce
> > > specific options
> > > for V3s and V3 to set specific aspects and reflect this all round
> > > the tree.
> > > 
> > > Also update the pinecube config to reflect the updated defaults.
> > > 
> > > Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
> > > ---
> > >  arch/arm/dts/Makefile                       |  2 +-
> > >  arch/arm/include/asm/arch-sunxi/cpu.h       |  2 +-
> > >  arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |  2 +-
> > >  arch/arm/mach-sunxi/Kconfig                 | 41 +++++++++++++--
> > > ------
> > >  arch/arm/mach-sunxi/board.c                 |  2 +-
> > >  arch/arm/mach-sunxi/cpu_info.c              |  2 +
> > >  arch/arm/mach-sunxi/dram_sunxi_dw.c         | 18 ++++-----
> > >  arch/arm/mach-sunxi/spl_spi_sunxi.c         |  2 +-
> > >  board/sunxi/board.c                         |  2 +-
> > >  configs/pinecube_defconfig                  |  3 +-
> > >  drivers/clk/sunxi/Kconfig                   |  2 +-
> > >  drivers/phy/allwinner/Kconfig               |  2 +-
> > >  drivers/pinctrl/sunxi/Kconfig               |  2 +-
> > >  drivers/power/Kconfig                       |  2 +-
> > >  14 files changed, 47 insertions(+), 37 deletions(-)
> > > 
> > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > > index 0dc7e190eb93..3d93679058c8 100644
> > > --- a/arch/arm/dts/Makefile
> > > +++ b/arch/arm/dts/Makefile
> > > @@ -646,7 +646,7 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
> > >         sun8i-r40-oka40i-c.dtb \
> > >         sun8i-t3-cqa3t-bv3.dtb \
> > >         sun8i-v40-bananapi-m2-berry.dtb
> > > -dtb-$(CONFIG_MACH_SUN8I_V3S) += \
> > > +dtb-$(CONFIG_MACH_SUN8I_V3_V3S) += \
> > >         sun8i-s3-elimo-initium.dtb \
> > >         sun8i-s3-pinecube.dtb \
> > >         sun8i-v3-sl631-imx179.dtb \
> > > diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
> > > b/arch/arm/include/asm/arch-sunxi/cpu.h
> > > index 768c6572d6b7..bd9dd97b890b 100644
> > > --- a/arch/arm/include/asm/arch-sunxi/cpu.h
> > > +++ b/arch/arm/include/asm/arch-sunxi/cpu.h
> > > @@ -18,7 +18,7 @@
> > >  
> > >  #define SOCID_A64      0x1689
> > >  #define SOCID_H3       0x1680
> > > -#define SOCID_V3S      0x1681
> > > +#define SOCID_V3_V3S   0x1681
> > >  #define SOCID_H5       0x1718
> > >  #define SOCID_R40      0x1701
> > >  
> > > diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> > > b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> > > index f023a4cfd934..3212b818286c 100644
> > > --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> > > +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> > > @@ -13,7 +13,7 @@
> > >  
> > >  #if defined(CONFIG_SUNXI_GEN_SUN6I) && \
> > >      !defined(CONFIG_MACH_SUN8I_R40) && \
> > > -    !defined(CONFIG_MACH_SUN8I_V3S)
> > > +    !defined(CONFIG_MACH_SUN8I_V3_V3S)
> > >  #define SUNXI_SRAM_A2_BASE             0x00040000
> > >  #ifdef CONFIG_MACH_SUN8I_H3
> > >  #define SUNXI_SRAM_A2_SIZE             (48 * 1024)     /* 16+32
> > > kiB */
> > > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-
> > > sunxi/Kconfig
> > > index 5a696095586e..f0faa9f80a23 100644
> > > --- a/arch/arm/mach-sunxi/Kconfig
> > > +++ b/arch/arm/mach-sunxi/Kconfig
> > > @@ -476,17 +476,13 @@ config MACH_SUN8I_R528
> > >         select SUPPORT_SPL
> > >         select DRAM_SUN20I_D1
> > >  
> > > +config MACH_SUN8I_V3
> > > +       bool "sun8i (Allwinner V3/S3/S3L)"
> > > +       select MACH_SUN8I_V3_V3S
> > > +
> > >  config MACH_SUN8I_V3S
> > > -       bool "sun8i (Allwinner V3/V3s/S3/S3L)"
> > > -       select CPU_V7A
> > > -       select CPU_V7_HAS_NONSEC
> > > -       select CPU_V7_HAS_VIRT
> > > -       select ARCH_SUPPORT_PSCI
> > > -       select SUNXI_GEN_SUN6I
> > > -       select SUNXI_DRAM_DW
> > > -       select SUNXI_DRAM_DW_16BIT
> > > -       select SUPPORT_SPL
> > > -       select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
> > > +       bool "sun8i (Allwinner V3s)"
> > > +       select MACH_SUN8I_V3_V3S
> > >  
> > >  config MACH_SUN9I
> > >         bool "sun9i (Allwinner A80)"
> > > @@ -562,7 +558,20 @@ config MACH_SUN8I
> > >         default y if MACH_SUN8I_A83T
> > >         default y if MACH_SUNXI_H3_H5
> > >         default y if MACH_SUN8I_R40
> > > -       default y if MACH_SUN8I_V3S
> > > +       default y if MACH_SUN8I_V3_V3S
> > > +
> > > +config MACH_SUN8I_V3_V3S
> > > +       bool "sun8i (Allwinner V3/V3s/S3/S3L)"
> > > +       depends on MACH_SUN8I_V3 || MACH_SUN8I_V3S
> > > +       select CPU_V7A
> > > +       select CPU_V7_HAS_NONSEC
> > > +       select CPU_V7_HAS_VIRT
> > > +       select ARCH_SUPPORT_PSCI
> > > +       select SUNXI_GEN_SUN6I
> > > +       select SUNXI_DRAM_DW
> > > +       select SUNXI_DRAM_DW_16BIT
> > > +       select SUPPORT_SPL
> > > +       select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
> > >  
> > >  config RESERVE_ALLWINNER_BOOT0_HEADER
> > >         bool "reserve space for Allwinner boot0 header"
> > > @@ -719,7 +728,7 @@ config DRAM_CLK
> > >         default 792 if MACH_SUN9I
> > >         default 648 if MACH_SUN8I_R40
> > >         default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I ||
> > > \
> > > -                      MACH_SUN8I_V3S
> > > +                      MACH_SUN8I_V3_V3S
> > >         default 312 if MACH_SUN6I || MACH_SUN8I
> > >         default 672 if MACH_SUN50I
> > >         default 744 if MACH_SUN50I_H6
> > > @@ -747,7 +756,7 @@ config DRAM_ZQ
> > >         default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I ||
> > > \
> > >                        MACH_SUN8I_A23 || MACH_SUN8I_A33 ||
> > > MACH_SUN8I_A83T
> > >         default 127 if MACH_SUN7I
> > > -       default 14779 if MACH_SUN8I_V3S
> > > +       default 14779 if MACH_SUN8I_V3_V3S
> > >         default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 ||
> > > MACH_SUN50I_H6
> > >         default 4145117 if MACH_SUN9I
> > >         default 3881915 if MACH_SUN50I
> > > @@ -877,7 +886,7 @@ config SYS_SOC
> > >  config SUNXI_MINIMUM_DRAM_MB
> > >         int "minimum DRAM size"
> > >         default 32 if MACH_SUNIV
> > > -       default 64 if MACH_SUN8I_V3S
> > > +       default 64 if MACH_SUN8I_V3_V3S
> > >         default 256
> > >         ---help---
> > >         Minimum DRAM size expected on the board. Traditionally we
> > > assumed
> > > @@ -963,7 +972,7 @@ config VIDEO_SUNXI
> > >         depends on !MACH_SUN8I_A83T
> > >         depends on !MACH_SUNXI_H3_H5
> > >         depends on !MACH_SUN8I_R40
> > > -       depends on !MACH_SUN8I_V3S
> > > +       depends on !MACH_SUN8I_V3_V3S
> > >         depends on !MACH_SUN9I
> > >         depends on !MACH_SUN50I
> > >         depends on !SUN50I_GEN_H6
> > > @@ -1186,7 +1195,7 @@ config SPL_STACK_R_ADDR
> > >  
> > >  config SPL_SPI_SUNXI
> > >         bool "Support for SPI Flash on Allwinner SoCs in SPL"
> > > -       depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I ||
> > > MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 ||
> > > MACH_SUN8I_V3S || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2
> > > +       depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I ||
> > > MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 ||
> > > MACH_SUN8I_V3_V3S || SUN50I_GEN_H6 || MACH_SUNIV ||
> > > SUNXI_GEN_NCAT2
> > >         help
> > >           Enable support for SPI Flash. This option allows SPL to
> > > read from
> > >           sunxi SPI Flash. It uses the same method as the boot
> > > ROM, so does
> > > diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-
> > > sunxi/board.c
> > > index fb4837c2082d..a1a02b0fae50 100644
> > > --- a/arch/arm/mach-sunxi/board.c
> > > +++ b/arch/arm/mach-sunxi/board.c
> > > @@ -149,7 +149,7 @@ static int gpio_init(void)
> > >         sunxi_gpio_set_cfgpin(SUNXI_GPB(9),
> > > SUN8I_A83T_GPB_UART0);
> > >         sunxi_gpio_set_cfgpin(SUNXI_GPB(10),
> > > SUN8I_A83T_GPB_UART0);
> > >         sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
> > > -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
> > > +#elif CONFIG_CONS_INDEX == 1 &&
> > > defined(CONFIG_MACH_SUN8I_V3_V3S)
> > >         sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
> > >         sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
> > >         sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
> > > diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-
> > > sunxi/cpu_info.c
> > > index c3a51d9956ec..5b03dcdc354d 100644
> > > --- a/arch/arm/mach-sunxi/cpu_info.c
> > > +++ b/arch/arm/mach-sunxi/cpu_info.c
> > > @@ -90,6 +90,8 @@ int print_cpuinfo(void)
> > >         printf("CPU:   Allwinner H3 (SUN8I %04x)\n",
> > > sunxi_get_sram_id());
> > >  #elif defined CONFIG_MACH_SUN8I_R40
> > >         printf("CPU:   Allwinner R40 (SUN8I %04x)\n",
> > > sunxi_get_sram_id());
> > > +#elif defined CONFIG_MACH_SUN8I_V3
> > > +       printf("CPU:   Allwinner V3/S3/S3L (SUN8I %04x)\n",
> > > sunxi_get_sram_id());
> > >  #elif defined CONFIG_MACH_SUN8I_V3S
> > >         printf("CPU:   Allwinner V3s (SUN8I %04x)\n",
> > > sunxi_get_sram_id());
> > >  #elif defined CONFIG_MACH_SUN8I_R528
> > > diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-
> > > sunxi/dram_sunxi_dw.c
> > > index 4ed295909ceb..56d03027b933 100644
> > > --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
> > > +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
> > > @@ -254,7 +254,7 @@ static void mctl_set_master_priority(uint16_t
> > > socid)
> > >         case SOCID_H3:
> > >                 mctl_set_master_priority_h3();
> > >                 return;
> > > -       case SOCID_V3S:
> > > +       case SOCID_V3_V3S:
> > >                 mctl_set_master_priority_v3s();
> > >                 return;
> > >         case SOCID_A64:
> > > @@ -445,7 +445,7 @@ static void mctl_sys_init(uint16_t socid,
> > > struct dram_para *para)
> > >                                 CCM_DRAMCLK_CFG_DIV(1) |
> > >                                 CCM_DRAMCLK_CFG_SRC_PLL11 |
> > >                                 CCM_DRAMCLK_CFG_UPD);
> > > -       } else if (socid == SOCID_H3 || socid == SOCID_H5 ||
> > > socid == SOCID_V3S) {
> > > +       } else if (socid == SOCID_H3 || socid == SOCID_H5 ||
> > > socid == SOCID_V3_V3S) {
> > >                 clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000,
> > > false);
> > >                 clrsetbits_le32(&ccm->dram_clk_cfg,
> > >                                 CCM_DRAMCLK_CFG_DIV_MASK |
> > > @@ -528,7 +528,7 @@ static int mctl_channel_init(uint16_t socid,
> > > struct dram_para *para)
> > >                 /* dphy & aphy phase select 270 degree */
> > >                 clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) |
> > > (0x3 << 8),
> > >                                 (0x1 << 10) | (0x2 << 8));
> > > -       } else if (socid == SOCID_V3S) {
> > > +       } else if (socid == SOCID_V3_V3S) {
> > >                 /* dx ddr_clk & hdr_clk dynamic mode */
> > >                 clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) |
> > > (0x3 << 12));
> > >  
> > > @@ -567,7 +567,7 @@ static int mctl_channel_init(uint16_t socid,
> > > struct dram_para *para)
> > >         mctl_set_bit_delays(para);
> > >         udelay(50);
> > >  
> > > -       if (socid == SOCID_V3S) {
> > > +       if (socid == SOCID_V3_V3S) {
> > >                 mctl_v3s_zq_calibration_quirk(para);
> > >  
> > >                 mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST
> > > |
> > > @@ -636,7 +636,7 @@ static int mctl_channel_init(uint16_t socid,
> > > struct dram_para *para)
> > >         udelay(10);
> > >  
> > >         /* set PGCR3, CKE polarity */
> > > -       if (socid == SOCID_H3 || socid == SOCID_V3S)
> > > +       if (socid == SOCID_H3 || socid == SOCID_V3_V3S)
> > >                 writel(0x00aa0060, &mctl_ctl->pgcr[3]);
> > >         else if (socid == SOCID_A64 || socid == SOCID_H5 || socid
> > > == SOCID_R40)
> > >                 writel(0xc0aa0060, &mctl_ctl->pgcr[3]);
> > > @@ -758,7 +758,7 @@ static void
> > > mctl_auto_detect_dram_size(uint16_t socid, struct dram_para
> > > *para)
> > >            0,  0,  0,  0,  0,  0,  0,  0,                       \
> > >            0,  0,  0,  0,  0,  0,  0      }
> > >  
> > > -#define
> > > SUN8I_V3S_DX_READ_DELAYS                                       \
> > > +#define SUN8I_V3S_DX_READ_DELAYS                               \
> > >         {{  8,  8,  8,  8,  8,  8,  8,  8,  8,  0,  0 },        \
> > >          {  7,  7,  7,  7,  7,  7,  7,  7,  7,  0,  0 },        \
> > >          {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },        \
> > > @@ -851,7 +851,7 @@ unsigned long sunxi_dram_init(void)
> > >                 .dx_read_delays  = SUN8I_H3_DX_READ_DELAYS,
> > >                 .dx_write_delays = SUN8I_H3_DX_WRITE_DELAYS,
> > >                 .ac_delays       = SUN8I_H3_AC_DELAYS,
> > > -#elif defined(CONFIG_MACH_SUN8I_V3S)
> > > +#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
> > >                 .dx_read_delays  = SUN8I_V3S_DX_READ_DELAYS,
> > >                 .dx_write_delays = SUN8I_V3S_DX_WRITE_DELAYS,
> > >                 .ac_delays       = SUN8I_V3S_AC_DELAYS,
> > > @@ -878,8 +878,8 @@ unsigned long sunxi_dram_init(void)
> > >         uint16_t socid = SOCID_H3;
> > >  #elif defined(CONFIG_MACH_SUN8I_R40)
> > >         uint16_t socid = SOCID_R40;
> > > -#elif defined(CONFIG_MACH_SUN8I_V3S)
> > > -       uint16_t socid = SOCID_V3S;
> > > +#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
> > > +       uint16_t socid = SOCID_V3_V3S;
> > >  #elif defined(CONFIG_MACH_SUN50I)
> > >         uint16_t socid = SOCID_A64;
> > >  #elif defined(CONFIG_MACH_SUN50I_H5)
> > > diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-
> > > sunxi/spl_spi_sunxi.c
> > > index 5f72e809952b..f6650652b42a 100644
> > > --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
> > > +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
> > > @@ -141,7 +141,7 @@ static bool is_sun6i_gen_spi(void)
> > >         return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
> > >                IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
> > >                IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) ||
> > > -              IS_ENABLED(CONFIG_MACH_SUN8I_V3S);
> > > +              IS_ENABLED(CONFIG_MACH_SUN8I_V3_V3S);
> > >  }
> > >  
> > >  static uintptr_t spi0_base_address(void)
> > > diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> > > index 2929bc17f084..6520636ffab5 100644
> > > --- a/board/sunxi/board.c
> > > +++ b/board/sunxi/board.c
> > > @@ -68,7 +68,7 @@ void i2c_init_board(void)
> > >         sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
> > >         sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
> > >         clock_twi_onoff(0, 1);
> > > -#elif defined(CONFIG_MACH_SUN8I_V3S)
> > > +#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
> > >         sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
> > >         sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
> > >         clock_twi_onoff(0, 1);
> > > diff --git a/configs/pinecube_defconfig
> > > b/configs/pinecube_defconfig
> > > index 7567a6aa7394..088dd6f8630a 100644
> > > --- a/configs/pinecube_defconfig
> > > +++ b/configs/pinecube_defconfig
> > > @@ -2,8 +2,7 @@ CONFIG_ARM=y
> > >  CONFIG_ARCH_SUNXI=y
> > >  CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube"
> > >  CONFIG_SPL=y
> > > -CONFIG_MACH_SUN8I_V3S=y
> > > -CONFIG_SUNXI_DRAM_DDR3_1333=y
> > > +CONFIG_MACH_SUN8I_V3=y
> > >  CONFIG_DRAM_CLK=504
> > >  CONFIG_DRAM_ODT_EN=y
> > >  CONFIG_I2C0_ENABLE=y
> > > diff --git a/drivers/clk/sunxi/Kconfig
> > > b/drivers/clk/sunxi/Kconfig
> > > index 1c1cc82719cd..207d3bed7922 100644
> > > --- a/drivers/clk/sunxi/Kconfig
> > > +++ b/drivers/clk/sunxi/Kconfig
> > > @@ -68,7 +68,7 @@ config CLK_SUN8I_R40
> > >  
> > >  config CLK_SUN8I_V3S
> > >         bool "Clock driver for Allwinner V3S"
> > > -       default MACH_SUN8I_V3S
> > > +       default MACH_SUN8I_V3_V3S
> > >         help
> > >           This enables common clock driver support for platforms
> > > based
> > >           on Allwinner V3S SoC.
> > > diff --git a/drivers/phy/allwinner/Kconfig
> > > b/drivers/phy/allwinner/Kconfig
> > > index bb0bd8d5f812..335eff0a8bac 100644
> > > --- a/drivers/phy/allwinner/Kconfig
> > > +++ b/drivers/phy/allwinner/Kconfig
> > > @@ -5,7 +5,7 @@ config PHY_SUN4I_USB
> > >         bool "Allwinner Sun4I USB PHY driver"
> > >         depends on ARCH_SUNXI
> > >         depends on !MACH_SUN9I
> > > -       default n if MACH_SUN8I_V3S
> > > +       default n if MACH_SUN8I_V3_V3S
> > >         default y
> > >         select DM_REGULATOR
> > >         select PHY
> > > diff --git a/drivers/pinctrl/sunxi/Kconfig
> > > b/drivers/pinctrl/sunxi/Kconfig
> > > index 543149922998..59039917158e 100644
> > > --- a/drivers/pinctrl/sunxi/Kconfig
> > > +++ b/drivers/pinctrl/sunxi/Kconfig
> > > @@ -76,7 +76,7 @@ config PINCTRL_SUN8I_H3_R
> > >  
> > >  config PINCTRL_SUN8I_V3S
> > >         bool "Support for the Allwinner V3s PIO"
> > > -       default MACH_SUN8I_V3S
> > > +       default MACH_SUN8I_V3_V3S
> > >         select PINCTRL_SUNXI
> > >  
> > >  config PINCTRL_SUN9I_A80
> > > diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
> > > index eed65058e667..cdb3d712389c 100644
> > > --- a/drivers/power/Kconfig
> > > +++ b/drivers/power/Kconfig
> > > @@ -75,7 +75,7 @@ config AXP152_POWER
> > >  
> > >  config AXP209_POWER
> > >         bool "axp209 pmic support"
> > > -       depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I ||
> > > MACH_SUN8I_V3S
> > > +       depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I ||
> > > MACH_SUN8I_V3
> > >         select AXP_PMIC_BUS
> > >         select CMD_POWEROFF
> > >         ---help---
> > 
> 


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 02/11] sunxi: Split V3 and V3s support with a common option
  2025-08-06 17:24     ` Paul Kocialkowski
  2025-08-08  3:48       ` Icenowy Zheng
@ 2025-10-21 14:02       ` Andre Przywara
  1 sibling, 0 replies; 19+ messages in thread
From: Andre Przywara @ 2025-10-21 14:02 UTC (permalink / raw)
  To: Paul Kocialkowski
  Cc: linux-sunxi, u-boot, Tom Rini, Jagan Teki, Chen-Yu Tsai,
	Icenowy Zheng, Paul Kocialkowski

On Wed, 6 Aug 2025 19:24:47 +0200
Paul Kocialkowski <paulk@sys-base.io> wrote:

Hi,

sorry for the late reply, had to think a bit about this.

> Le Wed 06 Aug 25, 01:21, Andre Przywara a écrit :
> > On Tue,  5 Aug 2025 19:48:18 +0200
> > Paul Kocialkowski <paulk@sys-base.io> wrote:
> > 
> > Hi Paul,
> >   
> > > From: Paul Kocialkowski <contact@paulk.fr>
> > > 
> > > There are a few notable differences that are relevant to U-Boot, including:
> > > - different DRAM configuration due to the co-packaged DRAM chip in V3s;
> > > - use of an external PMIC (typically an AXP209) on V3;
> > > - extra pins available on V3, e.g. for UART1.  
> > 
> > Mmmh, to be honest I am not really convinced this is useful. The patch
> > below looks roughly like a big s/MACH_SUN8I_V3S/MACH_SUN8I_V3_V3S/,
> > which I am not sure is really worth it. We had not super accurate names
> > before, after all those are just marketing names that Allwinner once
> > came up with. So we use MACH_SUN55I_A523, even though it's mostly
> > A527 or T527 chips, really, for instance.  
> 
> Yes I think this case is a bit different because there is actually a difference
> not just in the packaging and pins available but also because a dram die is
> co-packaged with the sun8i chip.

I still think it's an edge case of the normal DRAM-is-on-the-board scheme.
We can just treat is to be the same DRAM on all boards, which from a pure
DRAM init point of view is often the case anyway, even for non-co-packaged
DRAM. As Icenowy mentioned, we treat it like this for the F1C100s and
T113-s[34] (now).
So what is the actual DRAM difference? I am probably missing it, but I
can't seem to find any separate handling about this in this series?

> > For the three actually differing items you mention above: I think we
> > can treat the DRAM and external PMIC like board options, and could
> > describe the extra pins either unconditionally or drop them at all (see
> > my comment there).
> > 
> > What do you think? Is that distinction on the Kconfig level really
> > necessary?  
> 
> I think it is preferable because the DRAM die co-packaged with the chip is
> definitely not a board-specific choice, so I would rather see the DRAM-related
> details handled by the common Kconfig rather than duplicated over each V3s
> board.
>
> For the PMIC it mostly remains a board-specific option and is not enabled by
> default anyway, it's just the defaults that are updated. Apparently there are
> designs with V3s that use an AXP209 PMIC so the defaults could actually go
> to the common option.
> 
> Another approach here could be to keep a single MACH_SUN8I_V3 option and have
> an extra one to select the co-packaged DRAM that only V3s boards would select
> in their config. If it's the rename that bothers you we could keep the
> MACH_SUN8I_V3S name but I think it would be significantly more confusing.

Yes, I would prefer that: reduce the churn by keeping the current option,
even if the naming is not fully correct. We often go with the name of the
first available chip, and then I like to keep that even in light of new
names showing up: H616->H313/H618/H700, or A523->A527/T527, and
especially R528->T113, which is basically this very same case. 

And then have a special option to select the DRAM configs common to the V3s
or V3, maybe. But again, what would that be, exactly? Is this outside of
this series?

Cheers,
Andre

> 
> What do you think?
> 
> Paul
> 
> > Cheers,
> > Andre
> >   
> > > Move the exiting V3s config to a common option and introduce specific options
> > > for V3s and V3 to set specific aspects and reflect this all round the tree.
> > > 
> > > Also update the pinecube config to reflect the updated defaults.
> > > 
> > > Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
> > > ---
> > >  arch/arm/dts/Makefile                       |  2 +-
> > >  arch/arm/include/asm/arch-sunxi/cpu.h       |  2 +-
> > >  arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |  2 +-
> > >  arch/arm/mach-sunxi/Kconfig                 | 41 +++++++++++++--------
> > >  arch/arm/mach-sunxi/board.c                 |  2 +-
> > >  arch/arm/mach-sunxi/cpu_info.c              |  2 +
> > >  arch/arm/mach-sunxi/dram_sunxi_dw.c         | 18 ++++-----
> > >  arch/arm/mach-sunxi/spl_spi_sunxi.c         |  2 +-
> > >  board/sunxi/board.c                         |  2 +-
> > >  configs/pinecube_defconfig                  |  3 +-
> > >  drivers/clk/sunxi/Kconfig                   |  2 +-
> > >  drivers/phy/allwinner/Kconfig               |  2 +-
> > >  drivers/pinctrl/sunxi/Kconfig               |  2 +-
> > >  drivers/power/Kconfig                       |  2 +-
> > >  14 files changed, 47 insertions(+), 37 deletions(-)
> > > 
> > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > > index 0dc7e190eb93..3d93679058c8 100644
> > > --- a/arch/arm/dts/Makefile
> > > +++ b/arch/arm/dts/Makefile
> > > @@ -646,7 +646,7 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
> > >  	sun8i-r40-oka40i-c.dtb \
> > >  	sun8i-t3-cqa3t-bv3.dtb \
> > >  	sun8i-v40-bananapi-m2-berry.dtb
> > > -dtb-$(CONFIG_MACH_SUN8I_V3S) += \
> > > +dtb-$(CONFIG_MACH_SUN8I_V3_V3S) += \
> > >  	sun8i-s3-elimo-initium.dtb \
> > >  	sun8i-s3-pinecube.dtb \
> > >  	sun8i-v3-sl631-imx179.dtb \
> > > diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
> > > index 768c6572d6b7..bd9dd97b890b 100644
> > > --- a/arch/arm/include/asm/arch-sunxi/cpu.h
> > > +++ b/arch/arm/include/asm/arch-sunxi/cpu.h
> > > @@ -18,7 +18,7 @@
> > >  
> > >  #define SOCID_A64	0x1689
> > >  #define SOCID_H3	0x1680
> > > -#define SOCID_V3S	0x1681
> > > +#define SOCID_V3_V3S	0x1681
> > >  #define SOCID_H5	0x1718
> > >  #define SOCID_R40	0x1701
> > >  
> > > diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> > > index f023a4cfd934..3212b818286c 100644
> > > --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> > > +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
> > > @@ -13,7 +13,7 @@
> > >  
> > >  #if defined(CONFIG_SUNXI_GEN_SUN6I) && \
> > >      !defined(CONFIG_MACH_SUN8I_R40) && \
> > > -    !defined(CONFIG_MACH_SUN8I_V3S)
> > > +    !defined(CONFIG_MACH_SUN8I_V3_V3S)
> > >  #define SUNXI_SRAM_A2_BASE		0x00040000
> > >  #ifdef CONFIG_MACH_SUN8I_H3
> > >  #define SUNXI_SRAM_A2_SIZE		(48 * 1024)	/* 16+32 kiB */
> > > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> > > index 5a696095586e..f0faa9f80a23 100644
> > > --- a/arch/arm/mach-sunxi/Kconfig
> > > +++ b/arch/arm/mach-sunxi/Kconfig
> > > @@ -476,17 +476,13 @@ config MACH_SUN8I_R528
> > >  	select SUPPORT_SPL
> > >  	select DRAM_SUN20I_D1
> > >  
> > > +config MACH_SUN8I_V3
> > > +	bool "sun8i (Allwinner V3/S3/S3L)"
> > > +	select MACH_SUN8I_V3_V3S
> > > +
> > >  config MACH_SUN8I_V3S
> > > -	bool "sun8i (Allwinner V3/V3s/S3/S3L)"
> > > -	select CPU_V7A
> > > -	select CPU_V7_HAS_NONSEC
> > > -	select CPU_V7_HAS_VIRT
> > > -	select ARCH_SUPPORT_PSCI
> > > -	select SUNXI_GEN_SUN6I
> > > -	select SUNXI_DRAM_DW
> > > -	select SUNXI_DRAM_DW_16BIT
> > > -	select SUPPORT_SPL
> > > -	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
> > > +	bool "sun8i (Allwinner V3s)"
> > > +	select MACH_SUN8I_V3_V3S
> > >  
> > >  config MACH_SUN9I
> > >  	bool "sun9i (Allwinner A80)"
> > > @@ -562,7 +558,20 @@ config MACH_SUN8I
> > >  	default y if MACH_SUN8I_A83T
> > >  	default y if MACH_SUNXI_H3_H5
> > >  	default y if MACH_SUN8I_R40
> > > -	default y if MACH_SUN8I_V3S
> > > +	default y if MACH_SUN8I_V3_V3S
> > > +
> > > +config MACH_SUN8I_V3_V3S
> > > +	bool "sun8i (Allwinner V3/V3s/S3/S3L)"
> > > +	depends on MACH_SUN8I_V3 || MACH_SUN8I_V3S
> > > +	select CPU_V7A
> > > +	select CPU_V7_HAS_NONSEC
> > > +	select CPU_V7_HAS_VIRT
> > > +	select ARCH_SUPPORT_PSCI
> > > +	select SUNXI_GEN_SUN6I
> > > +	select SUNXI_DRAM_DW
> > > +	select SUNXI_DRAM_DW_16BIT
> > > +	select SUPPORT_SPL
> > > +	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
> > >  
> > >  config RESERVE_ALLWINNER_BOOT0_HEADER
> > >  	bool "reserve space for Allwinner boot0 header"
> > > @@ -719,7 +728,7 @@ config DRAM_CLK
> > >  	default 792 if MACH_SUN9I
> > >  	default 648 if MACH_SUN8I_R40
> > >  	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
> > > -		       MACH_SUN8I_V3S
> > > +		       MACH_SUN8I_V3_V3S
> > >  	default 312 if MACH_SUN6I || MACH_SUN8I
> > >  	default 672 if MACH_SUN50I
> > >  	default 744 if MACH_SUN50I_H6
> > > @@ -747,7 +756,7 @@ config DRAM_ZQ
> > >  	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
> > >  		       MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
> > >  	default 127 if MACH_SUN7I
> > > -	default 14779 if MACH_SUN8I_V3S
> > > +	default 14779 if MACH_SUN8I_V3_V3S
> > >  	default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
> > >  	default 4145117 if MACH_SUN9I
> > >  	default 3881915 if MACH_SUN50I
> > > @@ -877,7 +886,7 @@ config SYS_SOC
> > >  config SUNXI_MINIMUM_DRAM_MB
> > >  	int "minimum DRAM size"
> > >  	default 32 if MACH_SUNIV
> > > -	default 64 if MACH_SUN8I_V3S
> > > +	default 64 if MACH_SUN8I_V3_V3S
> > >  	default 256
> > >  	---help---
> > >  	Minimum DRAM size expected on the board. Traditionally we assumed
> > > @@ -963,7 +972,7 @@ config VIDEO_SUNXI
> > >  	depends on !MACH_SUN8I_A83T
> > >  	depends on !MACH_SUNXI_H3_H5
> > >  	depends on !MACH_SUN8I_R40
> > > -	depends on !MACH_SUN8I_V3S
> > > +	depends on !MACH_SUN8I_V3_V3S
> > >  	depends on !MACH_SUN9I
> > >  	depends on !MACH_SUN50I
> > >  	depends on !SUN50I_GEN_H6
> > > @@ -1186,7 +1195,7 @@ config SPL_STACK_R_ADDR
> > >  
> > >  config SPL_SPI_SUNXI
> > >  	bool "Support for SPI Flash on Allwinner SoCs in SPL"
> > > -	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN8I_V3S || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2
> > > +	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN8I_V3_V3S || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2
> > >  	help
> > >  	  Enable support for SPI Flash. This option allows SPL to read from
> > >  	  sunxi SPI Flash. It uses the same method as the boot ROM, so does
> > > diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> > > index fb4837c2082d..a1a02b0fae50 100644
> > > --- a/arch/arm/mach-sunxi/board.c
> > > +++ b/arch/arm/mach-sunxi/board.c
> > > @@ -149,7 +149,7 @@ static int gpio_init(void)
> > >  	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
> > >  	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
> > >  	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
> > > -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
> > > +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3_V3S)
> > >  	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
> > >  	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
> > >  	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
> > > diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
> > > index c3a51d9956ec..5b03dcdc354d 100644
> > > --- a/arch/arm/mach-sunxi/cpu_info.c
> > > +++ b/arch/arm/mach-sunxi/cpu_info.c
> > > @@ -90,6 +90,8 @@ int print_cpuinfo(void)
> > >  	printf("CPU:   Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
> > >  #elif defined CONFIG_MACH_SUN8I_R40
> > >  	printf("CPU:   Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
> > > +#elif defined CONFIG_MACH_SUN8I_V3
> > > +	printf("CPU:   Allwinner V3/S3/S3L (SUN8I %04x)\n", sunxi_get_sram_id());
> > >  #elif defined CONFIG_MACH_SUN8I_V3S
> > >  	printf("CPU:   Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
> > >  #elif defined CONFIG_MACH_SUN8I_R528
> > > diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
> > > index 4ed295909ceb..56d03027b933 100644
> > > --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
> > > +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
> > > @@ -254,7 +254,7 @@ static void mctl_set_master_priority(uint16_t socid)
> > >  	case SOCID_H3:
> > >  		mctl_set_master_priority_h3();
> > >  		return;
> > > -	case SOCID_V3S:
> > > +	case SOCID_V3_V3S:
> > >  		mctl_set_master_priority_v3s();
> > >  		return;
> > >  	case SOCID_A64:
> > > @@ -445,7 +445,7 @@ static void mctl_sys_init(uint16_t socid, struct dram_para *para)
> > >  				CCM_DRAMCLK_CFG_DIV(1) |
> > >  				CCM_DRAMCLK_CFG_SRC_PLL11 |
> > >  				CCM_DRAMCLK_CFG_UPD);
> > > -	} else if (socid == SOCID_H3 || socid == SOCID_H5 || socid == SOCID_V3S) {
> > > +	} else if (socid == SOCID_H3 || socid == SOCID_H5 || socid == SOCID_V3_V3S) {
> > >  		clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
> > >  		clrsetbits_le32(&ccm->dram_clk_cfg,
> > >  				CCM_DRAMCLK_CFG_DIV_MASK |
> > > @@ -528,7 +528,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
> > >  		/* dphy & aphy phase select 270 degree */
> > >  		clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
> > >  				(0x1 << 10) | (0x2 << 8));
> > > -	} else if (socid == SOCID_V3S) {
> > > +	} else if (socid == SOCID_V3_V3S) {
> > >  		/* dx ddr_clk & hdr_clk dynamic mode */
> > >  		clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
> > >  
> > > @@ -567,7 +567,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
> > >  	mctl_set_bit_delays(para);
> > >  	udelay(50);
> > >  
> > > -	if (socid == SOCID_V3S) {
> > > +	if (socid == SOCID_V3_V3S) {
> > >  		mctl_v3s_zq_calibration_quirk(para);
> > >  
> > >  		mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
> > > @@ -636,7 +636,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
> > >  	udelay(10);
> > >  
> > >  	/* set PGCR3, CKE polarity */
> > > -	if (socid == SOCID_H3 || socid == SOCID_V3S)
> > > +	if (socid == SOCID_H3 || socid == SOCID_V3_V3S)
> > >  		writel(0x00aa0060, &mctl_ctl->pgcr[3]);
> > >  	else if (socid == SOCID_A64 || socid == SOCID_H5 || socid == SOCID_R40)
> > >  		writel(0xc0aa0060, &mctl_ctl->pgcr[3]);
> > > @@ -758,7 +758,7 @@ static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
> > >  	   0,  0,  0,  0,  0,  0,  0,  0,			\
> > >  	   0,  0,  0,  0,  0,  0,  0      }
> > >  
> > > -#define SUN8I_V3S_DX_READ_DELAYS					\
> > > +#define SUN8I_V3S_DX_READ_DELAYS				\
> > >  	{{  8,  8,  8,  8,  8,  8,  8,  8,  8,  0,  0 },	\
> > >  	 {  7,  7,  7,  7,  7,  7,  7,  7,  7,  0,  0 },	\
> > >  	 {  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },	\
> > > @@ -851,7 +851,7 @@ unsigned long sunxi_dram_init(void)
> > >  		.dx_read_delays  = SUN8I_H3_DX_READ_DELAYS,
> > >  		.dx_write_delays = SUN8I_H3_DX_WRITE_DELAYS,
> > >  		.ac_delays	 = SUN8I_H3_AC_DELAYS,
> > > -#elif defined(CONFIG_MACH_SUN8I_V3S)
> > > +#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
> > >  		.dx_read_delays  = SUN8I_V3S_DX_READ_DELAYS,
> > >  		.dx_write_delays = SUN8I_V3S_DX_WRITE_DELAYS,
> > >  		.ac_delays	 = SUN8I_V3S_AC_DELAYS,
> > > @@ -878,8 +878,8 @@ unsigned long sunxi_dram_init(void)
> > >  	uint16_t socid = SOCID_H3;
> > >  #elif defined(CONFIG_MACH_SUN8I_R40)
> > >  	uint16_t socid = SOCID_R40;
> > > -#elif defined(CONFIG_MACH_SUN8I_V3S)
> > > -	uint16_t socid = SOCID_V3S;
> > > +#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
> > > +	uint16_t socid = SOCID_V3_V3S;
> > >  #elif defined(CONFIG_MACH_SUN50I)
> > >  	uint16_t socid = SOCID_A64;
> > >  #elif defined(CONFIG_MACH_SUN50I_H5)
> > > diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
> > > index 5f72e809952b..f6650652b42a 100644
> > > --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
> > > +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
> > > @@ -141,7 +141,7 @@ static bool is_sun6i_gen_spi(void)
> > >  	return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
> > >  	       IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
> > >  	       IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) ||
> > > -	       IS_ENABLED(CONFIG_MACH_SUN8I_V3S);
> > > +	       IS_ENABLED(CONFIG_MACH_SUN8I_V3_V3S);
> > >  }
> > >  
> > >  static uintptr_t spi0_base_address(void)
> > > diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> > > index 2929bc17f084..6520636ffab5 100644
> > > --- a/board/sunxi/board.c
> > > +++ b/board/sunxi/board.c
> > > @@ -68,7 +68,7 @@ void i2c_init_board(void)
> > >  	sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
> > >  	sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
> > >  	clock_twi_onoff(0, 1);
> > > -#elif defined(CONFIG_MACH_SUN8I_V3S)
> > > +#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
> > >  	sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
> > >  	sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
> > >  	clock_twi_onoff(0, 1);
> > > diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig
> > > index 7567a6aa7394..088dd6f8630a 100644
> > > --- a/configs/pinecube_defconfig
> > > +++ b/configs/pinecube_defconfig
> > > @@ -2,8 +2,7 @@ CONFIG_ARM=y
> > >  CONFIG_ARCH_SUNXI=y
> > >  CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube"
> > >  CONFIG_SPL=y
> > > -CONFIG_MACH_SUN8I_V3S=y
> > > -CONFIG_SUNXI_DRAM_DDR3_1333=y
> > > +CONFIG_MACH_SUN8I_V3=y
> > >  CONFIG_DRAM_CLK=504
> > >  CONFIG_DRAM_ODT_EN=y
> > >  CONFIG_I2C0_ENABLE=y
> > > diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
> > > index 1c1cc82719cd..207d3bed7922 100644
> > > --- a/drivers/clk/sunxi/Kconfig
> > > +++ b/drivers/clk/sunxi/Kconfig
> > > @@ -68,7 +68,7 @@ config CLK_SUN8I_R40
> > >  
> > >  config CLK_SUN8I_V3S
> > >  	bool "Clock driver for Allwinner V3S"
> > > -	default MACH_SUN8I_V3S
> > > +	default MACH_SUN8I_V3_V3S
> > >  	help
> > >  	  This enables common clock driver support for platforms based
> > >  	  on Allwinner V3S SoC.
> > > diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
> > > index bb0bd8d5f812..335eff0a8bac 100644
> > > --- a/drivers/phy/allwinner/Kconfig
> > > +++ b/drivers/phy/allwinner/Kconfig
> > > @@ -5,7 +5,7 @@ config PHY_SUN4I_USB
> > >  	bool "Allwinner Sun4I USB PHY driver"
> > >  	depends on ARCH_SUNXI
> > >  	depends on !MACH_SUN9I
> > > -	default n if MACH_SUN8I_V3S
> > > +	default n if MACH_SUN8I_V3_V3S
> > >  	default y
> > >  	select DM_REGULATOR
> > >  	select PHY
> > > diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> > > index 543149922998..59039917158e 100644
> > > --- a/drivers/pinctrl/sunxi/Kconfig
> > > +++ b/drivers/pinctrl/sunxi/Kconfig
> > > @@ -76,7 +76,7 @@ config PINCTRL_SUN8I_H3_R
> > >  
> > >  config PINCTRL_SUN8I_V3S
> > >  	bool "Support for the Allwinner V3s PIO"
> > > -	default MACH_SUN8I_V3S
> > > +	default MACH_SUN8I_V3_V3S
> > >  	select PINCTRL_SUNXI
> > >  
> > >  config PINCTRL_SUN9I_A80
> > > diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
> > > index eed65058e667..cdb3d712389c 100644
> > > --- a/drivers/power/Kconfig
> > > +++ b/drivers/power/Kconfig
> > > @@ -75,7 +75,7 @@ config AXP152_POWER
> > >  
> > >  config AXP209_POWER
> > >  	bool "axp209 pmic support"
> > > -	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3S
> > > +	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3
> > >  	select AXP_PMIC_BUS
> > >  	select CMD_POWEROFF
> > >  	---help---  
> >   
> 


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v2 03/11] sunxi: Disable secure SRAM on sun8i platforms missing it
  2025-08-05 17:48 [PATCH v2 00/11] Various V3/S3/V3s fixes and improvements Paul Kocialkowski
  2025-08-05 17:48 ` [PATCH v2 01/11] sunxi: Kconfig: Fix default order for V3s DRAM clock Paul Kocialkowski
  2025-08-05 17:48 ` [PATCH v2 02/11] sunxi: Split V3 and V3s support with a common option Paul Kocialkowski
@ 2025-08-05 17:48 ` Paul Kocialkowski
  2025-08-05 17:48 ` [PATCH v2 04/11] power: axp: Add default voltages for V3/S3 Paul Kocialkowski
                   ` (7 subsequent siblings)
  10 siblings, 0 replies; 19+ messages in thread
From: Paul Kocialkowski @ 2025-08-05 17:48 UTC (permalink / raw)
  To: u-boot
  Cc: Tom Rini, Jagan Teki, Andre Przywara, Chen-Yu Tsai, Icenowy Zheng,
	Paul Kocialkowski

From: Paul Kocialkowski <contact@paulk.fr>

While most sun8i platforms have secure SRAM available, some do not.
This is the case for the R40/V40 (based on sun7i) and V3/V3s.

Add the exceptions to the Kconfig default and clean up its align.
Update affected defconfigs to reflect the new default.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 arch/arm/cpu/armv7/Kconfig          | 6 ++++--
 configs/Bananapi_M2_Ultra_defconfig | 1 -
 configs/LicheePi_Zero_defconfig     | 1 -
 configs/bananapi_m2_berry_defconfig | 1 -
 configs/pinecube_defconfig          | 1 -
 5 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index ab86d642eeeb..769e5e1a4a53 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -29,8 +29,10 @@ config ARMV7_BOOT_SEC_DEFAULT
 
 config HAS_ARMV7_SECURE_BASE
 	bool "Enable support for a ahardware secure memory area"
-	default y if ARCH_LS1021A || ARCH_MX7 || ARCH_MX7ULP || ARCH_STM32MP \
-			|| MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || TEGRA124
+	default y if ARCH_LS1021A || ARCH_MX7 || ARCH_MX7ULP || \
+		     ARCH_STM32MP || MACH_SUN6I || MACH_SUN7I || \
+		     (MACH_SUN8I && !MACH_SUN8I_R40 && !MACH_SUN8I_V3_V3S) || \
+		     TEGRA124
 
 config ARMV7_SECURE_BASE
 	hex "Base address for secure mode memory"
diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig
index b1195afea20c..97570fa7b47b 100644
--- a/configs/Bananapi_M2_Ultra_defconfig
+++ b/configs/Bananapi_M2_Ultra_defconfig
@@ -5,7 +5,6 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN8I_R40=y
 CONFIG_DRAM_CLK=576
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-# CONFIG_HAS_ARMV7_SECURE_BASE is not set
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig
index b2cf0a018c7f..299deb0195a2 100644
--- a/configs/LicheePi_Zero_defconfig
+++ b/configs/LicheePi_Zero_defconfig
@@ -3,5 +3,4 @@ CONFIG_ARCH_SUNXI=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero"
 CONFIG_SPL=y
 CONFIG_MACH_SUN8I_V3S=y
-# CONFIG_HAS_ARMV7_SECURE_BASE is not set
 CONFIG_NO_NET=y
diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig
index 94d29a4743e1..6bbdcdd7e7eb 100644
--- a/configs/bananapi_m2_berry_defconfig
+++ b/configs/bananapi_m2_berry_defconfig
@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-v40-bananapi-m2-berry"
 CONFIG_SPL=y
 CONFIG_MACH_SUN8I_R40=y
 CONFIG_DRAM_CLK=576
-# CONFIG_HAS_ARMV7_SECURE_BASE is not set
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig
index 088dd6f8630a..7c68fff2ea22 100644
--- a/configs/pinecube_defconfig
+++ b/configs/pinecube_defconfig
@@ -6,7 +6,6 @@ CONFIG_MACH_SUN8I_V3=y
 CONFIG_DRAM_CLK=504
 CONFIG_DRAM_ODT_EN=y
 CONFIG_I2C0_ENABLE=y
-# CONFIG_HAS_ARMV7_SECURE_BASE is not set
 CONFIG_SPL_I2C=y
 CONFIG_NO_NET=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
-- 
2.49.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v2 04/11] power: axp: Add default voltages for V3/S3
  2025-08-05 17:48 [PATCH v2 00/11] Various V3/S3/V3s fixes and improvements Paul Kocialkowski
                   ` (2 preceding siblings ...)
  2025-08-05 17:48 ` [PATCH v2 03/11] sunxi: Disable secure SRAM on sun8i platforms missing it Paul Kocialkowski
@ 2025-08-05 17:48 ` Paul Kocialkowski
  2025-08-05 17:48 ` [PATCH v2 05/11] sunxi: Switch V3/V3s device-tree source to OF_UPSTREAM Paul Kocialkowski
                   ` (6 subsequent siblings)
  10 siblings, 0 replies; 19+ messages in thread
From: Paul Kocialkowski @ 2025-08-05 17:48 UTC (permalink / raw)
  To: u-boot
  Cc: Tom Rini, Jagan Teki, Andre Przywara, Chen-Yu Tsai, Icenowy Zheng,
	Paul Kocialkowski

From: Paul Kocialkowski <contact@paulk.fr>

The default voltages used by V3/S3 boards differs from the usual AXP209
default that are used on older chips.

Correct the default voltages based on the Allwinner reference design
schematics, which match boards found in the wild such as the Pinecube.
Update the affected config.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 configs/pinecube_defconfig | 2 --
 drivers/power/Kconfig      | 8 ++++++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig
index 7c68fff2ea22..ac3e7fbb4317 100644
--- a/configs/pinecube_defconfig
+++ b/configs/pinecube_defconfig
@@ -15,7 +15,5 @@ CONFIG_SYS_I2C_SPEED=400000
 CONFIG_MTD=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_AXP209_POWER=y
-CONFIG_AXP_DCDC2_VOLT=1250
-CONFIG_AXP_DCDC3_VOLT=3300
 CONFIG_CONS_INDEX=3
 CONFIG_SPI=y
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index cdb3d712389c..fd143ec5ad75 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -176,10 +176,11 @@ config AXP_DCDC2_VOLT
 	int "axp pmic dcdc2 voltage"
 	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP313_POWER || AXP717_POWER || AXP803_POWER
 	default 900 if AXP818_POWER
-	default 1400 if AXP152_POWER || AXP209_POWER
+	default 1400 if AXP152_POWER || (AXP209_POWER && !MACH_SUN8I_V3)
 	default 1000 if AXP313_POWER
 	default 1000 if AXP717_POWER
 	default 1000 if AXP803_POWER
+	default 1250 if MACH_SUN8I_V3
 	default 1200 if MACH_SUN6I
 	default 1100 if MACH_SUN8I
 	default 0 if MACH_SUN9I
@@ -192,6 +193,7 @@ config AXP_DCDC2_VOLT
 	On A80 boards dcdc2 powers the GPU and can be left off.
 	On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V.
 	On R40 boards dcdc2 is VDD-CPU and should be 1.1V
+	On V3/S3 boards dcdc2 is VDD-CPU/VDD-SYS and should be 1.25V.
 	On boards using the AXP313 or AXP717 it's often VDD-CPU.
 
 config AXP_DCDC3_VOLT
@@ -199,9 +201,10 @@ config AXP_DCDC3_VOLT
 	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP313_POWER || AXP717_POWER
 	default 900 if AXP809_POWER || AXP818_POWER
 	default 1500 if AXP152_POWER
-	default 1250 if AXP209_POWER
+	default 1250 if (AXP209_POWER && !MACH_SUN8I_V3)
 	default 1100 if AXP313_POWER
 	default 1100 if MACH_SUN8I_R40
+	default 3300 if MACH_SUN8I_V3
 	default 1200 if MACH_SUN6I || MACH_SUN8I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to
@@ -213,6 +216,7 @@ config AXP_DCDC3_VOLT
 	On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V.
 	On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V.
 	On R40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V.
+	On V3/S3 boards dcdc3 is VCC-IO and should be 3.3V.
 	On boards using the AXP313 or AXP717 it's often VDD-DRAM and should
 	be 1.1V for LPDDR4.
 
-- 
2.49.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v2 05/11] sunxi: Switch V3/V3s device-tree source to OF_UPSTREAM
  2025-08-05 17:48 [PATCH v2 00/11] Various V3/S3/V3s fixes and improvements Paul Kocialkowski
                   ` (3 preceding siblings ...)
  2025-08-05 17:48 ` [PATCH v2 04/11] power: axp: Add default voltages for V3/S3 Paul Kocialkowski
@ 2025-08-05 17:48 ` Paul Kocialkowski
  2025-08-05 17:48 ` [PATCH v2 06/11] sunxi: Add support for I2C1 on PB pins for the V3/V3s Paul Kocialkowski
                   ` (5 subsequent siblings)
  10 siblings, 0 replies; 19+ messages in thread
From: Paul Kocialkowski @ 2025-08-05 17:48 UTC (permalink / raw)
  To: u-boot
  Cc: Tom Rini, Jagan Teki, Andre Przywara, Chen-Yu Tsai, Icenowy Zheng,
	Paul Kocialkowski

From: Paul Kocialkowski <contact@paulk.fr>

There is nothing special for u-boot in the V3/V3s device-tree files,
they are just copies of the upstream ones.

Remove the copies and switch to OF_UPSTREAM for supported boards.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 arch/arm/dts/Makefile                         |   5 -
 arch/arm/dts/sun8i-s3-elimo-impetus.dtsi      |  44 --
 arch/arm/dts/sun8i-s3-elimo-initium.dts       |  29 -
 arch/arm/dts/sun8i-s3-lichee-zero-plus.dts    |  53 --
 arch/arm/dts/sun8i-s3-pinecube.dts            | 228 ------
 arch/arm/dts/sun8i-v3-sl631-imx179.dts        |  12 -
 arch/arm/dts/sun8i-v3-sl631.dtsi              | 138 ----
 arch/arm/dts/sun8i-v3.dtsi                    |  63 --
 arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts   | 276 --------
 arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts | 105 ---
 arch/arm/dts/sun8i-v3s-licheepi-zero.dts      | 101 ---
 arch/arm/dts/sun8i-v3s.dtsi                   | 656 ------------------
 arch/arm/mach-sunxi/Kconfig                   |   1 +
 configs/LicheePi_Zero_defconfig               |   2 +-
 configs/pinecube_defconfig                    |   2 +-
 15 files changed, 3 insertions(+), 1712 deletions(-)
 delete mode 100644 arch/arm/dts/sun8i-s3-elimo-impetus.dtsi
 delete mode 100644 arch/arm/dts/sun8i-s3-elimo-initium.dts
 delete mode 100644 arch/arm/dts/sun8i-s3-lichee-zero-plus.dts
 delete mode 100644 arch/arm/dts/sun8i-s3-pinecube.dts
 delete mode 100644 arch/arm/dts/sun8i-v3-sl631-imx179.dts
 delete mode 100644 arch/arm/dts/sun8i-v3-sl631.dtsi
 delete mode 100644 arch/arm/dts/sun8i-v3.dtsi
 delete mode 100644 arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts
 delete mode 100644 arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
 delete mode 100644 arch/arm/dts/sun8i-v3s-licheepi-zero.dts
 delete mode 100644 arch/arm/dts/sun8i-v3s.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3d93679058c8..d0d25aac1b25 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -646,11 +646,6 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
 	sun8i-r40-oka40i-c.dtb \
 	sun8i-t3-cqa3t-bv3.dtb \
 	sun8i-v40-bananapi-m2-berry.dtb
-dtb-$(CONFIG_MACH_SUN8I_V3_V3S) += \
-	sun8i-s3-elimo-initium.dtb \
-	sun8i-s3-pinecube.dtb \
-	sun8i-v3-sl631-imx179.dtb \
-	sun8i-v3s-licheepi-zero.dtb
 dtb-$(CONFIG_MACH_SUN8I_R528) += \
 	sun8i-t113s-mangopi-mq-r-t113.dtb
 dtb-$(CONFIG_MACH_SUN50I_H5) += \
diff --git a/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi b/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi
deleted file mode 100644
index 052b010a5607..000000000000
--- a/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi
+++ /dev/null
@@ -1,44 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2020 Matteo Scordino <matteo@elimo.io>
- */
-
-/dts-v1/;
-#include "sun8i-v3.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-/ {
-	model = "Elimo Impetus SoM";
-	compatible = "elimo,impetus", "sochip,s3", "allwinner,sun8i-v3";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-};
-
-&mmc0 {
-	broken-cd;
-	bus-width = <4>;
-	vmmc-supply = <&reg_vcc3v3>;
-	status = "okay";
-};
-
-&uart0 {
-	pinctrl-0 = <&uart0_pb_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&usb_otg {
-	dr_mode = "otg";
-	status = "okay";
-};
-
-&usbphy {
-	usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/sun8i-s3-elimo-initium.dts b/arch/arm/dts/sun8i-s3-elimo-initium.dts
deleted file mode 100644
index 039677c2cc65..000000000000
--- a/arch/arm/dts/sun8i-s3-elimo-initium.dts
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2020 Matteo Scordino <matteo@elimo.io>
- */
-
-/dts-v1/;
-#include "sun8i-s3-elimo-impetus.dtsi"
-
-/ {
-	model = "Elimo Initium";
-	compatible = "elimo,initium", "elimo,impetus", "sochip,s3",
-		     "allwinner,sun8i-v3";
-
-	aliases {
-		serial1 = &uart1;
-	};
-};
-
-&uart1 {
-	pinctrl-0 = <&uart1_pg_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&emac {
-	phy-handle = <&int_mii_phy>;
-	phy-mode = "mii";
-	status = "okay";
-};
diff --git a/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts
deleted file mode 100644
index d18192d51d1b..000000000000
--- a/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
- */
-
-/dts-v1/;
-#include "sun8i-v3.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	model = "Sipeed Lichee Zero Plus";
-	compatible = "sipeed,lichee-zero-plus", "sochip,s3",
-		     "allwinner,sun8i-v3";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	reg_vcc3v3: vcc3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc3v3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-};
-
-&mmc0 {
-	broken-cd;
-	bus-width = <4>;
-	vmmc-supply = <&reg_vcc3v3>;
-	status = "okay";
-};
-
-&uart0 {
-	pinctrl-0 = <&uart0_pb_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&usb_otg {
-	dr_mode = "peripheral";
-	status = "okay";
-};
-
-&usbphy {
-	usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/sun8i-s3-pinecube.dts b/arch/arm/dts/sun8i-s3-pinecube.dts
deleted file mode 100644
index e0d4404b5957..000000000000
--- a/arch/arm/dts/sun8i-s3-pinecube.dts
+++ /dev/null
@@ -1,228 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR X11)
-/*
- * Copyright 2019 Icenowy Zheng <icenowy@aosc.io>
- */
-
-/dts-v1/;
-#include "sun8i-v3.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "PineCube IP Camera";
-	compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3";
-
-	aliases {
-		serial0 = &uart2;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led1 {
-			label = "pine64:ir:led1";
-			gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */
-		};
-
-		led2 {
-			label = "pine64:ir:led2";
-			gpios = <&pio 1 12 GPIO_ACTIVE_LOW>; /* PB12 */
-		};
-	};
-
-	reg_vcc5v0: vcc5v0 {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	reg_vcc_wifi: vcc-wifi {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc-wifi";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 WIFI-EN */
-		vin-supply = <&reg_dcdc3>;
-		startup-delay-us = <200000>;
-	};
-
-	wifi_pwrseq: pwrseq {
-		compatible = "mmc-pwrseq-simple";
-		reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */
-		post-power-on-delay-ms = <200>;
-	};
-};
-
-&csi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&csi1_8bit_pins>;
-	status = "okay";
-
-	port {
-		csi1_ep: endpoint {
-			remote-endpoint = <&ov5640_ep>;
-			bus-width = <8>;
-			hsync-active = <1>; /* Active high */
-			vsync-active = <0>; /* Active low */
-			data-active = <1>;  /* Active high */
-			pclk-sample = <1>;  /* Rising */
-		};
-	};
-};
-
-&emac {
-	phy-handle = <&int_mii_phy>;
-	phy-mode = "mii";
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-
-	axp209: pmic@34 {
-		reg = <0x34>;
-		interrupt-parent = <&nmi_intc>;
-		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-	};
-};
-
-&i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pe_pins>;
-	status = "okay";
-
-	ov5640: camera@3c {
-		compatible = "ovti,ov5640";
-		reg = <0x3c>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&csi1_mclk_pin>;
-		clocks = <&ccu CLK_CSI1_MCLK>;
-		clock-names = "xclk";
-
-		AVDD-supply = <&reg_ldo3>;
-		DOVDD-supply = <&reg_ldo3>;
-		DVDD-supply = <&reg_ldo4>;
-		reset-gpios = <&pio 4 23 GPIO_ACTIVE_LOW>; /* PE23 */
-		powerdown-gpios = <&pio 4 24 GPIO_ACTIVE_HIGH>; /* PE24 */
-
-		port {
-			ov5640_ep: endpoint {
-				remote-endpoint = <&csi1_ep>;
-				bus-width = <8>;
-				hsync-active = <1>; /* Active high */
-				vsync-active = <0>; /* Active low */
-				data-active = <1>;  /* Active high */
-				pclk-sample = <1>;  /* Rising */
-			};
-		};
-	};
-};
-
-&lradc {
-	vref-supply = <&reg_ldo2>;
-	status = "okay";
-
-	button-200 {
-		label = "Setup";
-		linux,code = <KEY_SETUP>;
-		channel = <0>;
-		voltage = <190000>;
-	};
-};
-
-&mmc0 {
-	vmmc-supply = <&reg_dcdc3>;
-	bus-width = <4>;
-	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
-	status = "okay";
-};
-
-&mmc1 {
-	vmmc-supply = <&reg_vcc_wifi>;
-	vqmmc-supply = <&reg_dcdc3>;
-	mmc-pwrseq = <&wifi_pwrseq>;
-	bus-width = <4>;
-	non-removable;
-	status = "okay";
-};
-
-&pio {
-	vcc-pd-supply = <&reg_dcdc3>;
-	vcc-pe-supply = <&reg_ldo3>;
-};
-
-#include "axp209.dtsi"
-
-&ac_power_supply {
-	status = "okay";
-};
-
-&reg_dcdc2 {
-	regulator-always-on;
-	regulator-min-microvolt = <1250000>;
-	regulator-max-microvolt = <1250000>;
-	regulator-name = "vdd-sys-cpu-ephy";
-};
-
-&reg_dcdc3 {
-	regulator-always-on;
-	regulator-min-microvolt = <3300000>;
-	regulator-max-microvolt = <3300000>;
-	regulator-name = "vcc-3v3";
-};
-
-&reg_ldo1 {
-	regulator-name = "vdd-rtc";
-};
-
-&reg_ldo2 {
-	regulator-always-on;
-	regulator-min-microvolt = <3000000>;
-	regulator-max-microvolt = <3000000>;
-	regulator-name = "avcc";
-};
-
-&reg_ldo3 {
-	regulator-min-microvolt = <2800000>;
-	regulator-max-microvolt = <2800000>;
-	regulator-name = "avdd-dovdd-2v8-csi";
-	regulator-soft-start;
-	regulator-ramp-delay = <1600>;
-};
-
-&reg_ldo4 {
-	regulator-min-microvolt = <1800000>;
-	regulator-max-microvolt = <1800000>;
-	regulator-name = "dvdd-1v8-csi";
-};
-
-&spi0 {
-	status = "okay";
-
-	flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "winbond,w25q128", "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <40000000>;
-	};
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&usb_otg {
-	dr_mode = "host";
-	status = "okay";
-};
-
-&usbphy {
-	usb0_vbus-supply = <&reg_vcc5v0>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/sun8i-v3-sl631-imx179.dts b/arch/arm/dts/sun8i-v3-sl631-imx179.dts
deleted file mode 100644
index 117aeece4e55..000000000000
--- a/arch/arm/dts/sun8i-v3-sl631-imx179.dts
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR X11)
-/*
- * Copyright 2020 Paul Kocialkowski <contact@paulk.fr>
- */
-
-#include "sun8i-v3-sl631.dtsi"
-
-/ {
-	model = "SL631 Action Camera with IMX179";
-	compatible = "allwinner,sl631-imx179", "allwinner,sl631",
-		     "allwinner,sun8i-v3";
-};
diff --git a/arch/arm/dts/sun8i-v3-sl631.dtsi b/arch/arm/dts/sun8i-v3-sl631.dtsi
deleted file mode 100644
index 6f93f8c49f84..000000000000
--- a/arch/arm/dts/sun8i-v3-sl631.dtsi
+++ /dev/null
@@ -1,138 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR X11)
-/*
- * Copyright 2020 Paul Kocialkowski <contact@paulk.fr>
- */
-
-/dts-v1/;
-
-#include "sun8i-v3.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "SL631 Action Camera";
-	compatible = "allwinner,sl631", "allwinner,sun8i-v3";
-
-	aliases {
-		serial0 = &uart1;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-};
-
-&i2c0 {
-	status = "okay";
-
-	axp209: pmic@34 {
-		reg = <0x34>;
-		interrupt-parent = <&nmi_intc>;
-		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-	};
-};
-
-&i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pb_pins>;
-	status = "okay";
-};
-
-&lradc {
-	vref-supply = <&reg_ldo2>;
-	status = "okay";
-
-	button-174 {
-		label = "Down";
-		linux,code = <KEY_DOWN>;
-		channel = <0>;
-		voltage = <174603>;
-	};
-
-	button-384 {
-		label = "Up";
-		linux,code = <KEY_UP>;
-		channel = <0>;
-		voltage = <384126>;
-	};
-
-	button-593 {
-		label = "OK";
-		linux,code = <KEY_OK>;
-		channel = <0>;
-		voltage = <593650>;
-	};
-};
-
-&mmc0 {
-	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-	bus-width = <4>;
-	vmmc-supply = <&reg_dcdc3>;
-	status = "okay";
-};
-
-&pio {
-	vcc-pd-supply = <&reg_dcdc3>;
-	vcc-pe-supply = <&reg_dcdc3>;
-};
-
-#include "axp209.dtsi"
-
-&ac_power_supply {
-	status = "okay";
-};
-
-&battery_power_supply {
-	status = "okay";
-};
-
-&reg_dcdc2 {
-	regulator-always-on;
-	regulator-min-microvolt = <1250000>;
-	regulator-max-microvolt = <1250000>;
-	regulator-name = "vdd-sys-cpu";
-};
-
-&reg_dcdc3 {
-	regulator-always-on;
-	regulator-min-microvolt = <3300000>;
-	regulator-max-microvolt = <3300000>;
-	regulator-name = "vdd-3v3";
-};
-
-&reg_ldo1 {
-	regulator-name = "vdd-rtc";
-};
-
-&reg_ldo2 {
-	regulator-always-on;
-	regulator-min-microvolt = <3000000>;
-	regulator-max-microvolt = <3000000>;
-	regulator-name = "avcc";
-};
-
-&spi0 {
-	status = "okay";
-
-	flash@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <50000000>;
-	};
-};
-
-&uart1 {
-	pinctrl-0 = <&uart1_pg_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&usb_otg {
-	dr_mode = "peripheral";
-	status = "okay";
-};
-
-&usbphy {
-	status = "okay";
-};
diff --git a/arch/arm/dts/sun8i-v3.dtsi b/arch/arm/dts/sun8i-v3.dtsi
deleted file mode 100644
index 186c30cbe6ee..000000000000
--- a/arch/arm/dts/sun8i-v3.dtsi
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
- * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
- */
-
-#include "sun8i-v3s.dtsi"
-
-/ {
-	soc {
-		i2s0: i2s@1c22000 {
-			#sound-dai-cells = <0>;
-			compatible = "allwinner,sun8i-v3-i2s",
-				     "allwinner,sun8i-h3-i2s";
-			reg = <0x01c22000 0x400>;
-			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
-			clock-names = "apb", "mod";
-			dmas = <&dma 3>, <&dma 3>;
-			dma-names = "rx", "tx";
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2s0_pins>;
-			resets = <&ccu RST_BUS_I2S0>;
-			status = "disabled";
-		};
-	};
-};
-
-&ccu {
-	compatible = "allwinner,sun8i-v3-ccu";
-};
-
-&codec_analog {
-	compatible = "allwinner,sun8i-v3-codec-analog",
-		     "allwinner,sun8i-h3-codec-analog";
-};
-
-&emac {
-	/delete-property/ phy-handle;
-	/delete-property/ phy-mode;
-};
-
-&mdio_mux {
-	external_mdio: mdio@2 {
-		reg = <2>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-};
-
-&pio {
-	compatible = "allwinner,sun8i-v3-pinctrl";
-
-	i2s0_pins: i2s0-pins {
-		pins = "PG10", "PG11", "PG12", "PG13";
-		function = "i2s";
-	};
-
-	uart1_pg_pins: uart1-pg-pins {
-		pins = "PG6", "PG7";
-		function = "uart1";
-	};
-};
diff --git a/arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts b/arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts
deleted file mode 100644
index f34dfdf1566d..000000000000
--- a/arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts
+++ /dev/null
@@ -1,276 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-/dts-v1/;
-#include <dt-bindings/input/linux-event-codes.h>
-#include "sun8i-v3s.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-/ {
-	model = "Anbernic RG Nano";
-	compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s";
-
-	aliases {
-		rtc0 = &pcf8563;
-		rtc1 = &rtc;
-		serial0 = &uart0;
-	};
-
-	backlight: backlight {
-		compatible = "pwm-backlight";
-		brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>;
-		default-brightness-level = <11>;
-		power-supply = <&reg_vcc5v0>;
-		pwms = <&pwm 0 40000 1>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	gpio_keys: gpio-keys {
-		compatible = "gpio-keys";
-
-		button-a {
-			gpios = <&gpio_expander 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "BTN-A";
-			linux,code = <BTN_EAST>;
-		};
-
-		button-b {
-			gpios = <&gpio_expander 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "BTN-B";
-			linux,code = <BTN_SOUTH>;
-		};
-
-		button-down {
-			gpios = <&gpio_expander 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "DPAD-DOWN";
-			linux,code = <BTN_DPAD_DOWN>;
-		};
-
-		button-left {
-			gpios = <&gpio_expander 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "DPAD-LEFT";
-			linux,code = <BTN_DPAD_LEFT>;
-		};
-
-		button-right {
-			gpios = <&gpio_expander 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "DPAD-RIGHT";
-			linux,code = <BTN_DPAD_RIGHT>;
-		};
-
-		button-se {
-			gpios = <&gpio_expander 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "BTN-SELECT";
-			linux,code = <BTN_SELECT>;
-		};
-
-		button-st {
-			gpios = <&gpio_expander 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "BTN-START";
-			linux,code = <BTN_START>;
-		};
-
-		button-tl {
-			gpios = <&gpio_expander 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "BTN-L";
-			linux,code = <BTN_TL>;
-		};
-
-		button-tr {
-			gpios = <&gpio_expander 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "BTN-R";
-			linux,code = <BTN_TR>;
-		};
-
-		button-up {
-			gpios = <&gpio_expander 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "DPAD-UP";
-			linux,code = <BTN_DPAD_UP>;
-		};
-
-		button-x {
-			gpios = <&gpio_expander 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "BTN-X";
-			linux,code = <BTN_NORTH>;
-		};
-
-		button-y {
-			gpios = <&gpio_expander 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			label = "BTN-Y";
-			linux,code = <BTN_WEST>;
-		};
-	};
-};
-
-&codec {
-	allwinner,audio-routing = "Speaker", "HP",
-				  "MIC1", "Mic",
-				  "Mic", "HBIAS";
-	allwinner,pa-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PF6 */
-	status = "okay";
-};
-
-&ehci {
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-
-	gpio_expander: gpio@20 {
-		compatible = "nxp,pcal6416";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		#interrupt-cells = <2>;
-		interrupt-controller;
-		interrupt-parent = <&pio>;
-		interrupts = <1 3 IRQ_TYPE_EDGE_BOTH>; /* PB3/EINT3 */
-		vcc-supply = <&reg_vcc3v3>;
-	};
-
-	axp209: pmic@34 {
-		reg = <0x34>;
-		interrupt-parent = <&pio>;
-		interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5/EINT5 */
-	};
-
-	pcf8563: rtc@51 {
-		compatible = "nxp,pcf8563";
-		reg = <0x51>;
-	};
-};
-
-#include "axp209.dtsi"
-
-&battery_power_supply {
-	status = "okay";
-};
-
-&mmc0 {
-	broken-cd;
-	bus-width = <4>;
-	disable-wp;
-	vmmc-supply = <&reg_vcc3v3>;
-	vqmmc-supply = <&reg_vcc3v3>;
-	status = "okay";
-};
-
-&ohci {
-	status = "okay";
-};
-
-&pio {
-	vcc-pb-supply = <&reg_vcc3v3>;
-	vcc-pc-supply = <&reg_vcc3v3>;
-	vcc-pf-supply = <&reg_vcc3v3>;
-	vcc-pg-supply = <&reg_vcc3v3>;
-
-	spi0_no_miso_pins: spi0-no-miso-pins {
-		pins = "PC1", "PC2", "PC3";
-		function = "spi0";
-	};
-};
-
-&pwm {
-	pinctrl-0 = <&pwm0_pin>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-/* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */
-&reg_dcdc2 {
-	regulator-always-on;
-	regulator-max-microvolt = <1250000>;
-	regulator-min-microvolt = <1250000>;
-	regulator-name = "vdd-cpu";
-};
-
-/* DCDC3 wired into every 3.3v input that isn't the RTC. */
-&reg_dcdc3 {
-	regulator-always-on;
-	regulator-max-microvolt = <3300000>;
-	regulator-min-microvolt = <3300000>;
-	regulator-name = "vcc-io";
-};
-
-/* LDO1 wired into RTC, voltage is hard-wired at 3.3v. */
-&reg_ldo1 {
-	regulator-always-on;
-	regulator-name = "vcc-rtc";
-};
-
-/* LDO2 wired into VCC-PLL and audio codec. */
-&reg_ldo2 {
-	regulator-always-on;
-	regulator-max-microvolt = <3000000>;
-	regulator-min-microvolt = <3000000>;
-	regulator-name = "vcc-pll";
-};
-
-/* LDO3, LDO4, and LDO5 unused. */
-&reg_ldo3 {
-	status = "disabled";
-};
-
-&reg_ldo4 {
-	status = "disabled";
-};
-
-/* RTC uses internal oscillator */
-&rtc {
-	/delete-property/ clocks;
-};
-
-&spi0 {
-	pinctrl-0 = <&spi0_no_miso_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	display@0 {
-		compatible = "saef,sftc154b", "panel-mipi-dbi-spi";
-		reg = <0>;
-		backlight = <&backlight>;
-		dc-gpios = <&pio 2 0 GPIO_ACTIVE_HIGH>; /* PC0 */
-		reset-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */
-		spi-max-frequency = <100000000>;
-
-		height-mm = <39>;
-		width-mm = <39>;
-
-		/* Set hb-porch to compensate for non-visible area */
-		panel-timing {
-			hactive = <240>;
-			vactive = <240>;
-			hback-porch = <80>;
-			vback-porch = <0>;
-			clock-frequency = <0>;
-			hfront-porch = <0>;
-			hsync-len = <0>;
-			vfront-porch = <0>;
-			vsync-len = <0>;
-		};
-	};
-};
-
-&uart0 {
-	pinctrl-0 = <&uart0_pb_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&usb_otg {
-	dr_mode = "otg";
-	status = "okay";
-};
-
-&usb_power_supply {
-	status = "okay";
-};
-
-&usbphy {
-	usb0_id_det-gpios = <&pio 6 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG5 */
-	status = "okay";
-};
diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
deleted file mode 100644
index 752ad05c8f83..000000000000
--- a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "sun8i-v3s-licheepi-zero.dts"
-
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "Lichee Pi Zero with Dock";
-	compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero",
-		     "allwinner,sun8i-v3s";
-
-	aliases {
-		ethernet0 = &emac;
-	};
-
-	leds {
-		/* The LEDs use PG0~2 pins, which conflict with MMC1 */
-		status = "disabled";
-	};
-};
-
-&emac {
-	allwinner,leds-active-low;
-	status = "okay";
-};
-
-&lradc {
-	vref-supply = <&reg_vcc3v0>;
-	status = "okay";
-
-	button-200 {
-		label = "Volume Up";
-		linux,code = <KEY_VOLUMEUP>;
-		channel = <0>;
-		voltage = <200000>;
-	};
-
-	button-400 {
-		label = "Volume Down";
-		linux,code = <KEY_VOLUMEDOWN>;
-		channel = <0>;
-		voltage = <400000>;
-	};
-
-	button-600 {
-		label = "Select";
-		linux,code = <KEY_SELECT>;
-		channel = <0>;
-		voltage = <600000>;
-	};
-
-	button-800 {
-		label = "Start";
-		linux,code = <KEY_OK>;
-		channel = <0>;
-		voltage = <800000>;
-	};
-};
-
-&mmc1 {
-	broken-cd;
-	bus-width = <4>;
-	vmmc-supply = <&reg_vcc3v3>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
deleted file mode 100644
index 2e4587d26ce5..000000000000
--- a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "sun8i-v3s.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-/ {
-	model = "Lichee Pi Zero";
-	compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s";
-
-	aliases {
-		serial0 = &uart0;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		blue_led {
-			label = "licheepi:blue:usr";
-			gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
-		};
-
-		green_led {
-			label = "licheepi:green:usr";
-			gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
-			default-state = "on";
-		};
-
-		red_led {
-			label = "licheepi:red:usr";
-			gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */
-		};
-	};
-};
-
-&mmc0 {
-	broken-cd;
-	bus-width = <4>;
-	vmmc-supply = <&reg_vcc3v3>;
-	status = "okay";
-};
-
-&uart0 {
-	pinctrl-0 = <&uart0_pb_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&usb_otg {
-	dr_mode = "otg";
-	status = "okay";
-};
-
-&usbphy {
-	usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi
deleted file mode 100644
index 9e13c2aa8911..000000000000
--- a/arch/arm/dts/sun8i-v3s.dtsi
+++ /dev/null
@@ -1,656 +0,0 @@
-/*
- * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
- * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/sun6i-rtc.h>
-#include <dt-bindings/clock/sun8i-v3s-ccu.h>
-#include <dt-bindings/reset/sun8i-v3s-ccu.h>
-#include <dt-bindings/clock/sun8i-de2.h>
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-	interrupt-parent = <&gic>;
-
-	chosen {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		framebuffer-lcd {
-			compatible = "allwinner,simple-framebuffer",
-				     "simple-framebuffer";
-			allwinner,pipeline = "mixer0-lcd0";
-			clocks = <&display_clocks CLK_MIXER0>,
-				 <&ccu CLK_TCON0>;
-			status = "disabled";
-		};
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@0 {
-			compatible = "arm,cortex-a7";
-			device_type = "cpu";
-			reg = <0>;
-			clocks = <&ccu CLK_CPU>;
-		};
-	};
-
-	de: display-engine {
-		compatible = "allwinner,sun8i-v3s-display-engine";
-		allwinner,pipelines = <&mixer0>;
-		status = "disabled";
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	clocks {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		osc24M: osc24M-clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <24000000>;
-			clock-accuracy = <50000>;
-			clock-output-names = "osc24M";
-		};
-
-		osc32k: osc32k-clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <32768>;
-			clock-accuracy = <50000>;
-			clock-output-names = "ext-osc32k";
-		};
-	};
-
-	soc {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		display_clocks: clock@1000000 {
-			compatible = "allwinner,sun8i-v3s-de2-clk";
-			reg = <0x01000000 0x10000>;
-			clocks = <&ccu CLK_BUS_DE>,
-				 <&ccu CLK_DE>;
-			clock-names = "bus",
-				      "mod";
-			resets = <&ccu RST_BUS_DE>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
-
-		mixer0: mixer@1100000 {
-			compatible = "allwinner,sun8i-v3s-de2-mixer";
-			reg = <0x01100000 0x100000>;
-			clocks = <&display_clocks 0>,
-				 <&display_clocks 6>;
-			clock-names = "bus",
-				      "mod";
-			resets = <&display_clocks 0>;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				mixer0_out: port@1 {
-					reg = <1>;
-
-					mixer0_out_tcon0: endpoint {
-						remote-endpoint = <&tcon0_in_mixer0>;
-					};
-				};
-			};
-		};
-
-		syscon: system-control@1c00000 {
-			compatible = "allwinner,sun8i-v3s-system-control",
-				     "allwinner,sun8i-h3-system-control";
-			reg = <0x01c00000 0xd0>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-		};
-
-		nmi_intc: interrupt-controller@1c000d0 {
-			compatible = "allwinner,sun8i-v3s-nmi",
-				     "allwinner,sun9i-a80-nmi";
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			reg = <0x01c000d0 0x0c>;
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		dma: dma-controller@1c02000 {
-			compatible = "allwinner,sun8i-v3s-dma";
-			reg = <0x01c02000 0x1000>;
-			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_DMA>;
-			resets = <&ccu RST_BUS_DMA>;
-			#dma-cells = <1>;
-		};
-
-		tcon0: lcd-controller@1c0c000 {
-			compatible = "allwinner,sun8i-v3s-tcon";
-			reg = <0x01c0c000 0x1000>;
-			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_TCON0>,
-				 <&ccu CLK_TCON0>;
-			clock-names = "ahb",
-				      "tcon-ch0";
-			clock-output-names = "tcon-data-clock";
-			#clock-cells = <0>;
-			resets = <&ccu RST_BUS_TCON0>;
-			reset-names = "lcd";
-			status = "disabled";
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				tcon0_in: port@0 {
-					reg = <0>;
-
-					tcon0_in_mixer0: endpoint {
-						remote-endpoint = <&mixer0_out_tcon0>;
-					};
-				};
-
-				tcon0_out: port@1 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <1>;
-				};
-			};
-		};
-
-
-		mmc0: mmc@1c0f000 {
-			compatible = "allwinner,sun7i-a20-mmc";
-			reg = <0x01c0f000 0x1000>;
-			clocks = <&ccu CLK_BUS_MMC0>,
-				 <&ccu CLK_MMC0>,
-				 <&ccu CLK_MMC0_OUTPUT>,
-				 <&ccu CLK_MMC0_SAMPLE>;
-			clock-names = "ahb",
-				      "mmc",
-				      "output",
-				      "sample";
-			resets = <&ccu RST_BUS_MMC0>;
-			reset-names = "ahb";
-			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&mmc0_pins>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		mmc1: mmc@1c10000 {
-			compatible = "allwinner,sun7i-a20-mmc";
-			reg = <0x01c10000 0x1000>;
-			clocks = <&ccu CLK_BUS_MMC1>,
-				 <&ccu CLK_MMC1>,
-				 <&ccu CLK_MMC1_OUTPUT>,
-				 <&ccu CLK_MMC1_SAMPLE>;
-			clock-names = "ahb",
-				      "mmc",
-				      "output",
-				      "sample";
-			resets = <&ccu RST_BUS_MMC1>;
-			reset-names = "ahb";
-			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&mmc1_pins>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		mmc2: mmc@1c11000 {
-			compatible = "allwinner,sun7i-a20-mmc";
-			reg = <0x01c11000 0x1000>;
-			clocks = <&ccu CLK_BUS_MMC2>,
-				 <&ccu CLK_MMC2>,
-				 <&ccu CLK_MMC2_OUTPUT>,
-				 <&ccu CLK_MMC2_SAMPLE>;
-			clock-names = "ahb",
-				      "mmc",
-				      "output",
-				      "sample";
-			resets = <&ccu RST_BUS_MMC2>;
-			reset-names = "ahb";
-			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		crypto@1c15000 {
-			compatible = "allwinner,sun8i-v3s-crypto",
-				     "allwinner,sun8i-a33-crypto";
-			reg = <0x01c15000 0x1000>;
-			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
-			clock-names = "ahb", "mod";
-			dmas = <&dma 16>, <&dma 16>;
-			dma-names = "rx", "tx";
-			resets = <&ccu RST_BUS_CE>;
-			reset-names = "ahb";
-		};
-
-		usb_otg: usb@1c19000 {
-			compatible = "allwinner,sun8i-h3-musb";
-			reg = <0x01c19000 0x0400>;
-			clocks = <&ccu CLK_BUS_OTG>;
-			resets = <&ccu RST_BUS_OTG>;
-			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "mc";
-			phys = <&usbphy 0>;
-			phy-names = "usb";
-			extcon = <&usbphy 0>;
-			status = "disabled";
-		};
-
-		usbphy: phy@1c19400 {
-			compatible = "allwinner,sun8i-v3s-usb-phy";
-			reg = <0x01c19400 0x2c>,
-			      <0x01c1a800 0x4>;
-			reg-names = "phy_ctrl",
-				    "pmu0";
-			clocks = <&ccu CLK_USB_PHY0>;
-			clock-names = "usb0_phy";
-			resets = <&ccu RST_USB_PHY0>;
-			reset-names = "usb0_reset";
-			status = "disabled";
-			#phy-cells = <1>;
-		};
-
-		ehci: usb@1c1a000 {
-			compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci";
-			reg = <0x01c1a000 0x100>;
-			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
-			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
-			phys = <&usbphy 0>;
-			phy-names = "usb";
-			status = "disabled";
-		};
-
-		ohci: usb@1c1a400 {
-			compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci";
-			reg = <0x01c1a400 0x100>;
-			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
-				 <&ccu CLK_USB_OHCI0>;
-			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
-			phys = <&usbphy 0>;
-			phy-names = "usb";
-			status = "disabled";
-		};
-
-		ccu: clock@1c20000 {
-			compatible = "allwinner,sun8i-v3s-ccu";
-			reg = <0x01c20000 0x400>;
-			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
-			clock-names = "hosc", "losc";
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
-
-		rtc: rtc@1c20400 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun8i-v3-rtc";
-			reg = <0x01c20400 0x54>;
-			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc32k>;
-			clock-output-names = "osc32k", "osc32k-out";
-		};
-
-		pio: pinctrl@1c20800 {
-			compatible = "allwinner,sun8i-v3s-pinctrl";
-			reg = <0x01c20800 0x400>;
-			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
-				 <&rtc CLK_OSC32K>;
-			clock-names = "apb", "hosc", "losc";
-			gpio-controller;
-			#gpio-cells = <3>;
-			interrupt-controller;
-			#interrupt-cells = <3>;
-
-			/omit-if-no-ref/
-			csi0_mclk_pin: csi0-mclk-pin {
-				pins = "PE20";
-				function = "csi_mipi";
-			};
-
-			/omit-if-no-ref/
-			csi1_8bit_pins: csi1-8bit-pins {
-				pins = "PE0", "PE2", "PE3", "PE8", "PE9",
-				       "PE10", "PE11", "PE12", "PE13", "PE14",
-				       "PE15";
-				function = "csi";
-			};
-
-			/omit-if-no-ref/
-			csi1_mclk_pin: csi1-mclk-pin {
-				pins = "PE1";
-				function = "csi";
-			};
-
-			i2c0_pins: i2c0-pins {
-				pins = "PB6", "PB7";
-				function = "i2c0";
-			};
-
-			/omit-if-no-ref/
-			i2c1_pb_pins: i2c1-pb-pins {
-				pins = "PB8", "PB9";
-				function = "i2c1";
-			};
-
-			/omit-if-no-ref/
-			i2c1_pe_pins: i2c1-pe-pins {
-				pins = "PE21", "PE22";
-				function = "i2c1";
-			};
-
-			uart0_pb_pins: uart0-pb-pins {
-				pins = "PB8", "PB9";
-				function = "uart0";
-			};
-
-			uart2_pins: uart2-pins {
-				pins = "PB0", "PB1";
-				function = "uart2";
-			};
-
-			mmc0_pins: mmc0-pins {
-				pins = "PF0", "PF1", "PF2", "PF3",
-				       "PF4", "PF5";
-				function = "mmc0";
-				drive-strength = <30>;
-				bias-pull-up;
-			};
-
-			mmc1_pins: mmc1-pins {
-				pins = "PG0", "PG1", "PG2", "PG3",
-				       "PG4", "PG5";
-				function = "mmc1";
-				drive-strength = <30>;
-				bias-pull-up;
-			};
-
-			/omit-if-no-ref/
-			pwm0_pin: pwm0-pin {
-				pins = "PB4";
-				function = "pwm0";
-			};
-
-			/omit-if-no-ref/
-			pwm1_pin: pwm1-pin {
-				pins = "PB5";
-				function = "pwm1";
-			};
-
-			spi0_pins: spi0-pins {
-				pins = "PC0", "PC1", "PC2", "PC3";
-				function = "spi0";
-			};
-		};
-
-		timer@1c20c00 {
-			compatible = "allwinner,sun8i-v3s-timer";
-			reg = <0x01c20c00 0xa0>;
-			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc24M>;
-		};
-
-		wdt0: watchdog@1c20ca0 {
-			compatible = "allwinner,sun6i-a31-wdt";
-			reg = <0x01c20ca0 0x20>;
-			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&osc24M>;
-		};
-
-		pwm: pwm@1c21400 {
-			compatible = "allwinner,sun8i-v3s-pwm",
-				     "allwinner,sun7i-a20-pwm";
-			reg = <0x01c21400 0xc>;
-			clocks = <&osc24M>;
-			#pwm-cells = <3>;
-			status = "disabled";
-		};
-
-		lradc: lradc@1c22800 {
-			compatible = "allwinner,sun4i-a10-lradc-keys";
-			reg = <0x01c22800 0x400>;
-			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		codec: codec@1c22c00 {
-			#sound-dai-cells = <0>;
-			compatible = "allwinner,sun8i-v3s-codec";
-			reg = <0x01c22c00 0x400>;
-			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
-			clock-names = "apb", "codec";
-			resets = <&ccu RST_BUS_CODEC>;
-			dmas = <&dma 15>, <&dma 15>;
-			dma-names = "rx", "tx";
-			allwinner,codec-analog-controls = <&codec_analog>;
-			status = "disabled";
-		};
-
-		codec_analog: codec-analog@1c23000 {
-			compatible = "allwinner,sun8i-v3s-codec-analog";
-			reg = <0x01c23000 0x4>;
-		};
-
-		uart0: serial@1c28000 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x01c28000 0x400>;
-			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clocks = <&ccu CLK_BUS_UART0>;
-			dmas = <&dma 6>, <&dma 6>;
-			dma-names = "tx", "rx";
-			resets = <&ccu RST_BUS_UART0>;
-			status = "disabled";
-		};
-
-		uart1: serial@1c28400 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x01c28400 0x400>;
-			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clocks = <&ccu CLK_BUS_UART1>;
-			dmas = <&dma 7>, <&dma 7>;
-			dma-names = "tx", "rx";
-			resets = <&ccu RST_BUS_UART1>;
-			status = "disabled";
-		};
-
-		uart2: serial@1c28800 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x01c28800 0x400>;
-			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clocks = <&ccu CLK_BUS_UART2>;
-			dmas = <&dma 8>, <&dma 8>;
-			dma-names = "tx", "rx";
-			resets = <&ccu RST_BUS_UART2>;
-			pinctrl-0 = <&uart2_pins>;
-			pinctrl-names = "default";
-			status = "disabled";
-		};
-
-		i2c0: i2c@1c2ac00 {
-			compatible = "allwinner,sun6i-a31-i2c";
-			reg = <0x01c2ac00 0x400>;
-			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_I2C0>;
-			resets = <&ccu RST_BUS_I2C0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c0_pins>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		i2c1: i2c@1c2b000 {
-			compatible = "allwinner,sun6i-a31-i2c";
-			reg = <0x01c2b000 0x400>;
-			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_I2C1>;
-			resets = <&ccu RST_BUS_I2C1>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		emac: ethernet@1c30000 {
-			compatible = "allwinner,sun8i-v3s-emac";
-			syscon = <&syscon>;
-			reg = <0x01c30000 0x10000>;
-			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "macirq";
-			resets = <&ccu RST_BUS_EMAC>;
-			reset-names = "stmmaceth";
-			clocks = <&ccu CLK_BUS_EMAC>;
-			clock-names = "stmmaceth";
-			phy-handle = <&int_mii_phy>;
-			phy-mode = "mii";
-			status = "disabled";
-
-			mdio: mdio {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "snps,dwmac-mdio";
-			};
-
-			mdio_mux: mdio-mux {
-				compatible = "allwinner,sun8i-h3-mdio-mux";
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				mdio-parent-bus = <&mdio>;
-				/* Only one MDIO is usable at the time */
-				internal_mdio: mdio@1 {
-					compatible = "allwinner,sun8i-h3-mdio-internal";
-					reg = <1>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					int_mii_phy: ethernet-phy@1 {
-						compatible = "ethernet-phy-ieee802.3-c22";
-						reg = <1>;
-						clocks = <&ccu CLK_BUS_EPHY>;
-						resets = <&ccu RST_BUS_EPHY>;
-					};
-				};
-			};
-		};
-
-		spi0: spi@1c68000 {
-			compatible = "allwinner,sun8i-h3-spi";
-			reg = <0x01c68000 0x1000>;
-			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
-			clock-names = "ahb", "mod";
-			dmas = <&dma 23>, <&dma 23>;
-			dma-names = "rx", "tx";
-			pinctrl-names = "default";
-			pinctrl-0 = <&spi0_pins>;
-			resets = <&ccu RST_BUS_SPI0>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		gic: interrupt-controller@1c81000 {
-			compatible = "arm,gic-400";
-			reg = <0x01c81000 0x1000>,
-			      <0x01c82000 0x2000>,
-			      <0x01c84000 0x2000>,
-			      <0x01c86000 0x2000>;
-			interrupt-controller;
-			#interrupt-cells = <3>;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-		};
-
-		csi1: camera@1cb4000 {
-			compatible = "allwinner,sun8i-v3s-csi";
-			reg = <0x01cb4000 0x3000>;
-			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_CSI>,
-				 <&ccu CLK_CSI1_SCLK>,
-				 <&ccu CLK_DRAM_CSI>;
-			clock-names = "bus", "mod", "ram";
-			resets = <&ccu RST_BUS_CSI>;
-			status = "disabled";
-		};
-	};
-};
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index f0faa9f80a23..12981adbd042 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -572,6 +572,7 @@ config MACH_SUN8I_V3_V3S
 	select SUNXI_DRAM_DW_16BIT
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+	imply OF_UPSTREAM
 
 config RESERVE_ALLWINNER_BOOT0_HEADER
 	bool "reserve space for Allwinner boot0 header"
diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig
index 299deb0195a2..de695b362b44 100644
--- a/configs/LicheePi_Zero_defconfig
+++ b/configs/LicheePi_Zero_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero"
+CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun8i-v3s-licheepi-zero"
 CONFIG_SPL=y
 CONFIG_MACH_SUN8I_V3S=y
 CONFIG_NO_NET=y
diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig
index ac3e7fbb4317..2b2fb88c4933 100644
--- a/configs/pinecube_defconfig
+++ b/configs/pinecube_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube"
+CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun8i-s3-pinecube"
 CONFIG_SPL=y
 CONFIG_MACH_SUN8I_V3=y
 CONFIG_DRAM_CLK=504
-- 
2.49.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v2 06/11] sunxi: Add support for I2C1 on PB pins for the V3/V3s
  2025-08-05 17:48 [PATCH v2 00/11] Various V3/S3/V3s fixes and improvements Paul Kocialkowski
                   ` (4 preceding siblings ...)
  2025-08-05 17:48 ` [PATCH v2 05/11] sunxi: Switch V3/V3s device-tree source to OF_UPSTREAM Paul Kocialkowski
@ 2025-08-05 17:48 ` Paul Kocialkowski
  2025-08-06  4:30   ` Heiko Schocher
  2025-08-07  8:32   ` Paul Kocialkowski
  2025-08-05 17:48 ` [PATCH v2 07/11] sunxi: Add support for UART1 on PG pins for the V3/S3 Paul Kocialkowski
                   ` (4 subsequent siblings)
  10 siblings, 2 replies; 19+ messages in thread
From: Paul Kocialkowski @ 2025-08-05 17:48 UTC (permalink / raw)
  To: u-boot
  Cc: Tom Rini, Jagan Teki, Andre Przywara, Chen-Yu Tsai, Icenowy Zheng,
	Paul Kocialkowski

From: Paul Kocialkowski <contact@paulk.fr>

Both the V3 and V3s support I2C1 on PB pins, which is often used to
connect an AXP209 PMIC on V3 boards.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 board/sunxi/board.c  | 4 ++++
 include/sunxi_gpio.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 6520636ffab5..72aa86cd752d 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -98,6 +98,10 @@ void i2c_init_board(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
 	clock_twi_onoff(1, 1);
+#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_TWI1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_TWI1);
+	clock_twi_onoff(1, 1);
 #elif defined(CONFIG_MACH_SUN8I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
index 12b54c8dda4d..e166b9758f44 100644
--- a/include/sunxi_gpio.h
+++ b/include/sunxi_gpio.h
@@ -110,6 +110,7 @@ enum sunxi_gpio_number {
 #define SUN4I_GPB_TWI1		2
 #define SUN5I_GPB_TWI1		2
 #define SUN8I_V3S_GPB_TWI0	2
+#define SUN8I_V3S_GPB_TWI1	2
 #define SUN4I_GPB_UART0		2
 #define SUN5I_GPB_UART0		2
 #define SUN8I_GPB_UART2		2
-- 
2.49.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 06/11] sunxi: Add support for I2C1 on PB pins for the V3/V3s
  2025-08-05 17:48 ` [PATCH v2 06/11] sunxi: Add support for I2C1 on PB pins for the V3/V3s Paul Kocialkowski
@ 2025-08-06  4:30   ` Heiko Schocher
  2025-08-07  8:32   ` Paul Kocialkowski
  1 sibling, 0 replies; 19+ messages in thread
From: Heiko Schocher @ 2025-08-06  4:30 UTC (permalink / raw)
  To: Paul Kocialkowski, u-boot
  Cc: Tom Rini, Jagan Teki, Andre Przywara, Chen-Yu Tsai, Icenowy Zheng,
	Paul Kocialkowski

Hello Paul,

On 05.08.25 19:48, Paul Kocialkowski wrote:
> From: Paul Kocialkowski <contact@paulk.fr>
> 
> Both the V3 and V3s support I2C1 on PB pins, which is often used to
> connect an AXP209 PMIC on V3 boards.
> 
> Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
> ---
>   board/sunxi/board.c  | 4 ++++
>   include/sunxi_gpio.h | 1 +
>   2 files changed, 5 insertions(+)

Reviewed-by: Heiko Schocher <hs@denx.de>

bye,
Heiko
-- 
-- 
DENX Software Engineering GmbH, Managing Director: Johanna Denk, Tabea Lutz
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52   Fax: +49-8142-66989-80   Email: hs@denx.de

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 06/11] sunxi: Add support for I2C1 on PB pins for the V3/V3s
  2025-08-05 17:48 ` [PATCH v2 06/11] sunxi: Add support for I2C1 on PB pins for the V3/V3s Paul Kocialkowski
  2025-08-06  4:30   ` Heiko Schocher
@ 2025-08-07  8:32   ` Paul Kocialkowski
  1 sibling, 0 replies; 19+ messages in thread
From: Paul Kocialkowski @ 2025-08-07  8:32 UTC (permalink / raw)
  To: u-boot
  Cc: Tom Rini, Jagan Teki, Andre Przywara, Chen-Yu Tsai, Icenowy Zheng,
	Paul Kocialkowski

[-- Attachment #1: Type: text/plain, Size: 2053 bytes --]

Hi,

Le Tue 05 Aug 25, 19:48, Paul Kocialkowski a écrit :
> From: Paul Kocialkowski <contact@paulk.fr>
> 
> Both the V3 and V3s support I2C1 on PB pins, which is often used to
> connect an AXP209 PMIC on V3 boards.

Actually this appears to be wrong. I had this patch around for a while but
I was mistaken about the AXP209, which is typically connected to I2C0, not
I2C1.

So I think this patch could be dropped, it won't be directly useful for our
supported boards anyway.

All the best,

Paul

> Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
> ---
>  board/sunxi/board.c  | 4 ++++
>  include/sunxi_gpio.h | 1 +
>  2 files changed, 5 insertions(+)
> 
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index 6520636ffab5..72aa86cd752d 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -98,6 +98,10 @@ void i2c_init_board(void)
>  	sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
>  	sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
>  	clock_twi_onoff(1, 1);
> +#elif defined(CONFIG_MACH_SUN8I_V3_V3S)
> +	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_TWI1);
> +	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_TWI1);
> +	clock_twi_onoff(1, 1);
>  #elif defined(CONFIG_MACH_SUN8I)
>  	sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
>  	sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
> diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
> index 12b54c8dda4d..e166b9758f44 100644
> --- a/include/sunxi_gpio.h
> +++ b/include/sunxi_gpio.h
> @@ -110,6 +110,7 @@ enum sunxi_gpio_number {
>  #define SUN4I_GPB_TWI1		2
>  #define SUN5I_GPB_TWI1		2
>  #define SUN8I_V3S_GPB_TWI0	2
> +#define SUN8I_V3S_GPB_TWI1	2
>  #define SUN4I_GPB_UART0		2
>  #define SUN5I_GPB_UART0		2
>  #define SUN8I_GPB_UART2		2
> -- 
> 2.49.0
> 

-- 
Paul Kocialkowski,

Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/

Expert in multimedia, graphics and embedded hardware support with Linux.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v2 07/11] sunxi: Add support for UART1 on PG pins for the V3/S3
  2025-08-05 17:48 [PATCH v2 00/11] Various V3/S3/V3s fixes and improvements Paul Kocialkowski
                   ` (5 preceding siblings ...)
  2025-08-05 17:48 ` [PATCH v2 06/11] sunxi: Add support for I2C1 on PB pins for the V3/V3s Paul Kocialkowski
@ 2025-08-05 17:48 ` Paul Kocialkowski
       [not found]   ` <20250806012121.27bdcfeb@minigeek.lan>
  2025-08-05 17:48 ` [PATCH v2 08/11] sunxi: pinecube: Enable EMAC and network support Paul Kocialkowski
                   ` (3 subsequent siblings)
  10 siblings, 1 reply; 19+ messages in thread
From: Paul Kocialkowski @ 2025-08-05 17:48 UTC (permalink / raw)
  To: u-boot
  Cc: Tom Rini, Jagan Teki, Andre Przywara, Chen-Yu Tsai, Icenowy Zheng,
	Paul Kocialkowski

From: Paul Kocialkowski <contact@paulk.fr>

The V3/S3 has extra pins for UART1 on PG pins, which are not present
on the V3s. Add support for them and make them the default UART1 pins
on the V3. Note that PE pins are also available for UART1 but almost
never used since they also provide the CSI I2C lines.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 arch/arm/mach-sunxi/board.c | 4 ++++
 include/sunxi_gpio.h        | 1 +
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index a1a02b0fae50..d1b27b062d6d 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -169,6 +169,10 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
 	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I_V3)
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_V3_GPG_UART1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_V3_GPG_UART1);
+	sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3)
 	sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2);
 	sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2);
diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
index e166b9758f44..7d142f65ea8a 100644
--- a/include/sunxi_gpio.h
+++ b/include/sunxi_gpio.h
@@ -141,6 +141,7 @@ enum sunxi_gpio_number {
 #define SUN8I_GPG_SDC1		2
 #define SUN8I_GPG_UART1		2
 #define SUN5I_GPG_UART1		4
+#define SUN8I_V3_GPG_UART1	2
 
 #define SUN6I_GPH_PWM		2
 #define SUN8I_GPH_PWM		2
-- 
2.49.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

[parent not found: <20250806012121.27bdcfeb@minigeek.lan>]

* Re: [PATCH v2 07/11] sunxi: Add support for UART1 on PG pins for the V3/S3
       [not found]   ` <20250806012121.27bdcfeb@minigeek.lan>
@ 2025-08-06 17:18     ` Paul Kocialkowski
  0 siblings, 0 replies; 19+ messages in thread
From: Paul Kocialkowski @ 2025-08-06 17:18 UTC (permalink / raw)
  To: Andre Przywara
  Cc: u-boot, Tom Rini, Jagan Teki, Chen-Yu Tsai, Icenowy Zheng,
	Paul Kocialkowski

[-- Attachment #1: Type: text/plain, Size: 3554 bytes --]

Hi,

Thansk for the review!

Le Wed 06 Aug 25, 01:21, Andre Przywara a écrit :
> On Tue,  5 Aug 2025 19:48:23 +0200
> Paul Kocialkowski <paulk@sys-base.io> wrote:
> 
> Hi,
> 
> > From: Paul Kocialkowski <contact@paulk.fr>
> > 
> > The V3/S3 has extra pins for UART1 on PG pins, which are not present
> > on the V3s. Add support for them and make them the default UART1 pins
> > on the V3. Note that PE pins are also available for UART1 but almost
> > never used since they also provide the CSI I2C lines.
> 
> So the patch itself looks alright, but what is this actually used for?
> This pinmux setting here is really just for the SPL to setup the debug
> UART. Is there any board where UART1 is the supposed debug UART?
> Because if not, we just don't need that here, and if yes, I'd love to
> see the respective defconfig file ;-)

This is the default on the V3 reference design, which uses UART1 on PG pins for
debug and I've seen it in use in all V3/S3 devices I could see, including:
- Olimex S3-OLinuXino
- SL631 action camera
- iT-X3 action camera

The pinecube is the odd one out using UART2 instead. For V3s devices it's a bit
messy and the reference design uses UART2 over PB pins, but the only device we
support (Lichee Pi Zero) uses UART0 on PB pins instead (muxed with TWI1).

So you're right, it's not currently useful for devices in the tree, but I
assumed it could be useful in the future. I also just noticed that there is
already a fallback for sun8i which will direct UART1 to PG pins, on the same
pins that I'm using. So this patch is definitely not necessary then!

I have some work in progress to add support for the devices above, but never
sat down to finish them. I'll definitely submit them eventually!

All the best,

Paul

> Cheers,
> Andre
> 
> > 
> > Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
> > ---
> >  arch/arm/mach-sunxi/board.c | 4 ++++
> >  include/sunxi_gpio.h        | 1 +
> >  2 files changed, 5 insertions(+)
> > 
> > diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> > index a1a02b0fae50..d1b27b062d6d 100644
> > --- a/arch/arm/mach-sunxi/board.c
> > +++ b/arch/arm/mach-sunxi/board.c
> > @@ -169,6 +169,10 @@ static int gpio_init(void)
> >  	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
> >  	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
> >  	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
> > +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I_V3)
> > +	sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_V3_GPG_UART1);
> > +	sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_V3_GPG_UART1);
> > +	sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
> >  #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3)
> >  	sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2);
> >  	sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2);
> > diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
> > index e166b9758f44..7d142f65ea8a 100644
> > --- a/include/sunxi_gpio.h
> > +++ b/include/sunxi_gpio.h
> > @@ -141,6 +141,7 @@ enum sunxi_gpio_number {
> >  #define SUN8I_GPG_SDC1		2
> >  #define SUN8I_GPG_UART1		2
> >  #define SUN5I_GPG_UART1		4
> > +#define SUN8I_V3_GPG_UART1	2
> >  
> >  #define SUN6I_GPH_PWM		2
> >  #define SUN8I_GPH_PWM		2
> 

-- 
Paul Kocialkowski,

Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/

Expert in multimedia, graphics and embedded hardware support with Linux.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v2 08/11] sunxi: pinecube: Enable EMAC and network support
  2025-08-05 17:48 [PATCH v2 00/11] Various V3/S3/V3s fixes and improvements Paul Kocialkowski
                   ` (6 preceding siblings ...)
  2025-08-05 17:48 ` [PATCH v2 07/11] sunxi: Add support for UART1 on PG pins for the V3/S3 Paul Kocialkowski
@ 2025-08-05 17:48 ` Paul Kocialkowski
  2025-08-05 17:48 ` [PATCH v2 09/11] sunxi: Add support for the Lichee Pi Zero with Dock Paul Kocialkowski
                   ` (2 subsequent siblings)
  10 siblings, 0 replies; 19+ messages in thread
From: Paul Kocialkowski @ 2025-08-05 17:48 UTC (permalink / raw)
  To: u-boot
  Cc: Tom Rini, Jagan Teki, Andre Przywara, Chen-Yu Tsai, Icenowy Zheng,
	Paul Kocialkowski

From: Paul Kocialkowski <contact@paulk.fr>

The pinecube has an ethernet connector which uses the EMAC and internal
PHY of the chip. Enable it in the config.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 configs/pinecube_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig
index 2b2fb88c4933..b4aaca346653 100644
--- a/configs/pinecube_defconfig
+++ b/configs/pinecube_defconfig
@@ -7,13 +7,13 @@ CONFIG_DRAM_CLK=504
 CONFIG_DRAM_ODT_EN=y
 CONFIG_I2C0_ENABLE=y
 CONFIG_SPL_I2C=y
-CONFIG_NO_NET=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_MVTWSI=y
 CONFIG_SYS_I2C_SLAVE=0x7f
 CONFIG_SYS_I2C_SPEED=400000
 CONFIG_MTD=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SUN8I_EMAC=y
 CONFIG_AXP209_POWER=y
 CONFIG_CONS_INDEX=3
 CONFIG_SPI=y
-- 
2.49.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v2 09/11] sunxi: Add support for the Lichee Pi Zero with Dock
  2025-08-05 17:48 [PATCH v2 00/11] Various V3/S3/V3s fixes and improvements Paul Kocialkowski
                   ` (7 preceding siblings ...)
  2025-08-05 17:48 ` [PATCH v2 08/11] sunxi: pinecube: Enable EMAC and network support Paul Kocialkowski
@ 2025-08-05 17:48 ` Paul Kocialkowski
  2025-08-05 17:48 ` [PATCH v2 10/11] net: sun8i-emac: Remove internal PHY config default value Paul Kocialkowski
  2025-08-05 17:48 ` [PATCH v2 11/11] net: sun8i-emac: Add support for active-low leds with internal PHY Paul Kocialkowski
  10 siblings, 0 replies; 19+ messages in thread
From: Paul Kocialkowski @ 2025-08-05 17:48 UTC (permalink / raw)
  To: u-boot
  Cc: Tom Rini, Jagan Teki, Andre Przywara, Chen-Yu Tsai, Icenowy Zheng,
	Paul Kocialkowski

From: Paul Kocialkowski <contact@paulk.fr>

This adds a U-Boot config and device-tree build for the Lichee Pi Zero
with Dock. Compared to the Lichee Pi Zero, it has an ethernet port
(with internal PHY) so the EMAC driver and network support are enabled.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 configs/LicheePi_Zero_Dock_defconfig | 6 ++++++
 1 file changed, 6 insertions(+)
 create mode 100644 configs/LicheePi_Zero_Dock_defconfig

diff --git a/configs/LicheePi_Zero_Dock_defconfig b/configs/LicheePi_Zero_Dock_defconfig
new file mode 100644
index 000000000000..0ae53c0c067f
--- /dev/null
+++ b/configs/LicheePi_Zero_Dock_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun8i-v3s-licheepi-zero-dock"
+CONFIG_SPL=y
+CONFIG_MACH_SUN8I_V3S=y
+CONFIG_SUN8I_EMAC=y
-- 
2.49.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v2 10/11] net: sun8i-emac: Remove internal PHY config default value
  2025-08-05 17:48 [PATCH v2 00/11] Various V3/S3/V3s fixes and improvements Paul Kocialkowski
                   ` (8 preceding siblings ...)
  2025-08-05 17:48 ` [PATCH v2 09/11] sunxi: Add support for the Lichee Pi Zero with Dock Paul Kocialkowski
@ 2025-08-05 17:48 ` Paul Kocialkowski
  2025-08-05 17:48 ` [PATCH v2 11/11] net: sun8i-emac: Add support for active-low leds with internal PHY Paul Kocialkowski
  10 siblings, 0 replies; 19+ messages in thread
From: Paul Kocialkowski @ 2025-08-05 17:48 UTC (permalink / raw)
  To: u-boot
  Cc: Tom Rini, Jagan Teki, Andre Przywara, Chen-Yu Tsai, Icenowy Zheng,
	Paul Kocialkowski

From: Paul Kocialkowski <contact@paulk.fr>

We know about all the relevant fields in the syscon register so there
is no reason to read it first and modify it.

Build the register from scratch instead, with all relevant fields set.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 drivers/net/sun8i_emac.c | 32 +++++++++-----------------------
 1 file changed, 9 insertions(+), 23 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 8433e7db2654..6e95392b379b 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -57,10 +57,9 @@
 #define TX_TOTAL_BUFSIZE	(CFG_ETH_BUFSIZE * CFG_TX_DESCR_NUM)
 #define RX_TOTAL_BUFSIZE	(CFG_ETH_BUFSIZE * CFG_RX_DESCR_NUM)
 
-#define H3_EPHY_DEFAULT_VALUE	0x58000
-#define H3_EPHY_DEFAULT_MASK	GENMASK(31, 15)
 #define H3_EPHY_ADDR_SHIFT	20
 #define REG_PHY_ADDR_MASK	GENMASK(4, 0)
+#define H3_EPHY_CLK_SEL		BIT(18) /* 1: 24MHz, 0: 25MHz */
 #define H3_EPHY_LED_POL		BIT(17)	/* 1: active low, 0: active high */
 #define H3_EPHY_SHUTDOWN	BIT(16)	/* 1: shutdown, 0: power up */
 #define H3_EPHY_SELECT		BIT(15) /* 1: internal PHY, 0: external PHY */
@@ -287,35 +286,22 @@ static void sun8i_adjust_link(struct emac_eth_dev *priv,
 	writel(v, priv->mac_reg + EMAC_CTL0);
 }
 
-static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
+static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
+				 struct emac_eth_dev *priv)
 {
+	u32 reg = 0;
+
 	if (priv->use_internal_phy) {
 		/* H3 based SoC's that has an Internal 100MBit PHY
 		 * needs to be configured and powered up before use
 		*/
-		reg &= ~H3_EPHY_DEFAULT_MASK;
-		reg |=  H3_EPHY_DEFAULT_VALUE;
 		reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
-		reg &= ~H3_EPHY_SHUTDOWN;
-		return reg | H3_EPHY_SELECT;
+		reg |= H3_EPHY_CLK_SEL;
+		reg |= H3_EPHY_SELECT;
+	} else {
+		reg |= H3_EPHY_SHUTDOWN;
 	}
 
-	/* This is to select External Gigabit PHY on those boards with
-	 * an internal PHY. Does not hurt on other SoCs. Linux does
-	 * it as well.
-	 */
-	return reg & ~H3_EPHY_SELECT;
-}
-
-static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
-				 struct emac_eth_dev *priv)
-{
-	u32 reg;
-
-	reg = readl(priv->sysctl_reg);
-
-	reg = sun8i_emac_set_syscon_ephy(priv, reg);
-
 	reg &= ~(SC_ETCS_MASK | SC_EPIT);
 	if (priv->variant->support_rmii)
 		reg &= ~SC_RMII_EN;
-- 
2.49.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v2 11/11] net: sun8i-emac: Add support for active-low leds with internal PHY
  2025-08-05 17:48 [PATCH v2 00/11] Various V3/S3/V3s fixes and improvements Paul Kocialkowski
                   ` (9 preceding siblings ...)
  2025-08-05 17:48 ` [PATCH v2 10/11] net: sun8i-emac: Remove internal PHY config default value Paul Kocialkowski
@ 2025-08-05 17:48 ` Paul Kocialkowski
  10 siblings, 0 replies; 19+ messages in thread
From: Paul Kocialkowski @ 2025-08-05 17:48 UTC (permalink / raw)
  To: u-boot
  Cc: Tom Rini, Jagan Teki, Andre Przywara, Chen-Yu Tsai, Icenowy Zheng,
	Paul Kocialkowski

From: Paul Kocialkowski <contact@paulk.fr>

A device-tree property is already defined to indicate that the internal
PHY should be used with active-low leds, which corresponds to a
specific bit in the dedicated syscon register.

Add support for setting this bit when the property is present.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 drivers/net/sun8i_emac.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 6e95392b379b..41c52f56d7a9 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -175,6 +175,7 @@ struct sun8i_eth_pdata {
 	u32 reset_delays[3];
 	int tx_delay_ps;
 	int rx_delay_ps;
+	bool leds_active_low;
 };
 
 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
@@ -298,6 +299,9 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
 		reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
 		reg |= H3_EPHY_CLK_SEL;
 		reg |= H3_EPHY_SELECT;
+
+		if (pdata->leds_active_low)
+			reg |= H3_EPHY_LED_POL;
 	} else {
 		reg |= H3_EPHY_SHUTDOWN;
 	}
@@ -845,6 +849,10 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
 		printf("%s: Invalid RX delay value %d\n", __func__,
 		       sun8i_pdata->rx_delay_ps);
 
+	sun8i_pdata->leds_active_low =
+		fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
+				"allwinner,leds-active-low");
+
 	if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
 			    "snps,reset-active-low"))
 		reset_flags |= GPIOD_ACTIVE_LOW;
-- 
2.49.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2025-10-21 14:02 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-08-05 17:48 [PATCH v2 00/11] Various V3/S3/V3s fixes and improvements Paul Kocialkowski
2025-08-05 17:48 ` [PATCH v2 01/11] sunxi: Kconfig: Fix default order for V3s DRAM clock Paul Kocialkowski
2025-08-05 17:48 ` [PATCH v2 02/11] sunxi: Split V3 and V3s support with a common option Paul Kocialkowski
2025-08-06  0:21   ` Andre Przywara
2025-08-06 17:24     ` Paul Kocialkowski
2025-08-08  3:48       ` Icenowy Zheng
2025-10-21 14:02       ` Andre Przywara
2025-08-05 17:48 ` [PATCH v2 03/11] sunxi: Disable secure SRAM on sun8i platforms missing it Paul Kocialkowski
2025-08-05 17:48 ` [PATCH v2 04/11] power: axp: Add default voltages for V3/S3 Paul Kocialkowski
2025-08-05 17:48 ` [PATCH v2 05/11] sunxi: Switch V3/V3s device-tree source to OF_UPSTREAM Paul Kocialkowski
2025-08-05 17:48 ` [PATCH v2 06/11] sunxi: Add support for I2C1 on PB pins for the V3/V3s Paul Kocialkowski
2025-08-06  4:30   ` Heiko Schocher
2025-08-07  8:32   ` Paul Kocialkowski
2025-08-05 17:48 ` [PATCH v2 07/11] sunxi: Add support for UART1 on PG pins for the V3/S3 Paul Kocialkowski
     [not found]   ` <20250806012121.27bdcfeb@minigeek.lan>
2025-08-06 17:18     ` Paul Kocialkowski
2025-08-05 17:48 ` [PATCH v2 08/11] sunxi: pinecube: Enable EMAC and network support Paul Kocialkowski
2025-08-05 17:48 ` [PATCH v2 09/11] sunxi: Add support for the Lichee Pi Zero with Dock Paul Kocialkowski
2025-08-05 17:48 ` [PATCH v2 10/11] net: sun8i-emac: Remove internal PHY config default value Paul Kocialkowski
2025-08-05 17:48 ` [PATCH v2 11/11] net: sun8i-emac: Add support for active-low leds with internal PHY Paul Kocialkowski

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.