* [PATCH] clk: thead: Correct parent for DPU pixel clocks [not found] <CGME20250809170205eucas1p2da20fc85d38c98195d2ce36422592bee@eucas1p2.samsung.com> @ 2025-08-09 17:02 ` Michal Wilczynski 0 siblings, 0 replies; 4+ messages in thread From: Michal Wilczynski @ 2025-08-09 17:02 UTC (permalink / raw) To: Drew Fustini, Guo Ren, Fu Wei, Michael Turquette, Stephen Boyd Cc: linux-riscv, linux-clk, linux-kernel, Icenowy Zheng, Michal Wilczynski The dpu0_pixelclk and dpu1_pixelclk gates were incorrectly parented to the video_pll_clk. According to the TH1520 TRM, the "dpu0_pixelclk" should be sourced from "DPU0 PLL DIV CLK". In this driver, "DPU0 PLL DIV CLK" corresponds to the `dpu0_clk` clock, which is a divider whose parent is the `dpu0_pll_clk`. This patch corrects the clock hierarchy by reparenting `dpu0_pixelclk` to `dpu0_clk`. By symmetry, `dpu1_pixelclk` is also reparented to its correct source, `dpu1_clk`. Fixes: 50d4b157fa96 ("clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC") Reported-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> --- drivers/clk/thead/clk-th1520-ap.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c index cf1bba58f641e9b053cdda5fa52640590c5fa215..dd6359441f7e8a2c9d4a00c640b07af606627cc4 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -767,6 +767,10 @@ static struct ccu_div dpu0_clk = { }, }; +static const struct clk_parent_data dpu0_clk_pd[] = { + { .hw = &dpu0_clk.common.hw } +}; + static struct ccu_div dpu1_clk = { .div = TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED), .common = { @@ -779,6 +783,10 @@ static struct ccu_div dpu1_clk = { }, }; +static const struct clk_parent_data dpu1_clk_pd[] = { + { .hw = &dpu1_clk.common.hw } +}; + static CLK_FIXED_FACTOR_HW(emmc_sdio_ref_clk, "emmc-sdio-ref", &video_pll_clk.common.hw, 4, 1, 0); @@ -855,9 +863,9 @@ static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_pd, static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk", video_pll_clk_pd, 0x0, BIT(4), 0); static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk", - video_pll_clk_pd, 0x0, BIT(5), 0); + dpu0_clk_pd, 0x0, BIT(5), 0); static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk", - video_pll_clk_pd, 0x0, BIT(6), 0); + dpu1_clk_pd, 0x0, BIT(6), 0); static CCU_GATE(CLK_DPU_HCLK, dpu_hclk, "dpu-hclk", video_pll_clk_pd, 0x0, BIT(7), 0); static CCU_GATE(CLK_DPU_ACLK, dpu_aclk, "dpu-aclk", video_pll_clk_pd, 0x0, --- base-commit: 561c80369df0733ba0574882a1635287b20f9de2 change-id: 20250809-fix_clocks_thead_aug_9-5cffff4d0c38 Best regards, -- Michal Wilczynski <m.wilczynski@samsung.com> ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] clk: thead: Correct parent for DPU pixel clocks @ 2025-08-09 17:02 ` Michal Wilczynski 0 siblings, 0 replies; 4+ messages in thread From: Michal Wilczynski @ 2025-08-09 17:02 UTC (permalink / raw) To: Drew Fustini, Guo Ren, Fu Wei, Michael Turquette, Stephen Boyd Cc: Michal Wilczynski, linux-riscv, linux-clk, linux-kernel The dpu0_pixelclk and dpu1_pixelclk gates were incorrectly parented to the video_pll_clk. According to the TH1520 TRM, the "dpu0_pixelclk" should be sourced from "DPU0 PLL DIV CLK". In this driver, "DPU0 PLL DIV CLK" corresponds to the `dpu0_clk` clock, which is a divider whose parent is the `dpu0_pll_clk`. This patch corrects the clock hierarchy by reparenting `dpu0_pixelclk` to `dpu0_clk`. By symmetry, `dpu1_pixelclk` is also reparented to its correct source, `dpu1_clk`. Fixes: 50d4b157fa96 ("clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC") Reported-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> --- drivers/clk/thead/clk-th1520-ap.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c index cf1bba58f641e9b053cdda5fa52640590c5fa215..dd6359441f7e8a2c9d4a00c640b07af606627cc4 100644 --- a/drivers/clk/thead/clk-th1520-ap.c +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -767,6 +767,10 @@ static struct ccu_div dpu0_clk = { }, }; +static const struct clk_parent_data dpu0_clk_pd[] = { + { .hw = &dpu0_clk.common.hw } +}; + static struct ccu_div dpu1_clk = { .div = TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED), .common = { @@ -779,6 +783,10 @@ static struct ccu_div dpu1_clk = { }, }; +static const struct clk_parent_data dpu1_clk_pd[] = { + { .hw = &dpu1_clk.common.hw } +}; + static CLK_FIXED_FACTOR_HW(emmc_sdio_ref_clk, "emmc-sdio-ref", &video_pll_clk.common.hw, 4, 1, 0); @@ -855,9 +863,9 @@ static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_pd, static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk", video_pll_clk_pd, 0x0, BIT(4), 0); static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk", - video_pll_clk_pd, 0x0, BIT(5), 0); + dpu0_clk_pd, 0x0, BIT(5), 0); static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk", - video_pll_clk_pd, 0x0, BIT(6), 0); + dpu1_clk_pd, 0x0, BIT(6), 0); static CCU_GATE(CLK_DPU_HCLK, dpu_hclk, "dpu-hclk", video_pll_clk_pd, 0x0, BIT(7), 0); static CCU_GATE(CLK_DPU_ACLK, dpu_aclk, "dpu-aclk", video_pll_clk_pd, 0x0, --- base-commit: 561c80369df0733ba0574882a1635287b20f9de2 change-id: 20250809-fix_clocks_thead_aug_9-5cffff4d0c38 Best regards, -- Michal Wilczynski <m.wilczynski@samsung.com> _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] clk: thead: Correct parent for DPU pixel clocks 2025-08-09 17:02 ` Michal Wilczynski @ 2025-08-12 5:03 ` Drew Fustini -1 siblings, 0 replies; 4+ messages in thread From: Drew Fustini @ 2025-08-12 5:03 UTC (permalink / raw) To: Michal Wilczynski Cc: Guo Ren, Fu Wei, Michael Turquette, Stephen Boyd, linux-riscv, linux-clk, linux-kernel, Icenowy Zheng On Sat, Aug 09, 2025 at 07:02:00PM +0200, Michal Wilczynski wrote: > The dpu0_pixelclk and dpu1_pixelclk gates were incorrectly parented to > the video_pll_clk. > > According to the TH1520 TRM, the "dpu0_pixelclk" should be sourced from > "DPU0 PLL DIV CLK". In this driver, "DPU0 PLL DIV CLK" corresponds to > the `dpu0_clk` clock, which is a divider whose parent is the > `dpu0_pll_clk`. > > This patch corrects the clock hierarchy by reparenting `dpu0_pixelclk` > to `dpu0_clk`. By symmetry, `dpu1_pixelclk` is also reparented to its > correct source, `dpu1_clk`. > > Fixes: 50d4b157fa96 ("clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC") > Reported-by: Icenowy Zheng <uwu@icenowy.me> > Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Reviewed-by: Drew Fustini <fustini@kernel.org> Thanks for the patch. I've been excited to see Icenowy and you working on the graphics functionality. -Drew ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] clk: thead: Correct parent for DPU pixel clocks @ 2025-08-12 5:03 ` Drew Fustini 0 siblings, 0 replies; 4+ messages in thread From: Drew Fustini @ 2025-08-12 5:03 UTC (permalink / raw) To: Michal Wilczynski Cc: Stephen Boyd, Michael Turquette, linux-kernel, Guo Ren, linux-riscv, linux-clk, Fu Wei On Sat, Aug 09, 2025 at 07:02:00PM +0200, Michal Wilczynski wrote: > The dpu0_pixelclk and dpu1_pixelclk gates were incorrectly parented to > the video_pll_clk. > > According to the TH1520 TRM, the "dpu0_pixelclk" should be sourced from > "DPU0 PLL DIV CLK". In this driver, "DPU0 PLL DIV CLK" corresponds to > the `dpu0_clk` clock, which is a divider whose parent is the > `dpu0_pll_clk`. > > This patch corrects the clock hierarchy by reparenting `dpu0_pixelclk` > to `dpu0_clk`. By symmetry, `dpu1_pixelclk` is also reparented to its > correct source, `dpu1_clk`. > > Fixes: 50d4b157fa96 ("clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC") > Reported-by: Icenowy Zheng <uwu@icenowy.me> > Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Reviewed-by: Drew Fustini <fustini@kernel.org> Thanks for the patch. I've been excited to see Icenowy and you working on the graphics functionality. -Drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 4+ messages in thread
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[not found] <CGME20250809170205eucas1p2da20fc85d38c98195d2ce36422592bee@eucas1p2.samsung.com>
2025-08-09 17:02 ` [PATCH] clk: thead: Correct parent for DPU pixel clocks Michal Wilczynski
2025-08-09 17:02 ` Michal Wilczynski
2025-08-12 5:03 ` Drew Fustini
2025-08-12 5:03 ` Drew Fustini
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