Re: [PATCH v2 0/2] clk: thead: th1520-ap: allow gate cascade and fix padctrl0

From: Drew Fustini <fustini@kernel.org>
To: Icenowy Zheng <uwu@icenowy.me>
Cc: Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Michal Wilczynski <m.wilczynski@samsung.com>,
	Han Gao <rabenda.cn@gmail.com>, Yao Zi <ziyao@disroot.org>,
	linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 0/2] clk: thead: th1520-ap: allow gate cascade and fix padctrl0
Date: Mon, 18 Aug 2025 15:10:04 -0700	[thread overview]
Message-ID: <aKOkvK2UHxLP0LNA@x1> (raw)
In-Reply-To: <20250816084445.2582692-1-uwu@icenowy.me>

On Sat, Aug 16, 2025 at 04:44:43PM +0800, Icenowy Zheng wrote:
> Current ccu_gate implementation does not easily allow gates to be clock
> parents because of the waste of struct clk_hw in struct ccu_gate;
> however it's found that the padctrl0 apb clock gate seems to be
> downstream of perisys-apb4-hclk, gating the latter w/o gating the former
> makes the padctrl0 registers inaccessible too.
> 
> Fix this by refactor ccu_gate code, mimicing what Yao Zi did on
> ccu_mux; and then assign perisys-apb4-hclk as parent of padctrl0 bus
> gate.
> 
> Icenowy Zheng (2):
>   clk: thead: th1520-ap: describe gate clocks with clk_gate
>   clk: thead: th1520-ap: fix parent of padctrl0 clock
> 
>  drivers/clk/thead/clk-th1520-ap.c | 386 +++++++++++++++---------------
>  1 file changed, 189 insertions(+), 197 deletions(-)
> 
> -- 
> 2.50.1

Thank you, I've applied this to thead-clk-for-next [1]:

9e99b992c887 clk: thead: th1520-ap: fix parent of padctrl0 clock
aaa75cbd5d4f clk: thead: th1520-ap: describe gate clocks with clk_gate

-Drew

[1] https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git/log/?h=thead-clk-for-next