Re: [PATCH net] net: stmmac: dwmac-rk: Ensure clk_phy doesn't contain invalid address

From: Yao Zi <ziyao@disroot.org>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>,
	Chaoyi Chen <chaoyi.chen@rock-chips.com>
Cc: Andrew Lunn <andrew+netdev@lunn.ch>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Jonas Karlman <jonas@kwiboo.se>,
	David Wu <david.wu@rock-chips.com>,
	netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org
Subject: Re: [PATCH net] net: stmmac: dwmac-rk: Ensure clk_phy doesn't contain invalid address
Date: Sat, 6 Sep 2025 05:36:44 +0000	[thread overview]
Message-ID: <aLvIbPfWWNa6TwNv@pie> (raw)
In-Reply-To: <aLly7lJ05xQjqCWn@shell.armlinux.org.uk>

On Thu, Sep 04, 2025 at 12:07:26PM +0100, Russell King (Oracle) wrote:
> On Thu, Sep 04, 2025 at 12:05:19PM +0100, Russell King (Oracle) wrote:
> > On Thu, Sep 04, 2025 at 07:03:10PM +0800, Chaoyi Chen wrote:
> > > 
> > > On 9/4/2025 6:58 PM, Russell King (Oracle) wrote:
> > > > On Thu, Sep 04, 2025 at 03:12:24AM +0000, Yao Zi wrote:
> > > > >   	if (plat->phy_node) {
> > > > >   		bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
> > > > >   		ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy);
> > > > > -		/* If it is not integrated_phy, clk_phy is optional */
> > > > > +		/*
> > > > > +		 * If it is not integrated_phy, clk_phy is optional. But we must
> > > > > +		 * set bsp_priv->clk_phy to NULL if clk_phy isn't proivded, or
> > > > > +		 * the error code could be wrongly taken as an invalid pointer.
> > > > > +		 */
> > > > I'm concerned by this. This code is getting the first clock from the DT
> > > > description of the PHY. We don't know what type of PHY it is, or what
> > > > the DT description of that PHY might suggest that the first clock would
> > > > be.
> > > > 
> > > > However, we're geting it and setting it to 50MHz. What if the clock is
> > > > not what we think it is?
> > > 
> > > We only set integrated_phy to 50M, which are all known targets. For external PHYs, we do not perform frequency settings.
> > 
> > Same question concerning enabling and disabling another device's clock
> > that the other device should be handling.
> 
> Let me be absolutely clear: I consider *everything* that is going on
> with clk_phy here to be a dirty hack.
> 
> Resources used by a device that has its own driver should be managed
> by _that_ driver alone, not by some other random driver.

Agree on this. Should we drop the patch, or fix it up for now to at
least prevent the oops? Chaoyi, I guess there's no user of the feature
for now, is it?

Best regards,
Yao Zi

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