From: Catalin Marinas <catalin.marinas@arm.com>
To: Yeoreum Yun <yeoreum.yun@arm.com>
Cc: will@kernel.org, broonie@kernel.org, maz@kernel.org,
oliver.upton@linux.dev, joey.gouly@arm.com, james.morse@arm.com,
ardb@kernel.org, scott@os.amperecomputing.com,
suzuki.poulose@arm.com, yuzenghui@huawei.com,
mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org,
kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH RESEND v7 6/6] arm64: futex: support futex with FEAT_LSUI
Date: Fri, 12 Sep 2025 18:09:15 +0100 [thread overview]
Message-ID: <aMRTu3lcwqhu-dYY@arm.com> (raw)
In-Reply-To: <20250816151929.197589-7-yeoreum.yun@arm.com>
On Sat, Aug 16, 2025 at 04:19:29PM +0100, Yeoreum Yun wrote:
> @@ -115,11 +117,137 @@ __llsc_futex_cmpxchg(u32 __user *uaddr, u32 oldval, u32 newval, u32 *oval)
> return ret;
> }
>
> +#ifdef CONFIG_AS_HAS_LSUI
> +
> +#define __LSUI_PREAMBLE ".arch_extension lsui\n"
> +
> +#define LSUI_FUTEX_ATOMIC_OP(op, asm_op, mb) \
> +static __always_inline int \
> +__lsui_futex_atomic_##op(int oparg, u32 __user *uaddr, int *oval) \
> +{ \
> + int ret = 0; \
> + int oldval; \
> + \
> + uaccess_ttbr0_enable(); \
I think we can drop uaccess_ttbr0_*() from these functions. At the
kconfig level, TTBR0_PAN selects PAN. Hardware with LSUI will also
have PAN (since 8.1), so the above is an unnecessary branch or nop,
depending on how the alternatives play out. But add a comment instead.
> +static __always_inline int
> +__lsui_futex_atomic_eor(int oparg, u32 __user *uaddr, int *oval)
> +{
> + unsigned int loops = LLSC_MAX_LOOPS;
> + int ret, oldval, tmp;
> +
> + uaccess_ttbr0_enable();
> + /*
> + * there are no ldteor/stteor instructions...
> + */
> + asm volatile("// __lsui_futex_atomic_eor\n"
> + __LSUI_PREAMBLE
> +" prfm pstl1strm, %2\n"
> +"1: ldtxr %w1, %2\n"
> +" eor %w3, %w1, %w5\n"
> +"2: stltxr %w0, %w3, %2\n"
> +" cbz %w0, 3f\n"
> +" sub %w4, %w4, %w0\n"
> +" cbnz %w4, 1b\n"
> +" mov %w0, %w6\n"
> +"3:\n"
> +" dmb ish\n"
> + _ASM_EXTABLE_UACCESS_ERR(1b, 3b, %w0)
> + _ASM_EXTABLE_UACCESS_ERR(2b, 3b, %w0)
> + : "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp),
> + "+r" (loops)
> + : "r" (oparg), "Ir" (-EAGAIN)
> + : "memory");
> + uaccess_ttbr0_disable();
> +
> + if (!ret)
> + *oval = oldval;
> +
> + return ret;
> +}
That's an unfortunate omission from the architecture.
> +#define __lsui_llsc_body(op, ...) \
> +({ \
> + alternative_has_cap_likely(ARM64_HAS_LSUI) ? \
> + __lsui_##op(__VA_ARGS__) : __llsc_##op(__VA_ARGS__); \
> +})
> +
> +#else /* CONFIG_AS_HAS_LSUI */
> +
> +#define __lsui_llsc_body(op, ...) __llsc_##op(__VA_ARGS__)
> +
> +#endif /* CONFIG_AS_HAS_LSUI */
> +
> +
> #define FUTEX_ATOMIC_OP(op) \
> static __always_inline int \
> __futex_atomic_##op(int oparg, u32 __user *uaddr, int *oval) \
> { \
> - return __llsc_futex_atomic_##op(oparg, uaddr, oval); \
> + return __lsui_llsc_body(futex_atomic_##op, oparg, uaddr, oval); \
> }
That's what I got confused about. It looks fine:
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
next prev parent reply other threads:[~2025-09-12 17:09 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-16 15:19 [PATCH RESEND v7 0/6] support FEAT_LSUI and apply it on futex atomic ops Yeoreum Yun
2025-08-16 15:19 ` [PATCH RESEND v7 1/6] arm64: cpufeature: add FEAT_LSUI Yeoreum Yun
2025-09-12 16:12 ` Catalin Marinas
2025-08-16 15:19 ` [PATCH RESEND v7 2/6] KVM: arm64: expose FEAT_LSUI to guest Yeoreum Yun
2025-09-12 16:25 ` Catalin Marinas
2025-08-16 15:19 ` [PATCH RESEND v7 3/6] arm64: Kconfig: add LSUI Kconfig Yeoreum Yun
2025-09-12 16:24 ` Catalin Marinas
2025-09-15 10:42 ` Yeoreum Yun
2025-09-15 11:32 ` Will Deacon
2025-09-15 11:41 ` Yeoreum Yun
2025-08-16 15:19 ` [PATCH RESEND v7 4/6] arm64: futex: refactor futex atomic operation Yeoreum Yun
2025-09-11 15:38 ` Will Deacon
2025-09-11 16:04 ` Yeoreum Yun
2025-09-12 16:44 ` Catalin Marinas
2025-09-12 17:01 ` Catalin Marinas
2025-09-15 10:39 ` Yeoreum Yun
2025-09-12 16:53 ` Catalin Marinas
2025-09-15 10:32 ` Yeoreum Yun
2025-09-15 19:40 ` Catalin Marinas
2025-09-15 20:35 ` Will Deacon
2025-09-16 7:02 ` Catalin Marinas
2025-09-16 9:15 ` Yeoreum Yun
2025-09-16 9:24 ` Yeoreum Yun
2025-09-16 10:02 ` Yeoreum Yun
2025-09-16 10:16 ` Will Deacon
2025-09-16 12:50 ` Yeoreum Yun
2025-09-17 9:32 ` Yeoreum Yun
2025-09-16 12:47 ` Mark Rutland
2025-09-16 13:27 ` Yeoreum Yun
2025-09-16 13:45 ` Mark Rutland
2025-09-16 13:58 ` Yeoreum Yun
2025-09-16 14:07 ` Mark Rutland
2025-09-16 14:15 ` Yeoreum Yun
2025-09-15 22:34 ` Yeoreum Yun
2025-09-16 12:53 ` Catalin Marinas
2025-08-16 15:19 ` [PATCH v7 RESEND 5/6] arm64: futex: small optimisation for __llsc_futex_atomic_set() Yeoreum Yun
2025-09-11 15:28 ` Will Deacon
2025-09-11 16:19 ` Yeoreum Yun
2025-09-12 16:36 ` Catalin Marinas
2025-09-15 10:41 ` Yeoreum Yun
2025-08-16 15:19 ` [PATCH RESEND v7 6/6] arm64: futex: support futex with FEAT_LSUI Yeoreum Yun
2025-09-11 15:22 ` Will Deacon
2025-09-11 16:45 ` Yeoreum Yun
2025-09-12 17:16 ` Catalin Marinas
2025-09-15 9:15 ` Yeoreum Yun
2025-09-12 17:09 ` Catalin Marinas [this message]
2025-09-15 8:24 ` Yeoreum Yun
2025-09-01 10:06 ` [PATCH RESEND v7 0/6] support FEAT_LSUI and apply it on futex atomic ops Yeoreum Yun
2025-09-11 15:09 ` Will Deacon
2025-09-11 16:22 ` Catalin Marinas
2025-09-15 20:37 ` Will Deacon
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