[PATCH v5 0/7] drm/xe: Add user commands to WA BB via configfs

[PATCH v5 0/7] drm/xe: Add user commands to WA BB via configfs

[Lucas De Marchi]

Integrate WA BB (aka post context restore bb) with configfs to allow
validation to experiment with the GPU, executing commands on every
context switch.

Setting some registers to experiment:

	# echo 0 > /sys/bus/pci/drivers_autoprobe
	# modprobe xe
	# mkdir  /sys/kernel/config/xe/0000:03:00.0
	# cat > /sys/kernel/config/xe/0000\:03\:00.0/ctx_restore_post_bb  <<EOF
	bcs cmd 11000001 4F100 cafebabe
	vcs cmd 11000001 4F104 0FF1CE
	rcs cmd 11000001 4F108 BAADF00D
	EOF
	# echo 0000:03:00.0 > /sys/bus/pci/drivers/xe/bind
	# intel_reg read mmio:4F100 mmio:4f104 mmio:4f108
                                    (0x0004f100): 0xcafebabe
                                    (0x0004f104): 0x000ff1ce
                                    (0x0004f108): 0xbaadf00d

Same thing can be done with ctx_restore_mid_bb (as long as the register
is not overwritten during the engine restore phase). Which one to use
depends on the purpose of the debug.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
Changes in v5:
- First patches that were just tangentially related (and actual fixes)
  already applied
- Add new patches to support mid context restore (aka INDIRECT_CTX in
  the LRC)
- Link to v4: https://lore.kernel.org/r/20250911-wa-bb-cmds-v4-0-c8f7e48f7eae@intel.com

Changes in v4:
- Taint the kernel
- Link to v3: https://lore.kernel.org/r/20250905-wa-bb-cmds-v3-0-3da2b7bdc73e@intel.com

Changes in v3:
- Minor updates on first patches
- Fix kunit build (without CONFIG_CONFIGFS_FS)
- Fix use of binary attributes failing the expectation of a failed write
  producing an error code
- Link to v2: https://lore.kernel.org/r/20250827-wa-bb-cmds-v2-0-3cdf4d63c72a@intel.com

Changes in v2:
- Drop other refactors and fixes already merged
- Add documentation and make sure it works with intel_reg
- Refactor command parsing to be able to easily extend it for other BBs
  to be added in future.
- Link to v1: https://lore.kernel.org/r/20250523-wa-bb-cmds-v1-0-40b337f71bcd@intel.com
---
Lucas De Marchi (7):
      drm/xe/configfs: Extract function to parse engine
      drm/xe/configfs: Allow to select by class only
      drm/xe/lrc: Allow to add user commands on context switch
      drm/xe/configfs: Add post context restore bb
      drm/xe/lrc: Allow INDIRECT_CTX for more engine classes
      drm/xe/lrc: Allow to add user commands mid context switch
      drm/xe/configfs: Add mid context restore bb

 drivers/gpu/drm/xe/regs/xe_lrc_layout.h |   3 -
 drivers/gpu/drm/xe/xe_configfs.c        | 418 ++++++++++++++++++++++++++++++--
 drivers/gpu/drm/xe/xe_configfs.h        |  10 +
 drivers/gpu/drm/xe/xe_lrc.c             |  83 ++++++-
 4 files changed, 484 insertions(+), 30 deletions(-)

base-commit: c3610fc0ab7c1c668031b3804549187d75550e93
change-id: 20250523-wa-bb-cmds-2a81a7121fc2

Lucas De Marchi

[PATCH v5 1/7] drm/xe/configfs: Extract function to parse engine

[Lucas De Marchi]

Move the part that copies the engine to a local buffer so it can be
shared in future for other configfs attributes parsing an engine.

Reviewed-by: Raag Jadav <raag.jadav@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_configfs.c | 32 +++++++++++++++++++++-----------
 1 file changed, 21 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
index e52808e3199fc..8db7a2af11011 100644
--- a/drivers/gpu/drm/xe/xe_configfs.c
+++ b/drivers/gpu/drm/xe/xe_configfs.c
@@ -283,24 +283,34 @@ static bool lookup_engine_mask(const char *pattern, u64 *mask)
 	return false;
 }
 
+static int parse_engine(const char *s, const char *end_chars, u64 *mask)
+{
+	char buf[MAX_ENGINE_CLASS_CHARS + MAX_ENGINE_INSTANCE_CHARS + 1];
+	size_t len;
+
+	len = strcspn(s, end_chars);
+	if (len >= sizeof(buf))
+		return -EINVAL;
+
+	memcpy(buf, s, len);
+	buf[len] = '\0';
+
+	if (!lookup_engine_mask(buf, mask))
+		return -ENOENT;
+
+	return len;
+}
+
 static ssize_t engines_allowed_store(struct config_item *item, const char *page,
 				     size_t len)
 {
 	struct xe_config_group_device *dev = to_xe_config_group_device(item);
-	size_t patternlen, p;
+	ssize_t patternlen, p;
 	u64 mask, val = 0;
 
 	for (p = 0; p < len; p += patternlen + 1) {
-		char buf[MAX_ENGINE_CLASS_CHARS + MAX_ENGINE_INSTANCE_CHARS + 1];
-
-		patternlen = strcspn(page + p, ",\n");
-		if (patternlen >= sizeof(buf))
-			return -EINVAL;
-
-		memcpy(buf, page + p, patternlen);
-		buf[patternlen] = '\0';
-
-		if (!lookup_engine_mask(buf, &mask))
+		patternlen = parse_engine(page + p, ",\n", &mask);
+		if (patternlen < 0)
 			return -EINVAL;
 
 		val |= mask;

-- 
2.50.1

[PATCH v5 2/7] drm/xe/configfs: Allow to select by class only

[Lucas De Marchi]

For a future configfs attribute, it's desirable to select by engine mask
only as the instance doesn't make sense.

Rename the function lookup_engine_mask() to lookup_engine_info() and
make it return the entry. This allows parse_engine() to still return an
item if the caller wants to allow parsing a class-only string like
"rcs", "bcs", "ccs", etc.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Raag Jadav <raag.jadav@intel.com>
---
v2:
- Rename function to lookup_engine_info() and return the entry
  directly instead of the index (Raag Jadav)
- Add named initializer for new entry for consistency (Raag Jadav)
---
 drivers/gpu/drm/xe/xe_configfs.c | 50 ++++++++++++++++++++++++++++------------
 1 file changed, 35 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
index 8db7a2af11011..45fdb6cf26b5d 100644
--- a/drivers/gpu/drm/xe/xe_configfs.c
+++ b/drivers/gpu/drm/xe/xe_configfs.c
@@ -152,6 +152,7 @@ static void set_device_defaults(struct xe_config_device *config)
 struct engine_info {
 	const char *cls;
 	u64 mask;
+	enum xe_engine_class engine_class;
 };
 
 /* Some helpful macros to aid on the sizing of buffer allocation when parsing */
@@ -159,12 +160,12 @@ struct engine_info {
 #define MAX_ENGINE_INSTANCE_CHARS 2
 
 static const struct engine_info engine_info[] = {
-	{ .cls = "rcs", .mask = XE_HW_ENGINE_RCS_MASK },
-	{ .cls = "bcs", .mask = XE_HW_ENGINE_BCS_MASK },
-	{ .cls = "vcs", .mask = XE_HW_ENGINE_VCS_MASK },
-	{ .cls = "vecs", .mask = XE_HW_ENGINE_VECS_MASK },
-	{ .cls = "ccs", .mask = XE_HW_ENGINE_CCS_MASK },
-	{ .cls = "gsccs", .mask = XE_HW_ENGINE_GSCCS_MASK },
+	{ .cls = "rcs", .mask = XE_HW_ENGINE_RCS_MASK, .engine_class = XE_ENGINE_CLASS_RENDER },
+	{ .cls = "bcs", .mask = XE_HW_ENGINE_BCS_MASK, .engine_class = XE_ENGINE_CLASS_COPY },
+	{ .cls = "vcs", .mask = XE_HW_ENGINE_VCS_MASK, .engine_class = XE_ENGINE_CLASS_VIDEO_DECODE },
+	{ .cls = "vecs", .mask = XE_HW_ENGINE_VECS_MASK, .engine_class = XE_ENGINE_CLASS_VIDEO_ENHANCE },
+	{ .cls = "ccs", .mask = XE_HW_ENGINE_CCS_MASK, .engine_class = XE_ENGINE_CLASS_COMPUTE },
+	{ .cls = "gsccs", .mask = XE_HW_ENGINE_GSCCS_MASK, .engine_class = XE_ENGINE_CLASS_OTHER },
 };
 
 static struct xe_config_group_device *to_xe_config_group_device(struct config_item *item)
@@ -253,7 +254,18 @@ static ssize_t engines_allowed_show(struct config_item *item, char *page)
 	return p - page;
 }
 
-static bool lookup_engine_mask(const char *pattern, u64 *mask)
+/*
+ * Lookup engine_info. If @mask is not NULL, reduce the mask according to the
+ * instance in @pattern.
+ *
+ * Examples of inputs:
+ * - lookup_engine_info("rcs0", &mask): return "rcs" entry from @engine_info and
+ *   mask == BIT_ULL(XE_HW_ENGINE_RCS0)
+ * - lookup_engine_info("rcs*", &mask): return "rcs" entry from @engine_info and
+ *   mask == XE_HW_ENGINE_RCS_MASK
+ * - lookup_engine_info("rcs", NULL): return "rcs" entry from @engine_info
+ */
+static const struct engine_info *lookup_engine_info(const char *pattern, u64 *mask)
 {
 	for (size_t i = 0; i < ARRAY_SIZE(engine_info); i++) {
 		u8 instance;
@@ -263,29 +275,33 @@ static bool lookup_engine_mask(const char *pattern, u64 *mask)
 			continue;
 
 		pattern += strlen(engine_info[i].cls);
+		if (!mask && !*pattern)
+			return &engine_info[i];
 
 		if (!strcmp(pattern, "*")) {
 			*mask = engine_info[i].mask;
-			return true;
+			return &engine_info[i];
 		}
 
 		if (kstrtou8(pattern, 10, &instance))
-			return false;
+			return NULL;
 
 		bit = __ffs64(engine_info[i].mask) + instance;
 		if (bit >= fls64(engine_info[i].mask))
-			return false;
+			return NULL;
 
 		*mask = BIT_ULL(bit);
-		return true;
+		return &engine_info[i];
 	}
 
-	return false;
+	return NULL;
 }
 
-static int parse_engine(const char *s, const char *end_chars, u64 *mask)
+static int parse_engine(const char *s, const char *end_chars, u64 *mask,
+			const struct engine_info **pinfo)
 {
 	char buf[MAX_ENGINE_CLASS_CHARS + MAX_ENGINE_INSTANCE_CHARS + 1];
+	const struct engine_info *info;
 	size_t len;
 
 	len = strcspn(s, end_chars);
@@ -295,9 +311,13 @@ static int parse_engine(const char *s, const char *end_chars, u64 *mask)
 	memcpy(buf, s, len);
 	buf[len] = '\0';
 
-	if (!lookup_engine_mask(buf, mask))
+	info = lookup_engine_info(buf, mask);
+	if (!info)
 		return -ENOENT;
 
+	if (pinfo)
+		*pinfo = info;
+
 	return len;
 }
 
@@ -309,7 +329,7 @@ static ssize_t engines_allowed_store(struct config_item *item, const char *page,
 	u64 mask, val = 0;
 
 	for (p = 0; p < len; p += patternlen + 1) {
-		patternlen = parse_engine(page + p, ",\n", &mask);
+		patternlen = parse_engine(page + p, ",\n", &mask, NULL);
 		if (patternlen < 0)
 			return -EINVAL;
 

-- 
2.50.1

[PATCH v5 3/7] drm/xe/lrc: Allow to add user commands on context switch

[Lucas De Marchi]

During validation it's useful to allows additional commands to be
executed on context switch. Fetch the commands from configfs (to be
added) and add them to the WA BB.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2: Fix warning when building without configfs
v3: Move taint to this patch from the configfs implementation
---
 drivers/gpu/drm/xe/xe_configfs.c | 13 +++++++++++++
 drivers/gpu/drm/xe/xe_configfs.h |  6 ++++++
 drivers/gpu/drm/xe/xe_lrc.c      | 32 ++++++++++++++++++++++++++++++++
 3 files changed, 51 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
index 45fdb6cf26b5d..d86c75af03278 100644
--- a/drivers/gpu/drm/xe/xe_configfs.c
+++ b/drivers/gpu/drm/xe/xe_configfs.c
@@ -633,6 +633,19 @@ bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev)
 	return ret;
 }
 
+/**
+ * xe_configfs_get_ctx_restore_post_bb - get configfs ctx_restore_post_bb setting
+ * @pdev: pci device
+ *
+ * Return: post_ctx_restore setting in configfs
+ */
+u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev,
+					enum xe_engine_class class,
+					const u32 **cs)
+{
+	return 0;
+}
+
 int __init xe_configfs_init(void)
 {
 	int ret;
diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h
index 1402e863b71c0..eff2645b5f593 100644
--- a/drivers/gpu/drm/xe/xe_configfs.h
+++ b/drivers/gpu/drm/xe/xe_configfs.h
@@ -8,6 +8,8 @@
 #include <linux/limits.h>
 #include <linux/types.h>
 
+#include <xe_hw_engine_types.h>
+
 struct pci_dev;
 
 #if IS_ENABLED(CONFIG_CONFIGFS_FS)
@@ -17,6 +19,8 @@ void xe_configfs_check_device(struct pci_dev *pdev);
 bool xe_configfs_get_survivability_mode(struct pci_dev *pdev);
 u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev);
 bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev);
+u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev, enum xe_engine_class,
+					const u32 **cs);
 #else
 static inline int xe_configfs_init(void) { return 0; }
 static inline void xe_configfs_exit(void) { }
@@ -24,6 +28,8 @@ static inline void xe_configfs_check_device(struct pci_dev *pdev) { }
 static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; }
 static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) { return U64_MAX; }
 static inline bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev) { return false; }
+static inline u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev, enum xe_engine_class,
+						      const u32 **cs) { return 0; }
 #endif
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 6d52e0eb97f54..c706585611d55 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -8,6 +8,7 @@
 #include <generated/xe_wa_oob.h>
 
 #include <linux/ascii85.h>
+#include <linux/panic.h>
 
 #include "instructions/xe_mi_commands.h"
 #include "instructions/xe_gfxpipe_commands.h"
@@ -16,6 +17,7 @@
 #include "regs/xe_lrc_layout.h"
 #include "xe_bb.h"
 #include "xe_bo.h"
+#include "xe_configfs.h"
 #include "xe_device.h"
 #include "xe_drm_client.h"
 #include "xe_exec_queue_types.h"
@@ -1102,6 +1104,35 @@ static ssize_t setup_timestamp_wa(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
 	return cmd - batch;
 }
 
+static ssize_t setup_configfs_post_ctx_restore_bb(struct xe_lrc *lrc,
+						  struct xe_hw_engine *hwe,
+						  u32 *batch, size_t max_len)
+{
+	struct xe_device *xe = gt_to_xe(lrc->gt);
+	const u32 *user_batch;
+	u32 *cmd = batch;
+	u32 count;
+
+	count = xe_configfs_get_ctx_restore_post_bb(to_pci_dev(xe->drm.dev),
+						    hwe->class, &user_batch);
+	if (!count)
+		return 0;
+
+	if (count > max_len)
+		return -ENOSPC;
+
+	/*
+	 * This should be used only for tests and validation. Taint the kernel
+	 * as anything could be submitted directly in context switches
+	 */
+	add_taint(TAINT_TEST, LOCKDEP_STILL_OK);
+
+	memcpy(cmd, user_batch, count * sizeof(u32));
+	cmd += count;
+
+	return cmd - batch;
+}
+
 static ssize_t setup_invalidate_state_cache_wa(struct xe_lrc *lrc,
 					       struct xe_hw_engine *hwe,
 					       u32 *batch, size_t max_len)
@@ -1203,6 +1234,7 @@ int xe_lrc_setup_wa_bb_with_scratch(struct xe_lrc *lrc, struct xe_hw_engine *hwe
 		{ .setup = setup_timestamp_wa },
 		{ .setup = setup_invalidate_state_cache_wa },
 		{ .setup = setup_utilization_wa },
+		{ .setup = setup_configfs_post_ctx_restore_bb },
 	};
 	struct bo_setup_state state = {
 		.lrc = lrc,

-- 
2.50.1

Re: [PATCH v5 3/7] drm/xe/lrc: Allow to add user commands on context switch

[Rodrigo Vivi]

On Tue, Sep 16, 2025 at 02:15:40PM -0700, Lucas De Marchi wrote:
> During validation it's useful to allows additional commands to be
> executed on context switch. Fetch the commands from configfs (to be
> added) and add them to the WA BB.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> v2: Fix warning when building without configfs
> v3: Move taint to this patch from the configfs implementation

Better indeed

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_configfs.c | 13 +++++++++++++
>  drivers/gpu/drm/xe/xe_configfs.h |  6 ++++++
>  drivers/gpu/drm/xe/xe_lrc.c      | 32 ++++++++++++++++++++++++++++++++
>  3 files changed, 51 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
> index 45fdb6cf26b5d..d86c75af03278 100644
> --- a/drivers/gpu/drm/xe/xe_configfs.c
> +++ b/drivers/gpu/drm/xe/xe_configfs.c
> @@ -633,6 +633,19 @@ bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev)
>  	return ret;
>  }
>  
> +/**
> + * xe_configfs_get_ctx_restore_post_bb - get configfs ctx_restore_post_bb setting
> + * @pdev: pci device
> + *
> + * Return: post_ctx_restore setting in configfs
> + */
> +u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev,
> +					enum xe_engine_class class,
> +					const u32 **cs)
> +{
> +	return 0;
> +}
> +
>  int __init xe_configfs_init(void)
>  {
>  	int ret;
> diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h
> index 1402e863b71c0..eff2645b5f593 100644
> --- a/drivers/gpu/drm/xe/xe_configfs.h
> +++ b/drivers/gpu/drm/xe/xe_configfs.h
> @@ -8,6 +8,8 @@
>  #include <linux/limits.h>
>  #include <linux/types.h>
>  
> +#include <xe_hw_engine_types.h>
> +
>  struct pci_dev;
>  
>  #if IS_ENABLED(CONFIG_CONFIGFS_FS)
> @@ -17,6 +19,8 @@ void xe_configfs_check_device(struct pci_dev *pdev);
>  bool xe_configfs_get_survivability_mode(struct pci_dev *pdev);
>  u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev);
>  bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev);
> +u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev, enum xe_engine_class,
> +					const u32 **cs);
>  #else
>  static inline int xe_configfs_init(void) { return 0; }
>  static inline void xe_configfs_exit(void) { }
> @@ -24,6 +28,8 @@ static inline void xe_configfs_check_device(struct pci_dev *pdev) { }
>  static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; }
>  static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) { return U64_MAX; }
>  static inline bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev) { return false; }
> +static inline u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev, enum xe_engine_class,
> +						      const u32 **cs) { return 0; }
>  #endif
>  
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index 6d52e0eb97f54..c706585611d55 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -8,6 +8,7 @@
>  #include <generated/xe_wa_oob.h>
>  
>  #include <linux/ascii85.h>
> +#include <linux/panic.h>
>  
>  #include "instructions/xe_mi_commands.h"
>  #include "instructions/xe_gfxpipe_commands.h"
> @@ -16,6 +17,7 @@
>  #include "regs/xe_lrc_layout.h"
>  #include "xe_bb.h"
>  #include "xe_bo.h"
> +#include "xe_configfs.h"
>  #include "xe_device.h"
>  #include "xe_drm_client.h"
>  #include "xe_exec_queue_types.h"
> @@ -1102,6 +1104,35 @@ static ssize_t setup_timestamp_wa(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
>  	return cmd - batch;
>  }
>  
> +static ssize_t setup_configfs_post_ctx_restore_bb(struct xe_lrc *lrc,
> +						  struct xe_hw_engine *hwe,
> +						  u32 *batch, size_t max_len)
> +{
> +	struct xe_device *xe = gt_to_xe(lrc->gt);
> +	const u32 *user_batch;
> +	u32 *cmd = batch;
> +	u32 count;
> +
> +	count = xe_configfs_get_ctx_restore_post_bb(to_pci_dev(xe->drm.dev),
> +						    hwe->class, &user_batch);
> +	if (!count)
> +		return 0;
> +
> +	if (count > max_len)
> +		return -ENOSPC;
> +
> +	/*
> +	 * This should be used only for tests and validation. Taint the kernel
> +	 * as anything could be submitted directly in context switches
> +	 */
> +	add_taint(TAINT_TEST, LOCKDEP_STILL_OK);
> +
> +	memcpy(cmd, user_batch, count * sizeof(u32));
> +	cmd += count;
> +
> +	return cmd - batch;
> +}
> +
>  static ssize_t setup_invalidate_state_cache_wa(struct xe_lrc *lrc,
>  					       struct xe_hw_engine *hwe,
>  					       u32 *batch, size_t max_len)
> @@ -1203,6 +1234,7 @@ int xe_lrc_setup_wa_bb_with_scratch(struct xe_lrc *lrc, struct xe_hw_engine *hwe
>  		{ .setup = setup_timestamp_wa },
>  		{ .setup = setup_invalidate_state_cache_wa },
>  		{ .setup = setup_utilization_wa },
> +		{ .setup = setup_configfs_post_ctx_restore_bb },
>  	};
>  	struct bo_setup_state state = {
>  		.lrc = lrc,
> 
> -- 
> 2.50.1
> 

[PATCH v5 4/7] drm/xe/configfs: Add post context restore bb

[Lucas De Marchi]

Allow the user to specify commands to execute during a context restore.
Currently it's possible to parse 2 types of actions:

	- cmd: the instructions are added as is to the bb
	- reg: just use the address and value, without worrying about
	  encoding the right LRI instruction. This is possibly the most
	  useful use case, so added a dedicated action for that.

This also prepares for future BBs: mid context restore and rc6 context
restore that can re-use the same parsing functions.

Reviewed-by: Raag Jadav <raag.jadav@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
v2:
- use bin attribute to be allow multiline
v3:
- revert attribute back to a simple attribute rather than binary:
  otherwise configfs only calls the callback on the file release and
  ignores the result. With that the user can't rely on the return
  code to know if the setting was accepted.

  To still allow multiline, a method that uses just one syscall should
  be used. In bash, echo will end up using more syscalls. This can be
  workarounded by using heredoc, or simply writing it in C
  (rewrote that listening to
   https://www.youtube.com/watch?v=1S1fISh-pag, you're welcome to review
   listening to that beauty too)
v4: taint with TAINT_TEST (Matt Roper)
v5: move taint to previous patch (Raag)
---
 drivers/gpu/drm/xe/xe_configfs.c | 280 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 278 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
index d86c75af03278..9a30dc958c35c 100644
--- a/drivers/gpu/drm/xe/xe_configfs.c
+++ b/drivers/gpu/drm/xe/xe_configfs.c
@@ -4,6 +4,7 @@
  */
 
 #include <linux/bitops.h>
+#include <linux/ctype.h>
 #include <linux/configfs.h>
 #include <linux/cleanup.h>
 #include <linux/find.h>
@@ -12,6 +13,7 @@
 #include <linux/pci.h>
 #include <linux/string.h>
 
+#include "instructions/xe_mi_commands.h"
 #include "xe_configfs.h"
 #include "xe_hw_engine_types.h"
 #include "xe_module.h"
@@ -115,6 +117,37 @@
  *
  * This attribute can only be set before binding to the device.
  *
+ * Context restore BB
+ * ------------------
+ *
+ * Allow to execute a batch buffer during any context switches. When the
+ * GPU is restoring the context, it executes additional commands. It's useful
+ * for testing additional workarounds and validating certain HW behaviors: it's
+ * not intended for normal execution and will taint the kernel with TAINT_TEST
+ * when used.
+ *
+ * Currently this is implemented only for post context restore. Examples:
+ *
+ * #. Execute a LRI command to write 0xDEADBEEF to register 0x4f10::
+ *
+ *	# echo 'rcs cmd 11000001 4F100 DEADBEEF' \
+ *		> /sys/kernel/config/xe/0000:03:00.0/ctx_restore_post_bb
+ *
+ * #. Load certain values in a couple of registers (it can be used as a simpler
+ *    alternative to the `cmd`) action::
+ *
+ *	# cat > /sys/kernel/config/xe/0000:03:00.0/ctx_restore_post_bb <<EOF
+ *	rcs reg 4F100 DEADBEEF
+ *	rcs reg 4F104 FFFFFFFF
+ *	EOF
+ *
+ *    .. note::
+ *
+ *       When using multiple lines, make sure to use a command that is
+ *       implemented with a single write syscall, like HEREDOC.
+ *
+ * This attribute can only be set before binding to the device.
+ *
  * Remove devices
  * ==============
  *
@@ -123,11 +156,18 @@
  *	# rmdir /sys/kernel/config/xe/0000:03:00.0/
  */
 
+/* Similar to struct xe_bb, but not tied to HW (yet) */
+struct wa_bb {
+	u32 *cs;
+	u32 len; /* in dwords */
+};
+
 struct xe_config_group_device {
 	struct config_group group;
 
 	struct xe_config_device {
 		u64 engines_allowed;
+		struct wa_bb ctx_restore_post_bb[XE_ENGINE_CLASS_MAX];
 		bool survivability_mode;
 		bool enable_psmi;
 	} config;
@@ -371,11 +411,233 @@ static ssize_t enable_psmi_store(struct config_item *item, const char *page, siz
 	return len;
 }
 
+static bool wa_bb_read_advance(bool dereference, char **p,
+			       const char *append, size_t len,
+			       size_t *max_size)
+{
+	if (dereference) {
+		if (len >= *max_size)
+			return false;
+		*max_size -= len;
+		if (append)
+			memcpy(*p, append, len);
+	}
+
+	*p += len;
+
+	return true;
+}
+
+static ssize_t wa_bb_show(struct xe_config_group_device *dev,
+			  struct wa_bb wa_bb[static XE_ENGINE_CLASS_MAX],
+			  char *data, size_t sz)
+{
+	char *p = data;
+
+	guard(mutex)(&dev->lock);
+
+	for (size_t i = 0; i < ARRAY_SIZE(engine_info); i++) {
+		enum xe_engine_class ec = engine_info[i].engine_class;
+		size_t len;
+
+		if (!wa_bb[ec].len)
+			continue;
+
+		len = snprintf(p, sz, "%s:", engine_info[i].cls);
+		if (!wa_bb_read_advance(data, &p, NULL, len, &sz))
+			return -ENOBUFS;
+
+		for (size_t j = 0; j < wa_bb[ec].len; j++) {
+			len = snprintf(p, sz, " %08x", wa_bb[ec].cs[j]);
+			if (!wa_bb_read_advance(data, &p, NULL, len, &sz))
+				return -ENOBUFS;
+		}
+
+		if (!wa_bb_read_advance(data, &p, "\n", 1, &sz))
+			return -ENOBUFS;
+	}
+
+	if (!wa_bb_read_advance(data, &p, "", 1, &sz))
+		return -ENOBUFS;
+
+	/* Reserve one more to match check for '\0' */
+	if (!data)
+		p++;
+
+	return p - data;
+}
+
+static ssize_t ctx_restore_post_bb_show(struct config_item *item, char *page)
+{
+	struct xe_config_group_device *dev = to_xe_config_group_device(item);
+
+	return wa_bb_show(dev, dev->config.ctx_restore_post_bb, page, SZ_4K);
+}
+
+static void wa_bb_append(struct wa_bb *wa_bb, u32 val)
+{
+	if (wa_bb->cs)
+		wa_bb->cs[wa_bb->len] = val;
+
+	wa_bb->len++;
+}
+
+static ssize_t parse_hex(const char *line, u32 *pval)
+{
+	char numstr[12];
+	const char *p;
+	ssize_t numlen;
+
+	p = line + strspn(line, " \t");
+	if (!*p || *p == '\n')
+		return 0;
+
+	numlen = strcspn(p, " \t\n");
+	if (!numlen || numlen >= sizeof(numstr) - 1)
+		return -EINVAL;
+
+	memcpy(numstr, p, numlen);
+	numstr[numlen] = '\0';
+	p += numlen;
+
+	if (kstrtou32(numstr, 16, pval))
+		return -EINVAL;
+
+	return p - line;
+}
+
+/*
+ * Parse lines with the format
+ *
+ *	<engine-class> cmd <u32> <u32...>
+ *	<engine-class> reg <u32_addr> <u32_val>
+ *
+ * and optionally save them in @wa_bb[i].cs is non-NULL.
+ *
+ * Return the number of dwords parsed.
+ */
+static ssize_t parse_wa_bb_lines(const char *lines,
+				 struct wa_bb wa_bb[static XE_ENGINE_CLASS_MAX])
+{
+	ssize_t dwords = 0, ret;
+	const char *p;
+
+	for (p = lines; *p; p++) {
+		const struct engine_info *info = NULL;
+		u32 val, val2;
+
+		/* Also allow empty lines */
+		p += strspn(p, " \t\n");
+		if (!*p)
+			break;
+
+		ret = parse_engine(p, " \t\n", NULL, &info);
+		if (ret < 0)
+			return ret;
+
+		p += ret;
+		p += strspn(p, " \t");
+
+		if (str_has_prefix(p, "cmd")) {
+			for (p += strlen("cmd"); *p;) {
+				ret = parse_hex(p, &val);
+				if (ret < 0)
+					return -EINVAL;
+				if (!ret)
+					break;
+
+				p += ret;
+				dwords++;
+				wa_bb_append(&wa_bb[info->engine_class], val);
+			}
+		} else if (str_has_prefix(p, "reg")) {
+			p += strlen("reg");
+			ret = parse_hex(p, &val);
+			if (ret <= 0)
+				return -EINVAL;
+
+			p += ret;
+			ret = parse_hex(p, &val2);
+			if (ret <= 0)
+				return -EINVAL;
+
+			p += ret;
+			dwords += 3;
+			wa_bb_append(&wa_bb[info->engine_class],
+				     MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1));
+			wa_bb_append(&wa_bb[info->engine_class], val);
+			wa_bb_append(&wa_bb[info->engine_class], val2);
+		} else {
+			return -EINVAL;
+		}
+	}
+
+	return dwords;
+}
+
+static ssize_t wa_bb_store(struct wa_bb wa_bb[static XE_ENGINE_CLASS_MAX],
+			   struct xe_config_group_device *dev,
+			   const char *page, size_t len)
+{
+	/* tmp_wa_bb must match wa_bb's size */
+	struct wa_bb tmp_wa_bb[XE_ENGINE_CLASS_MAX] = { };
+	ssize_t count, class;
+	u32 *tmp;
+
+	/* 1. Count dwords - wa_bb[i].cs is NULL for all classes */
+	count = parse_wa_bb_lines(page, tmp_wa_bb);
+	if (count < 0)
+		return count;
+
+	guard(mutex)(&dev->lock);
+
+	if (is_bound(dev))
+		return -EBUSY;
+
+	/*
+	 * 2. Allocate a u32 array and set the pointers to the right positions
+	 * according to the length of each class' wa_bb
+	 */
+	tmp = krealloc(wa_bb[0].cs, count * sizeof(u32), GFP_KERNEL);
+	if (!tmp)
+		return -ENOMEM;
+
+	if (!count) {
+		memset(wa_bb, 0, sizeof(tmp_wa_bb));
+		return len;
+	}
+
+	for (class = 0, count = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
+		tmp_wa_bb[class].cs = tmp + count;
+		count += tmp_wa_bb[class].len;
+		tmp_wa_bb[class].len = 0;
+	}
+
+	/* 3. Parse wa_bb lines again, this time saving the values */
+	count = parse_wa_bb_lines(page, tmp_wa_bb);
+	if (count < 0)
+		return count;
+
+	memcpy(wa_bb, tmp_wa_bb, sizeof(tmp_wa_bb));
+
+	return len;
+}
+
+static ssize_t ctx_restore_post_bb_store(struct config_item *item,
+					 const char *data, size_t sz)
+{
+	struct xe_config_group_device *dev = to_xe_config_group_device(item);
+
+	return wa_bb_store(dev->config.ctx_restore_post_bb, dev, data, sz);
+}
+
+CONFIGFS_ATTR(, ctx_restore_post_bb);
 CONFIGFS_ATTR(, enable_psmi);
 CONFIGFS_ATTR(, engines_allowed);
 CONFIGFS_ATTR(, survivability_mode);
 
 static struct configfs_attribute *xe_config_device_attrs[] = {
+	&attr_ctx_restore_post_bb,
 	&attr_enable_psmi,
 	&attr_engines_allowed,
 	&attr_survivability_mode,
@@ -387,6 +649,8 @@ static void xe_config_device_release(struct config_item *item)
 	struct xe_config_group_device *dev = to_xe_config_group_device(item);
 
 	mutex_destroy(&dev->lock);
+
+	kfree(dev->config.ctx_restore_post_bb[0].cs);
 	kfree(dev);
 }
 
@@ -636,14 +900,26 @@ bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev)
 /**
  * xe_configfs_get_ctx_restore_post_bb - get configfs ctx_restore_post_bb setting
  * @pdev: pci device
+ * @class: hw engine class
+ * @cs: pointer to the bb to use - only valid during probe
  *
- * Return: post_ctx_restore setting in configfs
+ * Return: Number of dwords used in the post_ctx_restore setting in configfs
  */
 u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev,
 					enum xe_engine_class class,
 					const u32 **cs)
 {
-	return 0;
+	struct xe_config_group_device *dev = find_xe_config_group_device(pdev);
+	u32 len;
+
+	if (!dev)
+		return 0;
+
+	*cs = dev->config.ctx_restore_post_bb[class].cs;
+	len = dev->config.ctx_restore_post_bb[class].len;
+	config_group_put(&dev->group);
+
+	return len;
 }
 
 int __init xe_configfs_init(void)

-- 
2.50.1

Re: [PATCH v5 4/7] drm/xe/configfs: Add post context restore bb

[Kees Bakker]

Op 16-09-2025 om 23:15 schreef Lucas De Marchi:
> Allow the user to specify commands to execute during a context restore.
> Currently it's possible to parse 2 types of actions:
>
> 	- cmd: the instructions are added as is to the bb
> 	- reg: just use the address and value, without worrying about
> 	  encoding the right LRI instruction. This is possibly the most
> 	  useful use case, so added a dedicated action for that.
>
> This also prepares for future BBs: mid context restore and rc6 context
> restore that can re-use the same parsing functions.
>
> Reviewed-by: Raag Jadav <raag.jadav@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> v2:
> - use bin attribute to be allow multiline
> v3:
> - revert attribute back to a simple attribute rather than binary:
>    otherwise configfs only calls the callback on the file release and
>    ignores the result. With that the user can't rely on the return
>    code to know if the setting was accepted.
>
>    To still allow multiline, a method that uses just one syscall should
>    be used. In bash, echo will end up using more syscalls. This can be
>    workarounded by using heredoc, or simply writing it in C
>    (rewrote that listening to
>     https://www.youtube.com/watch?v=1S1fISh-pag, you're welcome to review
>     listening to that beauty too)
> v4: taint with TAINT_TEST (Matt Roper)
> v5: move taint to previous patch (Raag)
> ---
>   drivers/gpu/drm/xe/xe_configfs.c | 280 ++++++++++++++++++++++++++++++++++++++-
>   1 file changed, 278 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
> ...
> +static ssize_t parse_wa_bb_lines(const char *lines,
> +				 struct wa_bb wa_bb[static XE_ENGINE_CLASS_MAX])
> +{
> +	ssize_t dwords = 0, ret;
> +	const char *p;
> +
> +	for (p = lines; *p; p++) {
> +		const struct engine_info *info = NULL;
> +		u32 val, val2;
> +
> +		/* Also allow empty lines */
> +		p += strspn(p, " \t\n");
> +		if (!*p)
> +			break;
> +
> +		ret = parse_engine(p, " \t\n", NULL, &info);
Notice that parse_engine is calling lookup_engine_info with mask being NULL
That function is writing to *mask without checking for NULL.
-- 
Kees

Re: [PATCH v5 4/7] drm/xe/configfs: Add post context restore bb

[Lucas De Marchi]

On Wed, Sep 24, 2025 at 10:31:39PM +0200, Kees Bakker wrote:
>Op 16-09-2025 om 23:15 schreef Lucas De Marchi:
>>Allow the user to specify commands to execute during a context restore.
>>Currently it's possible to parse 2 types of actions:
>>
>>	- cmd: the instructions are added as is to the bb
>>	- reg: just use the address and value, without worrying about
>>	  encoding the right LRI instruction. This is possibly the most
>>	  useful use case, so added a dedicated action for that.
>>
>>This also prepares for future BBs: mid context restore and rc6 context
>>restore that can re-use the same parsing functions.
>>
>>Reviewed-by: Raag Jadav <raag.jadav@intel.com>
>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>---
>>v2:
>>- use bin attribute to be allow multiline
>>v3:
>>- revert attribute back to a simple attribute rather than binary:
>>   otherwise configfs only calls the callback on the file release and
>>   ignores the result. With that the user can't rely on the return
>>   code to know if the setting was accepted.
>>
>>   To still allow multiline, a method that uses just one syscall should
>>   be used. In bash, echo will end up using more syscalls. This can be
>>   workarounded by using heredoc, or simply writing it in C
>>   (rewrote that listening to
>>    https://www.youtube.com/watch?v=1S1fISh-pag, you're welcome to review
>>    listening to that beauty too)
>>v4: taint with TAINT_TEST (Matt Roper)
>>v5: move taint to previous patch (Raag)
>>---
>>  drivers/gpu/drm/xe/xe_configfs.c | 280 ++++++++++++++++++++++++++++++++++++++-
>>  1 file changed, 278 insertions(+), 2 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
>>...
>>+static ssize_t parse_wa_bb_lines(const char *lines,
>>+				 struct wa_bb wa_bb[static XE_ENGINE_CLASS_MAX])
>>+{
>>+	ssize_t dwords = 0, ret;
>>+	const char *p;
>>+
>>+	for (p = lines; *p; p++) {
>>+		const struct engine_info *info = NULL;
>>+		u32 val, val2;
>>+
>>+		/* Also allow empty lines */
>>+		p += strspn(p, " \t\n");
>>+		if (!*p)
>>+			break;
>>+
>>+		ret = parse_engine(p, " \t\n", NULL, &info);
>Notice that parse_engine is calling lookup_engine_info with mask being NULL
>That function is writing to *mask without checking for NULL.

commit dd797967160b ("drm/xe/configfs: Fix engine class parsing")
should have that fixed

Lucas De Marchi

>-- 
>Kees

[PATCH v5 5/7] drm/xe/lrc: Allow INDIRECT_CTX for more engine classes

[Lucas De Marchi]

Currently it's only allowed for render and compute. Going forward we
want to enable it for more engine classes. Let the XE_LRC_FLAG_INDIRECT_CTX
flag (and thus gt_engine_needs_indirect_ctx()) be the deciding factor
for its availability.

While at it, add the missing const to rcs_funcs array. Since
CTX_INDIRECT_CTX_OFFSET_DEFAULT already matches the HW default and
gt_engine_needs_indirect_ctx() only ever enables it for rcs/ccs, there
is no change in behavior, it's only preparation for future use case.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_lrc_layout.h |  3 ---
 drivers/gpu/drm/xe/xe_lrc.c             | 14 ++++++++++----
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
index 1b101edb838bf..b5eff383902c5 100644
--- a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
+++ b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
@@ -40,7 +40,4 @@
 #define INDIRECT_CTX_RING_START_UDW	(0x08 + 1)
 #define INDIRECT_CTX_RING_CTL		(0x0a + 1)
 
-#define CTX_INDIRECT_CTX_OFFSET_MASK	REG_GENMASK(15, 6)
-#define CTX_INDIRECT_CTX_OFFSET_DEFAULT	REG_FIELD_PREP(CTX_INDIRECT_CTX_OFFSET_MASK, 0xd)
-
 #endif
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index c706585611d55..0ab99c210d882 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -1281,9 +1281,11 @@ static int setup_wa_bb(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
 static int
 setup_indirect_ctx(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
 {
-	static struct bo_setup rcs_funcs[] = {
+	static const struct bo_setup rcs_funcs[] = {
 		{ .setup = setup_timestamp_wa },
 	};
+	static const struct bo_setup xcs_funcs[] = {
+	};
 	struct bo_setup_state state = {
 		.lrc = lrc,
 		.hwe = hwe,
@@ -1300,6 +1302,9 @@ setup_indirect_ctx(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
 	    hwe->class == XE_ENGINE_CLASS_COMPUTE) {
 		state.funcs = rcs_funcs;
 		state.num_funcs = ARRAY_SIZE(rcs_funcs);
+	} else {
+		state.funcs = xcs_funcs;
+		state.num_funcs = ARRAY_SIZE(xcs_funcs);
 	}
 
 	if (xe_gt_WARN_ON(lrc->gt, !state.funcs))
@@ -1326,14 +1331,15 @@ setup_indirect_ctx(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
 	finish_bo(&state);
 	kfree(state.buffer);
 
+	/*
+	 * Enable INDIRECT_CTX leaving INDIRECT_CTX_OFFSET at its default: it
+	 * varies per engine class, but the default is good enough
+	 */
 	xe_lrc_write_ctx_reg(lrc,
 			     CTX_CS_INDIRECT_CTX,
 			     (xe_bo_ggtt_addr(lrc->bo) + state.offset) |
 			     /* Size in CLs. */
 			     (state.written * sizeof(u32) / 64));
-	xe_lrc_write_ctx_reg(lrc,
-			     CTX_CS_INDIRECT_CTX_OFFSET,
-			     CTX_INDIRECT_CTX_OFFSET_DEFAULT);
 
 	return 0;
 }

-- 
2.50.1

Re: [PATCH v5 5/7] drm/xe/lrc: Allow INDIRECT_CTX for more engine classes

[Rodrigo Vivi]

On Tue, Sep 16, 2025 at 02:15:42PM -0700, Lucas De Marchi wrote:
> Currently it's only allowed for render and compute. Going forward we
> want to enable it for more engine classes. Let the XE_LRC_FLAG_INDIRECT_CTX
> flag (and thus gt_engine_needs_indirect_ctx()) be the deciding factor
> for its availability.
> 
> While at it, add the missing const to rcs_funcs array. Since
> CTX_INDIRECT_CTX_OFFSET_DEFAULT already matches the HW default and
> gt_engine_needs_indirect_ctx() only ever enables it for rcs/ccs, there
> is no change in behavior, it's only preparation for future use case.
> 

thanks for the offline explanation and pointers

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_lrc_layout.h |  3 ---
>  drivers/gpu/drm/xe/xe_lrc.c             | 14 ++++++++++----
>  2 files changed, 10 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> index 1b101edb838bf..b5eff383902c5 100644
> --- a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> +++ b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
> @@ -40,7 +40,4 @@
>  #define INDIRECT_CTX_RING_START_UDW	(0x08 + 1)
>  #define INDIRECT_CTX_RING_CTL		(0x0a + 1)
>  
> -#define CTX_INDIRECT_CTX_OFFSET_MASK	REG_GENMASK(15, 6)
> -#define CTX_INDIRECT_CTX_OFFSET_DEFAULT	REG_FIELD_PREP(CTX_INDIRECT_CTX_OFFSET_MASK, 0xd)
> -
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index c706585611d55..0ab99c210d882 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -1281,9 +1281,11 @@ static int setup_wa_bb(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
>  static int
>  setup_indirect_ctx(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
>  {
> -	static struct bo_setup rcs_funcs[] = {
> +	static const struct bo_setup rcs_funcs[] = {
>  		{ .setup = setup_timestamp_wa },
>  	};
> +	static const struct bo_setup xcs_funcs[] = {
> +	};
>  	struct bo_setup_state state = {
>  		.lrc = lrc,
>  		.hwe = hwe,
> @@ -1300,6 +1302,9 @@ setup_indirect_ctx(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
>  	    hwe->class == XE_ENGINE_CLASS_COMPUTE) {
>  		state.funcs = rcs_funcs;
>  		state.num_funcs = ARRAY_SIZE(rcs_funcs);
> +	} else {
> +		state.funcs = xcs_funcs;
> +		state.num_funcs = ARRAY_SIZE(xcs_funcs);
>  	}
>  
>  	if (xe_gt_WARN_ON(lrc->gt, !state.funcs))
> @@ -1326,14 +1331,15 @@ setup_indirect_ctx(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
>  	finish_bo(&state);
>  	kfree(state.buffer);
>  
> +	/*
> +	 * Enable INDIRECT_CTX leaving INDIRECT_CTX_OFFSET at its default: it
> +	 * varies per engine class, but the default is good enough
> +	 */
>  	xe_lrc_write_ctx_reg(lrc,
>  			     CTX_CS_INDIRECT_CTX,
>  			     (xe_bo_ggtt_addr(lrc->bo) + state.offset) |
>  			     /* Size in CLs. */
>  			     (state.written * sizeof(u32) / 64));
> -	xe_lrc_write_ctx_reg(lrc,
> -			     CTX_CS_INDIRECT_CTX_OFFSET,
> -			     CTX_INDIRECT_CTX_OFFSET_DEFAULT);
>  
>  	return 0;
>  }
> 
> -- 
> 2.50.1
> 

[PATCH v5 6/7] drm/xe/lrc: Allow to add user commands mid context switch

[Lucas De Marchi]

Like done for post-context-restore commands, allow to add commands from
configfs in the middle of context restore. Since currently the indirect
ctx hardcodes the offset to CTX_INDIRECT_CTX_OFFSET_DEFAULT, this is
executed in the very beginning of engine context restore.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_configfs.c | 15 +++++++++++++++
 drivers/gpu/drm/xe/xe_configfs.h |  4 ++++
 drivers/gpu/drm/xe/xe_lrc.c      | 37 +++++++++++++++++++++++++++++++++++++
 3 files changed, 56 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
index 9a30dc958c35c..90bc5a4b5da71 100644
--- a/drivers/gpu/drm/xe/xe_configfs.c
+++ b/drivers/gpu/drm/xe/xe_configfs.c
@@ -897,6 +897,21 @@ bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev)
 	return ret;
 }
 
+/**
+ * xe_configfs_get_ctx_restore_mid_bb - get configfs ctx_restore_mid_bb setting
+ * @pdev: pci device
+ * @class: hw engine class
+ * @cs: pointer to the bb to use - only valid during probe
+ *
+ * Return: Number of dwords used in the mid_ctx_restore setting in configfs
+ */
+u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev,
+				       enum xe_engine_class class,
+				       const u32 **cs)
+{
+	return 0;
+}
+
 /**
  * xe_configfs_get_ctx_restore_post_bb - get configfs ctx_restore_post_bb setting
  * @pdev: pci device
diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h
index eff2645b5f593..c61e0e47ed94c 100644
--- a/drivers/gpu/drm/xe/xe_configfs.h
+++ b/drivers/gpu/drm/xe/xe_configfs.h
@@ -19,6 +19,8 @@ void xe_configfs_check_device(struct pci_dev *pdev);
 bool xe_configfs_get_survivability_mode(struct pci_dev *pdev);
 u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev);
 bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev);
+u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
+				       const u32 **cs);
 u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev, enum xe_engine_class,
 					const u32 **cs);
 #else
@@ -28,6 +30,8 @@ static inline void xe_configfs_check_device(struct pci_dev *pdev) { }
 static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; }
 static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) { return U64_MAX; }
 static inline bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev) { return false; }
+static inline u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
+						     const u32 **cs) { return 0; }
 static inline u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev, enum xe_engine_class,
 						      const u32 **cs) { return 0; }
 #endif
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 0ab99c210d882..47e9df7750725 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -77,11 +77,17 @@ lrc_to_xe(struct xe_lrc *lrc)
 static bool
 gt_engine_needs_indirect_ctx(struct xe_gt *gt, enum xe_engine_class class)
 {
+	struct xe_device *xe = gt_to_xe(gt);
+
 	if (XE_GT_WA(gt, 16010904313) &&
 	    (class == XE_ENGINE_CLASS_RENDER ||
 	     class == XE_ENGINE_CLASS_COMPUTE))
 		return true;
 
+	if (xe_configfs_get_ctx_restore_mid_bb(to_pci_dev(xe->drm.dev),
+					       class, NULL))
+		return true;
+
 	return false;
 }
 
@@ -1133,6 +1139,35 @@ static ssize_t setup_configfs_post_ctx_restore_bb(struct xe_lrc *lrc,
 	return cmd - batch;
 }
 
+static ssize_t setup_configfs_mid_ctx_restore_bb(struct xe_lrc *lrc,
+						 struct xe_hw_engine *hwe,
+						 u32 *batch, size_t max_len)
+{
+	struct xe_device *xe = gt_to_xe(lrc->gt);
+	const u32 *user_batch;
+	u32 *cmd = batch;
+	u32 count;
+
+	count = xe_configfs_get_ctx_restore_mid_bb(to_pci_dev(xe->drm.dev),
+						   hwe->class, &user_batch);
+	if (!count)
+		return 0;
+
+	if (count > max_len)
+		return -ENOSPC;
+
+	/*
+	 * This should be used only for tests and validation. Taint the kernel
+	 * as anything could be submitted directly in context switches
+	 */
+	add_taint(TAINT_TEST, LOCKDEP_STILL_OK);
+
+	memcpy(cmd, user_batch, count * sizeof(u32));
+	cmd += count;
+
+	return cmd - batch;
+}
+
 static ssize_t setup_invalidate_state_cache_wa(struct xe_lrc *lrc,
 					       struct xe_hw_engine *hwe,
 					       u32 *batch, size_t max_len)
@@ -1283,8 +1318,10 @@ setup_indirect_ctx(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
 {
 	static const struct bo_setup rcs_funcs[] = {
 		{ .setup = setup_timestamp_wa },
+		{ .setup = setup_configfs_mid_ctx_restore_bb },
 	};
 	static const struct bo_setup xcs_funcs[] = {
+		{ .setup = setup_configfs_mid_ctx_restore_bb },
 	};
 	struct bo_setup_state state = {
 		.lrc = lrc,

-- 
2.50.1

Re: [PATCH v5 6/7] drm/xe/lrc: Allow to add user commands mid context switch

[Rodrigo Vivi]

On Tue, Sep 16, 2025 at 02:15:43PM -0700, Lucas De Marchi wrote:
> Like done for post-context-restore commands, allow to add commands from
> configfs in the middle of context restore. Since currently the indirect
> ctx hardcodes the offset to CTX_INDIRECT_CTX_OFFSET_DEFAULT, this is
> executed in the very beginning of engine context restore.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_configfs.c | 15 +++++++++++++++
>  drivers/gpu/drm/xe/xe_configfs.h |  4 ++++
>  drivers/gpu/drm/xe/xe_lrc.c      | 37 +++++++++++++++++++++++++++++++++++++
>  3 files changed, 56 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
> index 9a30dc958c35c..90bc5a4b5da71 100644
> --- a/drivers/gpu/drm/xe/xe_configfs.c
> +++ b/drivers/gpu/drm/xe/xe_configfs.c
> @@ -897,6 +897,21 @@ bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev)
>  	return ret;
>  }
>  
> +/**
> + * xe_configfs_get_ctx_restore_mid_bb - get configfs ctx_restore_mid_bb setting
> + * @pdev: pci device
> + * @class: hw engine class
> + * @cs: pointer to the bb to use - only valid during probe
> + *
> + * Return: Number of dwords used in the mid_ctx_restore setting in configfs
> + */
> +u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev,
> +				       enum xe_engine_class class,
> +				       const u32 **cs)
> +{
> +	return 0;
> +}
> +
>  /**
>   * xe_configfs_get_ctx_restore_post_bb - get configfs ctx_restore_post_bb setting
>   * @pdev: pci device
> diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h
> index eff2645b5f593..c61e0e47ed94c 100644
> --- a/drivers/gpu/drm/xe/xe_configfs.h
> +++ b/drivers/gpu/drm/xe/xe_configfs.h
> @@ -19,6 +19,8 @@ void xe_configfs_check_device(struct pci_dev *pdev);
>  bool xe_configfs_get_survivability_mode(struct pci_dev *pdev);
>  u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev);
>  bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev);
> +u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
> +				       const u32 **cs);
>  u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev, enum xe_engine_class,
>  					const u32 **cs);
>  #else
> @@ -28,6 +30,8 @@ static inline void xe_configfs_check_device(struct pci_dev *pdev) { }
>  static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; }
>  static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) { return U64_MAX; }
>  static inline bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev) { return false; }
> +static inline u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engine_class,
> +						     const u32 **cs) { return 0; }
>  static inline u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev, enum xe_engine_class,
>  						      const u32 **cs) { return 0; }
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index 0ab99c210d882..47e9df7750725 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -77,11 +77,17 @@ lrc_to_xe(struct xe_lrc *lrc)
>  static bool
>  gt_engine_needs_indirect_ctx(struct xe_gt *gt, enum xe_engine_class class)
>  {
> +	struct xe_device *xe = gt_to_xe(gt);
> +
>  	if (XE_GT_WA(gt, 16010904313) &&
>  	    (class == XE_ENGINE_CLASS_RENDER ||
>  	     class == XE_ENGINE_CLASS_COMPUTE))
>  		return true;
>  
> +	if (xe_configfs_get_ctx_restore_mid_bb(to_pci_dev(xe->drm.dev),
> +					       class, NULL))
> +		return true;
> +
>  	return false;
>  }
>  
> @@ -1133,6 +1139,35 @@ static ssize_t setup_configfs_post_ctx_restore_bb(struct xe_lrc *lrc,
>  	return cmd - batch;
>  }
>  
> +static ssize_t setup_configfs_mid_ctx_restore_bb(struct xe_lrc *lrc,
> +						 struct xe_hw_engine *hwe,
> +						 u32 *batch, size_t max_len)
> +{
> +	struct xe_device *xe = gt_to_xe(lrc->gt);
> +	const u32 *user_batch;
> +	u32 *cmd = batch;
> +	u32 count;
> +
> +	count = xe_configfs_get_ctx_restore_mid_bb(to_pci_dev(xe->drm.dev),
> +						   hwe->class, &user_batch);
> +	if (!count)
> +		return 0;
> +
> +	if (count > max_len)
> +		return -ENOSPC;
> +
> +	/*
> +	 * This should be used only for tests and validation. Taint the kernel
> +	 * as anything could be submitted directly in context switches
> +	 */
> +	add_taint(TAINT_TEST, LOCKDEP_STILL_OK);
> +
> +	memcpy(cmd, user_batch, count * sizeof(u32));
> +	cmd += count;
> +
> +	return cmd - batch;
> +}
> +
>  static ssize_t setup_invalidate_state_cache_wa(struct xe_lrc *lrc,
>  					       struct xe_hw_engine *hwe,
>  					       u32 *batch, size_t max_len)
> @@ -1283,8 +1318,10 @@ setup_indirect_ctx(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
>  {
>  	static const struct bo_setup rcs_funcs[] = {
>  		{ .setup = setup_timestamp_wa },
> +		{ .setup = setup_configfs_mid_ctx_restore_bb },
>  	};
>  	static const struct bo_setup xcs_funcs[] = {
> +		{ .setup = setup_configfs_mid_ctx_restore_bb },
>  	};
>  	struct bo_setup_state state = {
>  		.lrc = lrc,
> 
> -- 
> 2.50.1
> 

[PATCH v5 7/7] drm/xe/configfs: Add mid context restore bb

[Lucas De Marchi]

Like done for post context restore, allow the user to add commands to
the middle of context restore, at the beginning of engine restore
commands.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_configfs.c | 46 ++++++++++++++++++++++++++++++++++++----
 1 file changed, 42 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
index 90bc5a4b5da71..640df5bee4579 100644
--- a/drivers/gpu/drm/xe/xe_configfs.c
+++ b/drivers/gpu/drm/xe/xe_configfs.c
@@ -126,13 +126,21 @@
  * not intended for normal execution and will taint the kernel with TAINT_TEST
  * when used.
  *
- * Currently this is implemented only for post context restore. Examples:
+ * Currently this is implemented only for post and mid context restore.
+ * Examples:
  *
- * #. Execute a LRI command to write 0xDEADBEEF to register 0x4f10::
+ * #. Execute a LRI command to write 0xDEADBEEF to register 0x4f10 after the
+ *    normal context restore::
  *
  *	# echo 'rcs cmd 11000001 4F100 DEADBEEF' \
  *		> /sys/kernel/config/xe/0000:03:00.0/ctx_restore_post_bb
  *
+ * #. Execute a LRI command to write 0xDEADBEEF to register 0x4f10 at the
+ *    beginning of the context restore::
+ *
+ *	# echo 'rcs cmd 11000001 4F100 DEADBEEF' \
+ *		> /sys/kernel/config/xe/0000:03:00.0/ctx_restore_mid_bb
+
  * #. Load certain values in a couple of registers (it can be used as a simpler
  *    alternative to the `cmd`) action::
  *
@@ -146,7 +154,7 @@
  *       When using multiple lines, make sure to use a command that is
  *       implemented with a single write syscall, like HEREDOC.
  *
- * This attribute can only be set before binding to the device.
+ * These attributes can only be set before binding to the device.
  *
  * Remove devices
  * ==============
@@ -168,6 +176,7 @@ struct xe_config_group_device {
 	struct xe_config_device {
 		u64 engines_allowed;
 		struct wa_bb ctx_restore_post_bb[XE_ENGINE_CLASS_MAX];
+		struct wa_bb ctx_restore_mid_bb[XE_ENGINE_CLASS_MAX];
 		bool survivability_mode;
 		bool enable_psmi;
 	} config;
@@ -467,6 +476,13 @@ static ssize_t wa_bb_show(struct xe_config_group_device *dev,
 	return p - data;
 }
 
+static ssize_t ctx_restore_mid_bb_show(struct config_item *item, char *page)
+{
+	struct xe_config_group_device *dev = to_xe_config_group_device(item);
+
+	return wa_bb_show(dev, dev->config.ctx_restore_mid_bb, page, SZ_4K);
+}
+
 static ssize_t ctx_restore_post_bb_show(struct config_item *item, char *page)
 {
 	struct xe_config_group_device *dev = to_xe_config_group_device(item);
@@ -623,6 +639,14 @@ static ssize_t wa_bb_store(struct wa_bb wa_bb[static XE_ENGINE_CLASS_MAX],
 	return len;
 }
 
+static ssize_t ctx_restore_mid_bb_store(struct config_item *item,
+					const char *data, size_t sz)
+{
+	struct xe_config_group_device *dev = to_xe_config_group_device(item);
+
+	return wa_bb_store(dev->config.ctx_restore_mid_bb, dev, data, sz);
+}
+
 static ssize_t ctx_restore_post_bb_store(struct config_item *item,
 					 const char *data, size_t sz)
 {
@@ -631,12 +655,14 @@ static ssize_t ctx_restore_post_bb_store(struct config_item *item,
 	return wa_bb_store(dev->config.ctx_restore_post_bb, dev, data, sz);
 }
 
+CONFIGFS_ATTR(, ctx_restore_mid_bb);
 CONFIGFS_ATTR(, ctx_restore_post_bb);
 CONFIGFS_ATTR(, enable_psmi);
 CONFIGFS_ATTR(, engines_allowed);
 CONFIGFS_ATTR(, survivability_mode);
 
 static struct configfs_attribute *xe_config_device_attrs[] = {
+	&attr_ctx_restore_mid_bb,
 	&attr_ctx_restore_post_bb,
 	&attr_enable_psmi,
 	&attr_engines_allowed,
@@ -909,7 +935,19 @@ u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev,
 				       enum xe_engine_class class,
 				       const u32 **cs)
 {
-	return 0;
+	struct xe_config_group_device *dev = find_xe_config_group_device(pdev);
+	u32 len;
+
+	if (!dev)
+		return 0;
+
+	if (cs)
+		*cs = dev->config.ctx_restore_mid_bb[class].cs;
+
+	len = dev->config.ctx_restore_mid_bb[class].len;
+	config_group_put(&dev->group);
+
+	return len;
 }
 
 /**

-- 
2.50.1

Re: [PATCH v5 7/7] drm/xe/configfs: Add mid context restore bb

[Rodrigo Vivi]

On Tue, Sep 16, 2025 at 02:15:44PM -0700, Lucas De Marchi wrote:
> Like done for post context restore, allow the user to add commands to
> the middle of context restore, at the beginning of engine restore
> commands.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_configfs.c | 46 ++++++++++++++++++++++++++++++++++++----
>  1 file changed, 42 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
> index 90bc5a4b5da71..640df5bee4579 100644
> --- a/drivers/gpu/drm/xe/xe_configfs.c
> +++ b/drivers/gpu/drm/xe/xe_configfs.c
> @@ -126,13 +126,21 @@
>   * not intended for normal execution and will taint the kernel with TAINT_TEST
>   * when used.
>   *
> - * Currently this is implemented only for post context restore. Examples:
> + * Currently this is implemented only for post and mid context restore.
> + * Examples:
>   *
> - * #. Execute a LRI command to write 0xDEADBEEF to register 0x4f10::
> + * #. Execute a LRI command to write 0xDEADBEEF to register 0x4f10 after the
> + *    normal context restore::
>   *
>   *	# echo 'rcs cmd 11000001 4F100 DEADBEEF' \
>   *		> /sys/kernel/config/xe/0000:03:00.0/ctx_restore_post_bb
>   *
> + * #. Execute a LRI command to write 0xDEADBEEF to register 0x4f10 at the
> + *    beginning of the context restore::
> + *
> + *	# echo 'rcs cmd 11000001 4F100 DEADBEEF' \
> + *		> /sys/kernel/config/xe/0000:03:00.0/ctx_restore_mid_bb
> +
>   * #. Load certain values in a couple of registers (it can be used as a simpler
>   *    alternative to the `cmd`) action::
>   *
> @@ -146,7 +154,7 @@
>   *       When using multiple lines, make sure to use a command that is
>   *       implemented with a single write syscall, like HEREDOC.
>   *
> - * This attribute can only be set before binding to the device.
> + * These attributes can only be set before binding to the device.
>   *
>   * Remove devices
>   * ==============
> @@ -168,6 +176,7 @@ struct xe_config_group_device {
>  	struct xe_config_device {
>  		u64 engines_allowed;
>  		struct wa_bb ctx_restore_post_bb[XE_ENGINE_CLASS_MAX];
> +		struct wa_bb ctx_restore_mid_bb[XE_ENGINE_CLASS_MAX];
>  		bool survivability_mode;
>  		bool enable_psmi;
>  	} config;
> @@ -467,6 +476,13 @@ static ssize_t wa_bb_show(struct xe_config_group_device *dev,
>  	return p - data;
>  }
>  
> +static ssize_t ctx_restore_mid_bb_show(struct config_item *item, char *page)
> +{
> +	struct xe_config_group_device *dev = to_xe_config_group_device(item);
> +
> +	return wa_bb_show(dev, dev->config.ctx_restore_mid_bb, page, SZ_4K);
> +}
> +
>  static ssize_t ctx_restore_post_bb_show(struct config_item *item, char *page)
>  {
>  	struct xe_config_group_device *dev = to_xe_config_group_device(item);
> @@ -623,6 +639,14 @@ static ssize_t wa_bb_store(struct wa_bb wa_bb[static XE_ENGINE_CLASS_MAX],
>  	return len;
>  }
>  
> +static ssize_t ctx_restore_mid_bb_store(struct config_item *item,
> +					const char *data, size_t sz)
> +{
> +	struct xe_config_group_device *dev = to_xe_config_group_device(item);
> +
> +	return wa_bb_store(dev->config.ctx_restore_mid_bb, dev, data, sz);
> +}
> +
>  static ssize_t ctx_restore_post_bb_store(struct config_item *item,
>  					 const char *data, size_t sz)
>  {
> @@ -631,12 +655,14 @@ static ssize_t ctx_restore_post_bb_store(struct config_item *item,
>  	return wa_bb_store(dev->config.ctx_restore_post_bb, dev, data, sz);
>  }
>  
> +CONFIGFS_ATTR(, ctx_restore_mid_bb);
>  CONFIGFS_ATTR(, ctx_restore_post_bb);
>  CONFIGFS_ATTR(, enable_psmi);
>  CONFIGFS_ATTR(, engines_allowed);
>  CONFIGFS_ATTR(, survivability_mode);
>  
>  static struct configfs_attribute *xe_config_device_attrs[] = {
> +	&attr_ctx_restore_mid_bb,
>  	&attr_ctx_restore_post_bb,
>  	&attr_enable_psmi,
>  	&attr_engines_allowed,
> @@ -909,7 +935,19 @@ u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev,
>  				       enum xe_engine_class class,
>  				       const u32 **cs)
>  {
> -	return 0;
> +	struct xe_config_group_device *dev = find_xe_config_group_device(pdev);
> +	u32 len;
> +
> +	if (!dev)
> +		return 0;
> +
> +	if (cs)
> +		*cs = dev->config.ctx_restore_mid_bb[class].cs;
> +
> +	len = dev->config.ctx_restore_mid_bb[class].len;
> +	config_group_put(&dev->group);
> +
> +	return len;
>  }
>  
>  /**
> 
> -- 
> 2.50.1
> 

✗ CI.checkpatch: warning for drm/xe: Add user commands to WA BB via configfs

[Patchwork]

== Series Details ==

Series: drm/xe: Add user commands to WA BB via configfs
URL   : https://patchwork.freedesktop.org/series/154618/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
fbd08a78c3a3bb17964db2a326514c69c1dca660
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 5cbf02e92d04690ac75fc0f51d817a6f5051efa1
Author: Lucas De Marchi <lucas.demarchi@intel.com>
Date:   Tue Sep 16 14:15:44 2025 -0700

    drm/xe/configfs: Add mid context restore bb
    
    Like done for post context restore, allow the user to add commands to
    the middle of context restore, at the beginning of engine restore
    commands.
    
    Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+ /mt/dim checkpatch c3610fc0ab7c1c668031b3804549187d75550e93 drm-intel
93ff3347ad4b drm/xe/configfs: Extract function to parse engine
50ec07c9f776 drm/xe/configfs: Allow to select by class only
-:41: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#41: FILE: drivers/gpu/drm/xe/xe_configfs.c:165:
+	{ .cls = "vcs", .mask = XE_HW_ENGINE_VCS_MASK, .engine_class = XE_ENGINE_CLASS_VIDEO_DECODE },

-:42: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#42: FILE: drivers/gpu/drm/xe/xe_configfs.c:166:
+	{ .cls = "vecs", .mask = XE_HW_ENGINE_VECS_MASK, .engine_class = XE_ENGINE_CLASS_VIDEO_ENHANCE },

total: 0 errors, 2 warnings, 0 checks, 105 lines checked
42515e16e743 drm/xe/lrc: Allow to add user commands on context switch
6942c31fa605 drm/xe/configfs: Add post context restore bb
b2ca3a46e669 drm/xe/lrc: Allow INDIRECT_CTX for more engine classes
c05578995897 drm/xe/lrc: Allow to add user commands mid context switch
5cbf02e92d04 drm/xe/configfs: Add mid context restore bb

✓ CI.KUnit: success for drm/xe: Add user commands to WA BB via configfs

[Patchwork]

== Series Details ==

Series: drm/xe: Add user commands to WA BB via configfs
URL   : https://patchwork.freedesktop.org/series/154618/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[21:21:45] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:21:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[21:22:26] Starting KUnit Kernel (1/1)...
[21:22:26] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:22:26] ================== guc_buf (11 subtests) ===================
[21:22:26] [PASSED] test_smallest
[21:22:26] [PASSED] test_largest
[21:22:26] [PASSED] test_granular
[21:22:26] [PASSED] test_unique
[21:22:26] [PASSED] test_overlap
[21:22:26] [PASSED] test_reusable
[21:22:26] [PASSED] test_too_big
[21:22:26] [PASSED] test_flush
[21:22:26] [PASSED] test_lookup
[21:22:26] [PASSED] test_data
[21:22:26] [PASSED] test_class
[21:22:26] ===================== [PASSED] guc_buf =====================
[21:22:26] =================== guc_dbm (7 subtests) ===================
[21:22:26] [PASSED] test_empty
[21:22:26] [PASSED] test_default
[21:22:26] ======================== test_size  ========================
[21:22:26] [PASSED] 4
[21:22:26] [PASSED] 8
[21:22:26] [PASSED] 32
[21:22:26] [PASSED] 256
[21:22:26] ==================== [PASSED] test_size ====================
[21:22:26] ======================= test_reuse  ========================
[21:22:26] [PASSED] 4
[21:22:26] [PASSED] 8
[21:22:26] [PASSED] 32
[21:22:26] [PASSED] 256
[21:22:26] =================== [PASSED] test_reuse ====================
[21:22:26] =================== test_range_overlap  ====================
[21:22:26] [PASSED] 4
[21:22:26] [PASSED] 8
[21:22:26] [PASSED] 32
[21:22:26] [PASSED] 256
[21:22:26] =============== [PASSED] test_range_overlap ================
[21:22:26] =================== test_range_compact  ====================
[21:22:26] [PASSED] 4
[21:22:26] [PASSED] 8
[21:22:26] [PASSED] 32
[21:22:26] [PASSED] 256
[21:22:26] =============== [PASSED] test_range_compact ================
[21:22:26] ==================== test_range_spare  =====================
[21:22:26] [PASSED] 4
[21:22:26] [PASSED] 8
[21:22:26] [PASSED] 32
[21:22:26] [PASSED] 256
[21:22:26] ================ [PASSED] test_range_spare =================
[21:22:26] ===================== [PASSED] guc_dbm =====================
[21:22:26] =================== guc_idm (6 subtests) ===================
[21:22:26] [PASSED] bad_init
[21:22:26] [PASSED] no_init
[21:22:26] [PASSED] init_fini
[21:22:26] [PASSED] check_used
[21:22:26] [PASSED] check_quota
[21:22:26] [PASSED] check_all
[21:22:26] ===================== [PASSED] guc_idm =====================
[21:22:26] ================== no_relay (3 subtests) ===================
[21:22:26] [PASSED] xe_drops_guc2pf_if_not_ready
[21:22:26] [PASSED] xe_drops_guc2vf_if_not_ready
[21:22:26] [PASSED] xe_rejects_send_if_not_ready
[21:22:26] ==================== [PASSED] no_relay =====================
[21:22:26] ================== pf_relay (14 subtests) ==================
[21:22:26] [PASSED] pf_rejects_guc2pf_too_short
[21:22:26] [PASSED] pf_rejects_guc2pf_too_long
[21:22:26] [PASSED] pf_rejects_guc2pf_no_payload
[21:22:26] [PASSED] pf_fails_no_payload
[21:22:26] [PASSED] pf_fails_bad_origin
[21:22:26] [PASSED] pf_fails_bad_type
[21:22:26] [PASSED] pf_txn_reports_error
[21:22:26] [PASSED] pf_txn_sends_pf2guc
[21:22:26] [PASSED] pf_sends_pf2guc
[21:22:26] [SKIPPED] pf_loopback_nop
[21:22:26] [SKIPPED] pf_loopback_echo
[21:22:26] [SKIPPED] pf_loopback_fail
[21:22:26] [SKIPPED] pf_loopback_busy
[21:22:26] [SKIPPED] pf_loopback_retry
[21:22:26] ==================== [PASSED] pf_relay =====================
[21:22:26] ================== vf_relay (3 subtests) ===================
[21:22:26] [PASSED] vf_rejects_guc2vf_too_short
[21:22:26] [PASSED] vf_rejects_guc2vf_too_long
[21:22:26] [PASSED] vf_rejects_guc2vf_no_payload
[21:22:26] ==================== [PASSED] vf_relay =====================
[21:22:26] ===================== lmtt (1 subtest) =====================
[21:22:26] ======================== test_ops  =========================
[21:22:26] [PASSED] 2-level
[21:22:26] [PASSED] multi-level
[21:22:26] ==================== [PASSED] test_ops =====================
[21:22:26] ====================== [PASSED] lmtt =======================
[21:22:26] ================= pf_service (11 subtests) =================
[21:22:26] [PASSED] pf_negotiate_any
[21:22:26] [PASSED] pf_negotiate_base_match
[21:22:26] [PASSED] pf_negotiate_base_newer
[21:22:26] [PASSED] pf_negotiate_base_next
[21:22:26] [SKIPPED] pf_negotiate_base_older
[21:22:26] [PASSED] pf_negotiate_base_prev
[21:22:26] [PASSED] pf_negotiate_latest_match
[21:22:26] [PASSED] pf_negotiate_latest_newer
[21:22:26] [PASSED] pf_negotiate_latest_next
[21:22:26] [SKIPPED] pf_negotiate_latest_older
[21:22:26] [SKIPPED] pf_negotiate_latest_prev
[21:22:26] =================== [PASSED] pf_service ====================
[21:22:26] ================= xe_guc_g2g (2 subtests) ==================
[21:22:26] ============== xe_live_guc_g2g_kunit_default  ==============
[21:22:26] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[21:22:26] ============== xe_live_guc_g2g_kunit_allmem  ===============
[21:22:26] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[21:22:26] =================== [SKIPPED] xe_guc_g2g ===================
[21:22:26] =================== xe_mocs (2 subtests) ===================
[21:22:26] ================ xe_live_mocs_kernel_kunit  ================
[21:22:26] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[21:22:26] ================ xe_live_mocs_reset_kunit  =================
[21:22:26] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[21:22:26] ==================== [SKIPPED] xe_mocs =====================
[21:22:26] ================= xe_migrate (2 subtests) ==================
[21:22:26] ================= xe_migrate_sanity_kunit  =================
[21:22:26] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[21:22:26] ================== xe_validate_ccs_kunit  ==================
[21:22:26] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[21:22:26] =================== [SKIPPED] xe_migrate ===================
[21:22:26] ================== xe_dma_buf (1 subtest) ==================
[21:22:26] ==================== xe_dma_buf_kunit  =====================
[21:22:26] ================ [SKIPPED] xe_dma_buf_kunit ================
[21:22:26] =================== [SKIPPED] xe_dma_buf ===================
[21:22:26] ================= xe_bo_shrink (1 subtest) =================
[21:22:26] =================== xe_bo_shrink_kunit  ====================
[21:22:26] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[21:22:26] ================== [SKIPPED] xe_bo_shrink ==================
[21:22:26] ==================== xe_bo (2 subtests) ====================
[21:22:26] ================== xe_ccs_migrate_kunit  ===================
[21:22:26] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[21:22:26] ==================== xe_bo_evict_kunit  ====================
[21:22:26] =============== [SKIPPED] xe_bo_evict_kunit ================
[21:22:26] ===================== [SKIPPED] xe_bo ======================
[21:22:26] ==================== args (11 subtests) ====================
[21:22:26] [PASSED] count_args_test
[21:22:26] [PASSED] call_args_example
[21:22:26] [PASSED] call_args_test
[21:22:26] [PASSED] drop_first_arg_example
[21:22:26] [PASSED] drop_first_arg_test
[21:22:26] [PASSED] first_arg_example
[21:22:26] [PASSED] first_arg_test
[21:22:26] [PASSED] last_arg_example
[21:22:26] [PASSED] last_arg_test
[21:22:26] [PASSED] pick_arg_example
[21:22:26] [PASSED] sep_comma_example
[21:22:26] ====================== [PASSED] args =======================
[21:22:26] =================== xe_pci (3 subtests) ====================
[21:22:26] ==================== check_graphics_ip  ====================
[21:22:26] [PASSED] 12.70 Xe_LPG
[21:22:26] [PASSED] 12.71 Xe_LPG
[21:22:26] [PASSED] 12.74 Xe_LPG+
[21:22:26] [PASSED] 20.01 Xe2_HPG
[21:22:26] [PASSED] 20.02 Xe2_HPG
[21:22:26] [PASSED] 20.04 Xe2_LPG
[21:22:26] [PASSED] 30.00 Xe3_LPG
[21:22:26] [PASSED] 30.01 Xe3_LPG
[21:22:26] [PASSED] 30.03 Xe3_LPG
[21:22:26] ================ [PASSED] check_graphics_ip ================
[21:22:26] ===================== check_media_ip  ======================
[21:22:26] [PASSED] 13.00 Xe_LPM+
[21:22:26] [PASSED] 13.01 Xe2_HPM
[21:22:26] [PASSED] 20.00 Xe2_LPM
[21:22:26] [PASSED] 30.00 Xe3_LPM
[21:22:26] [PASSED] 30.02 Xe3_LPM
[21:22:26] ================= [PASSED] check_media_ip ==================
[21:22:26] ================= check_platform_gt_count  =================
[21:22:26] [PASSED] 0x9A60 (TIGERLAKE)
[21:22:26] [PASSED] 0x9A68 (TIGERLAKE)
[21:22:26] [PASSED] 0x9A70 (TIGERLAKE)
[21:22:26] [PASSED] 0x9A40 (TIGERLAKE)
[21:22:26] [PASSED] 0x9A49 (TIGERLAKE)
[21:22:26] [PASSED] 0x9A59 (TIGERLAKE)
[21:22:26] [PASSED] 0x9A78 (TIGERLAKE)
[21:22:26] [PASSED] 0x9AC0 (TIGERLAKE)
[21:22:26] [PASSED] 0x9AC9 (TIGERLAKE)
[21:22:26] [PASSED] 0x9AD9 (TIGERLAKE)
[21:22:26] [PASSED] 0x9AF8 (TIGERLAKE)
[21:22:26] [PASSED] 0x4C80 (ROCKETLAKE)
[21:22:26] [PASSED] 0x4C8A (ROCKETLAKE)
[21:22:26] [PASSED] 0x4C8B (ROCKETLAKE)
[21:22:26] [PASSED] 0x4C8C (ROCKETLAKE)
[21:22:26] [PASSED] 0x4C90 (ROCKETLAKE)
[21:22:26] [PASSED] 0x4C9A (ROCKETLAKE)
[21:22:26] [PASSED] 0x4680 (ALDERLAKE_S)
[21:22:26] [PASSED] 0x4682 (ALDERLAKE_S)
[21:22:26] [PASSED] 0x4688 (ALDERLAKE_S)
[21:22:26] [PASSED] 0x468A (ALDERLAKE_S)
[21:22:26] [PASSED] 0x468B (ALDERLAKE_S)
[21:22:26] [PASSED] 0x4690 (ALDERLAKE_S)
[21:22:26] [PASSED] 0x4692 (ALDERLAKE_S)
[21:22:26] [PASSED] 0x4693 (ALDERLAKE_S)
[21:22:26] [PASSED] 0x46A0 (ALDERLAKE_P)
[21:22:26] [PASSED] 0x46A1 (ALDERLAKE_P)
[21:22:26] [PASSED] 0x46A2 (ALDERLAKE_P)
[21:22:26] [PASSED] 0x46A3 (ALDERLAKE_P)
[21:22:26] [PASSED] 0x46A6 (ALDERLAKE_P)
[21:22:26] [PASSED] 0x46A8 (ALDERLAKE_P)
[21:22:26] [PASSED] 0x46AA (ALDERLAKE_P)
[21:22:26] [PASSED] 0x462A (ALDERLAKE_P)
[21:22:26] [PASSED] 0x4626 (ALDERLAKE_P)
[21:22:26] [PASSED] 0x4628 (ALDERLAKE_P)
[21:22:26] [PASSED] 0x46B0 (ALDERLAKE_P)
[21:22:26] [PASSED] 0x46B1 (ALDERLAKE_P)
[21:22:26] [PASSED] 0x46B2 (ALDERLAKE_P)
[21:22:26] [PASSED] 0x46B3 (ALDERLAKE_P)
[21:22:26] [PASSED] 0x46C0 (ALDERLAKE_P)
[21:22:26] [PASSED] 0x46C1 (ALDERLAKE_P)
[21:22:26] [PASSED] 0x46C2 (ALDERLAKE_P)
[21:22:26] [PASSED] 0x46C3 (ALDERLAKE_P)
[21:22:26] [PASSED] 0x46D0 (ALDERLAKE_N)
[21:22:26] [PASSED] 0x46D1 (ALDERLAKE_N)
[21:22:26] [PASSED] 0x46D2 (ALDERLAKE_N)
[21:22:26] [PASSED] 0x46D3 (ALDERLAKE_N)
[21:22:26] [PASSED] 0x46D4 (ALDERLAKE_N)
[21:22:26] [PASSED] 0xA721 (ALDERLAKE_P)
[21:22:26] [PASSED] 0xA7A1 (ALDERLAKE_P)
[21:22:26] [PASSED] 0xA7A9 (ALDERLAKE_P)
[21:22:26] [PASSED] 0xA7AC (ALDERLAKE_P)
[21:22:26] [PASSED] 0xA7AD (ALDERLAKE_P)
[21:22:26] [PASSED] 0xA720 (ALDERLAKE_P)
[21:22:26] [PASSED] 0xA7A0 (ALDERLAKE_P)
[21:22:26] [PASSED] 0xA7A8 (ALDERLAKE_P)
[21:22:26] [PASSED] 0xA7AA (ALDERLAKE_P)
[21:22:26] [PASSED] 0xA7AB (ALDERLAKE_P)
[21:22:26] [PASSED] 0xA780 (ALDERLAKE_S)
[21:22:26] [PASSED] 0xA781 (ALDERLAKE_S)
[21:22:26] [PASSED] 0xA782 (ALDERLAKE_S)
[21:22:26] [PASSED] 0xA783 (ALDERLAKE_S)
[21:22:26] [PASSED] 0xA788 (ALDERLAKE_S)
[21:22:26] [PASSED] 0xA789 (ALDERLAKE_S)
[21:22:26] [PASSED] 0xA78A (ALDERLAKE_S)
[21:22:26] [PASSED] 0xA78B (ALDERLAKE_S)
[21:22:26] [PASSED] 0x4905 (DG1)
[21:22:26] [PASSED] 0x4906 (DG1)
[21:22:26] [PASSED] 0x4907 (DG1)
[21:22:26] [PASSED] 0x4908 (DG1)
[21:22:26] [PASSED] 0x4909 (DG1)
[21:22:26] [PASSED] 0x56C0 (DG2)
[21:22:26] [PASSED] 0x56C2 (DG2)
[21:22:26] [PASSED] 0x56C1 (DG2)
[21:22:26] [PASSED] 0x7D51 (METEORLAKE)
[21:22:26] [PASSED] 0x7DD1 (METEORLAKE)
[21:22:26] [PASSED] 0x7D41 (METEORLAKE)
[21:22:26] [PASSED] 0x7D67 (METEORLAKE)
[21:22:26] [PASSED] 0xB640 (METEORLAKE)
[21:22:26] [PASSED] 0x56A0 (DG2)
[21:22:26] [PASSED] 0x56A1 (DG2)
[21:22:26] [PASSED] 0x56A2 (DG2)
[21:22:26] [PASSED] 0x56BE (DG2)
[21:22:26] [PASSED] 0x56BF (DG2)
[21:22:26] [PASSED] 0x5690 (DG2)
[21:22:26] [PASSED] 0x5691 (DG2)
[21:22:26] [PASSED] 0x5692 (DG2)
[21:22:26] [PASSED] 0x56A5 (DG2)
[21:22:26] [PASSED] 0x56A6 (DG2)
[21:22:26] [PASSED] 0x56B0 (DG2)
[21:22:26] [PASSED] 0x56B1 (DG2)
[21:22:26] [PASSED] 0x56BA (DG2)
[21:22:26] [PASSED] 0x56BB (DG2)
[21:22:26] [PASSED] 0x56BC (DG2)
[21:22:26] [PASSED] 0x56BD (DG2)
[21:22:26] [PASSED] 0x5693 (DG2)
[21:22:26] [PASSED] 0x5694 (DG2)
[21:22:26] [PASSED] 0x5695 (DG2)
[21:22:26] [PASSED] 0x56A3 (DG2)
[21:22:26] [PASSED] 0x56A4 (DG2)
[21:22:26] [PASSED] 0x56B2 (DG2)
[21:22:26] [PASSED] 0x56B3 (DG2)
[21:22:26] [PASSED] 0x5696 (DG2)
[21:22:26] [PASSED] 0x5697 (DG2)
[21:22:26] [PASSED] 0xB69 (PVC)
[21:22:26] [PASSED] 0xB6E (PVC)
[21:22:26] [PASSED] 0xBD4 (PVC)
[21:22:26] [PASSED] 0xBD5 (PVC)
[21:22:26] [PASSED] 0xBD6 (PVC)
[21:22:26] [PASSED] 0xBD7 (PVC)
[21:22:26] [PASSED] 0xBD8 (PVC)
[21:22:26] [PASSED] 0xBD9 (PVC)
[21:22:26] [PASSED] 0xBDA (PVC)
[21:22:26] [PASSED] 0xBDB (PVC)
[21:22:26] [PASSED] 0xBE0 (PVC)
[21:22:26] [PASSED] 0xBE1 (PVC)
[21:22:26] [PASSED] 0xBE5 (PVC)
[21:22:26] [PASSED] 0x7D40 (METEORLAKE)
[21:22:26] [PASSED] 0x7D45 (METEORLAKE)
[21:22:26] [PASSED] 0x7D55 (METEORLAKE)
[21:22:26] [PASSED] 0x7D60 (METEORLAKE)
[21:22:26] [PASSED] 0x7DD5 (METEORLAKE)
[21:22:26] [PASSED] 0x6420 (LUNARLAKE)
[21:22:26] [PASSED] 0x64A0 (LUNARLAKE)
[21:22:26] [PASSED] 0x64B0 (LUNARLAKE)
[21:22:26] [PASSED] 0xE202 (BATTLEMAGE)
[21:22:26] [PASSED] 0xE209 (BATTLEMAGE)
[21:22:26] [PASSED] 0xE20B (BATTLEMAGE)
[21:22:26] [PASSED] 0xE20C (BATTLEMAGE)
[21:22:26] [PASSED] 0xE20D (BATTLEMAGE)
[21:22:26] [PASSED] 0xE210 (BATTLEMAGE)
[21:22:26] [PASSED] 0xE211 (BATTLEMAGE)
[21:22:26] [PASSED] 0xE212 (BATTLEMAGE)
[21:22:26] [PASSED] 0xE216 (BATTLEMAGE)
[21:22:26] [PASSED] 0xE220 (BATTLEMAGE)
[21:22:26] [PASSED] 0xE221 (BATTLEMAGE)
[21:22:26] [PASSED] 0xE222 (BATTLEMAGE)
[21:22:26] [PASSED] 0xE223 (BATTLEMAGE)
[21:22:26] [PASSED] 0xB080 (PANTHERLAKE)
[21:22:26] [PASSED] 0xB081 (PANTHERLAKE)
[21:22:26] [PASSED] 0xB082 (PANTHERLAKE)
[21:22:26] [PASSED] 0xB083 (PANTHERLAKE)
[21:22:26] [PASSED] 0xB084 (PANTHERLAKE)
[21:22:26] [PASSED] 0xB085 (PANTHERLAKE)
[21:22:26] [PASSED] 0xB086 (PANTHERLAKE)
[21:22:26] [PASSED] 0xB087 (PANTHERLAKE)
[21:22:26] [PASSED] 0xB08F (PANTHERLAKE)
[21:22:26] [PASSED] 0xB090 (PANTHERLAKE)
[21:22:26] [PASSED] 0xB0A0 (PANTHERLAKE)
[21:22:26] [PASSED] 0xB0B0 (PANTHERLAKE)
[21:22:26] [PASSED] 0xFD80 (PANTHERLAKE)
[21:22:26] [PASSED] 0xFD81 (PANTHERLAKE)
[21:22:26] ============= [PASSED] check_platform_gt_count =============
[21:22:26] ===================== [PASSED] xe_pci ======================
[21:22:26] =================== xe_rtp (2 subtests) ====================
[21:22:26] =============== xe_rtp_process_to_sr_tests  ================
[21:22:26] [PASSED] coalesce-same-reg
[21:22:26] [PASSED] no-match-no-add
[21:22:26] [PASSED] match-or
[21:22:26] [PASSED] match-or-xfail
[21:22:26] [PASSED] no-match-no-add-multiple-rules
[21:22:26] [PASSED] two-regs-two-entries
[21:22:26] [PASSED] clr-one-set-other
[21:22:26] [PASSED] set-field
[21:22:26] [PASSED] conflict-duplicate
[21:22:26] [PASSED] conflict-not-disjoint
[21:22:26] [PASSED] conflict-reg-type
[21:22:26] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[21:22:26] ================== xe_rtp_process_tests  ===================
[21:22:26] [PASSED] active1
[21:22:26] [PASSED] active2
[21:22:26] [PASSED] active-inactive
[21:22:26] [PASSED] inactive-active
[21:22:26] [PASSED] inactive-1st_or_active-inactive
[21:22:26] [PASSED] inactive-2nd_or_active-inactive
[21:22:26] [PASSED] inactive-last_or_active-inactive
[21:22:26] [PASSED] inactive-no_or_active-inactive
[21:22:26] ============== [PASSED] xe_rtp_process_tests ===============
[21:22:26] ===================== [PASSED] xe_rtp ======================
[21:22:26] ==================== xe_wa (1 subtest) =====================
[21:22:26] ======================== xe_wa_gt  =========================
[21:22:26] [PASSED] TIGERLAKE B0
[21:22:26] [PASSED] DG1 A0
[21:22:26] [PASSED] DG1 B0
[21:22:26] [PASSED] ALDERLAKE_S A0
[21:22:26] [PASSED] ALDERLAKE_S B0
[21:22:26] [PASSED] ALDERLAKE_S C0
[21:22:26] [PASSED] ALDERLAKE_S D0
[21:22:26] [PASSED] ALDERLAKE_P A0
[21:22:26] [PASSED] ALDERLAKE_P B0
[21:22:26] [PASSED] ALDERLAKE_P C0stty: 'standard input': Inappropriate ioctl for device

[21:22:26] [PASSED] ALDERLAKE_S RPLS D0
[21:22:26] [PASSED] ALDERLAKE_P RPLU E0
[21:22:26] [PASSED] DG2 G10 C0
[21:22:26] [PASSED] DG2 G11 B1
[21:22:26] [PASSED] DG2 G12 A1
[21:22:26] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:22:26] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[21:22:26] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[21:22:26] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[21:22:26] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[21:22:26] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[21:22:26] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[21:22:26] ==================== [PASSED] xe_wa_gt =====================
[21:22:26] ====================== [PASSED] xe_wa ======================
[21:22:26] ============================================================
[21:22:26] Testing complete. Ran 300 tests: passed: 282, skipped: 18
[21:22:27] Elapsed time: 41.429s total, 4.300s configuring, 36.763s building, 0.330s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[21:22:27] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:22:28] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[21:22:57] Starting KUnit Kernel (1/1)...
[21:22:57] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:22:57] ============ drm_test_pick_cmdline (2 subtests) ============
[21:22:57] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[21:22:57] =============== drm_test_pick_cmdline_named  ===============
[21:22:57] [PASSED] NTSC
[21:22:57] [PASSED] NTSC-J
[21:22:57] [PASSED] PAL
[21:22:57] [PASSED] PAL-M
[21:22:57] =========== [PASSED] drm_test_pick_cmdline_named ===========
[21:22:57] ============== [PASSED] drm_test_pick_cmdline ==============
[21:22:57] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[21:22:57] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[21:22:57] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[21:22:57] =========== drm_validate_clone_mode (2 subtests) ===========
[21:22:57] ============== drm_test_check_in_clone_mode  ===============
[21:22:57] [PASSED] in_clone_mode
[21:22:57] [PASSED] not_in_clone_mode
[21:22:57] ========== [PASSED] drm_test_check_in_clone_mode ===========
[21:22:57] =============== drm_test_check_valid_clones  ===============
[21:22:57] [PASSED] not_in_clone_mode
[21:22:57] [PASSED] valid_clone
[21:22:57] [PASSED] invalid_clone
[21:22:57] =========== [PASSED] drm_test_check_valid_clones ===========
[21:22:57] ============= [PASSED] drm_validate_clone_mode =============
[21:22:57] ============= drm_validate_modeset (1 subtest) =============
[21:22:57] [PASSED] drm_test_check_connector_changed_modeset
[21:22:57] ============== [PASSED] drm_validate_modeset ===============
[21:22:57] ====== drm_test_bridge_get_current_state (2 subtests) ======
[21:22:57] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[21:22:57] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[21:22:57] ======== [PASSED] drm_test_bridge_get_current_state ========
[21:22:57] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[21:22:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[21:22:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[21:22:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[21:22:57] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[21:22:57] ============== drm_bridge_alloc (2 subtests) ===============
[21:22:57] [PASSED] drm_test_drm_bridge_alloc_basic
[21:22:57] [PASSED] drm_test_drm_bridge_alloc_get_put
[21:22:57] ================ [PASSED] drm_bridge_alloc =================
[21:22:57] ================== drm_buddy (7 subtests) ==================
[21:22:57] [PASSED] drm_test_buddy_alloc_limit
[21:22:57] [PASSED] drm_test_buddy_alloc_optimistic
[21:22:57] [PASSED] drm_test_buddy_alloc_pessimistic
[21:22:57] [PASSED] drm_test_buddy_alloc_pathological
[21:22:57] [PASSED] drm_test_buddy_alloc_contiguous
[21:22:57] [PASSED] drm_test_buddy_alloc_clear
[21:22:57] [PASSED] drm_test_buddy_alloc_range_bias
[21:22:57] ==================== [PASSED] drm_buddy ====================
[21:22:57] ============= drm_cmdline_parser (40 subtests) =============
[21:22:57] [PASSED] drm_test_cmdline_force_d_only
[21:22:57] [PASSED] drm_test_cmdline_force_D_only_dvi
[21:22:57] [PASSED] drm_test_cmdline_force_D_only_hdmi
[21:22:57] [PASSED] drm_test_cmdline_force_D_only_not_digital
[21:22:57] [PASSED] drm_test_cmdline_force_e_only
[21:22:57] [PASSED] drm_test_cmdline_res
[21:22:57] [PASSED] drm_test_cmdline_res_vesa
[21:22:57] [PASSED] drm_test_cmdline_res_vesa_rblank
[21:22:57] [PASSED] drm_test_cmdline_res_rblank
[21:22:57] [PASSED] drm_test_cmdline_res_bpp
[21:22:57] [PASSED] drm_test_cmdline_res_refresh
[21:22:57] [PASSED] drm_test_cmdline_res_bpp_refresh
[21:22:57] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[21:22:57] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[21:22:57] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[21:22:57] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[21:22:57] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[21:22:57] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[21:22:57] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[21:22:57] [PASSED] drm_test_cmdline_res_margins_force_on
[21:22:57] [PASSED] drm_test_cmdline_res_vesa_margins
[21:22:57] [PASSED] drm_test_cmdline_name
[21:22:57] [PASSED] drm_test_cmdline_name_bpp
[21:22:57] [PASSED] drm_test_cmdline_name_option
[21:22:57] [PASSED] drm_test_cmdline_name_bpp_option
[21:22:57] [PASSED] drm_test_cmdline_rotate_0
[21:22:57] [PASSED] drm_test_cmdline_rotate_90
[21:22:57] [PASSED] drm_test_cmdline_rotate_180
[21:22:57] [PASSED] drm_test_cmdline_rotate_270
[21:22:57] [PASSED] drm_test_cmdline_hmirror
[21:22:57] [PASSED] drm_test_cmdline_vmirror
[21:22:57] [PASSED] drm_test_cmdline_margin_options
[21:22:57] [PASSED] drm_test_cmdline_multiple_options
[21:22:57] [PASSED] drm_test_cmdline_bpp_extra_and_option
[21:22:57] [PASSED] drm_test_cmdline_extra_and_option
[21:22:57] [PASSED] drm_test_cmdline_freestanding_options
[21:22:57] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[21:22:57] [PASSED] drm_test_cmdline_panel_orientation
[21:22:57] ================ drm_test_cmdline_invalid  =================
[21:22:57] [PASSED] margin_only
[21:22:57] [PASSED] interlace_only
[21:22:57] [PASSED] res_missing_x
[21:22:57] [PASSED] res_missing_y
[21:22:57] [PASSED] res_bad_y
[21:22:57] [PASSED] res_missing_y_bpp
[21:22:57] [PASSED] res_bad_bpp
[21:22:57] [PASSED] res_bad_refresh
[21:22:57] [PASSED] res_bpp_refresh_force_on_off
[21:22:57] [PASSED] res_invalid_mode
[21:22:57] [PASSED] res_bpp_wrong_place_mode
[21:22:57] [PASSED] name_bpp_refresh
[21:22:57] [PASSED] name_refresh
[21:22:57] [PASSED] name_refresh_wrong_mode
[21:22:57] [PASSED] name_refresh_invalid_mode
[21:22:57] [PASSED] rotate_multiple
[21:22:57] [PASSED] rotate_invalid_val
[21:22:57] [PASSED] rotate_truncated
[21:22:57] [PASSED] invalid_option
[21:22:57] [PASSED] invalid_tv_option
[21:22:57] [PASSED] truncated_tv_option
[21:22:57] ============ [PASSED] drm_test_cmdline_invalid =============
[21:22:57] =============== drm_test_cmdline_tv_options  ===============
[21:22:57] [PASSED] NTSC
[21:22:57] [PASSED] NTSC_443
[21:22:57] [PASSED] NTSC_J
[21:22:57] [PASSED] PAL
[21:22:57] [PASSED] PAL_M
[21:22:57] [PASSED] PAL_N
[21:22:57] [PASSED] SECAM
[21:22:57] [PASSED] MONO_525
[21:22:57] [PASSED] MONO_625
[21:22:57] =========== [PASSED] drm_test_cmdline_tv_options ===========
[21:22:57] =============== [PASSED] drm_cmdline_parser ================
[21:22:57] ========== drmm_connector_hdmi_init (20 subtests) ==========
[21:22:57] [PASSED] drm_test_connector_hdmi_init_valid
[21:22:57] [PASSED] drm_test_connector_hdmi_init_bpc_8
[21:22:57] [PASSED] drm_test_connector_hdmi_init_bpc_10
[21:22:57] [PASSED] drm_test_connector_hdmi_init_bpc_12
[21:22:57] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[21:22:57] [PASSED] drm_test_connector_hdmi_init_bpc_null
[21:22:57] [PASSED] drm_test_connector_hdmi_init_formats_empty
[21:22:57] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[21:22:57] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[21:22:57] [PASSED] supported_formats=0x9 yuv420_allowed=1
[21:22:57] [PASSED] supported_formats=0x9 yuv420_allowed=0
[21:22:57] [PASSED] supported_formats=0x3 yuv420_allowed=1
[21:22:57] [PASSED] supported_formats=0x3 yuv420_allowed=0
[21:22:57] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:22:57] [PASSED] drm_test_connector_hdmi_init_null_ddc
[21:22:57] [PASSED] drm_test_connector_hdmi_init_null_product
[21:22:57] [PASSED] drm_test_connector_hdmi_init_null_vendor
[21:22:57] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[21:22:57] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[21:22:57] [PASSED] drm_test_connector_hdmi_init_product_valid
[21:22:57] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[21:22:57] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[21:22:57] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[21:22:57] ========= drm_test_connector_hdmi_init_type_valid  =========
[21:22:57] [PASSED] HDMI-A
[21:22:57] [PASSED] HDMI-B
[21:22:57] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[21:22:57] ======== drm_test_connector_hdmi_init_type_invalid  ========
[21:22:57] [PASSED] Unknown
[21:22:57] [PASSED] VGA
[21:22:57] [PASSED] DVI-I
[21:22:57] [PASSED] DVI-D
[21:22:57] [PASSED] DVI-A
[21:22:57] [PASSED] Composite
[21:22:57] [PASSED] SVIDEO
[21:22:57] [PASSED] LVDS
[21:22:57] [PASSED] Component
[21:22:57] [PASSED] DIN
[21:22:57] [PASSED] DP
[21:22:57] [PASSED] TV
[21:22:57] [PASSED] eDP
[21:22:57] [PASSED] Virtual
[21:22:57] [PASSED] DSI
[21:22:57] [PASSED] DPI
[21:22:57] [PASSED] Writeback
[21:22:57] [PASSED] SPI
[21:22:57] [PASSED] USB
[21:22:57] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[21:22:57] ============ [PASSED] drmm_connector_hdmi_init =============
[21:22:57] ============= drmm_connector_init (3 subtests) =============
[21:22:57] [PASSED] drm_test_drmm_connector_init
[21:22:57] [PASSED] drm_test_drmm_connector_init_null_ddc
[21:22:57] ========= drm_test_drmm_connector_init_type_valid  =========
[21:22:57] [PASSED] Unknown
[21:22:57] [PASSED] VGA
[21:22:57] [PASSED] DVI-I
[21:22:57] [PASSED] DVI-D
[21:22:57] [PASSED] DVI-A
[21:22:57] [PASSED] Composite
[21:22:57] [PASSED] SVIDEO
[21:22:57] [PASSED] LVDS
[21:22:57] [PASSED] Component
[21:22:57] [PASSED] DIN
[21:22:57] [PASSED] DP
[21:22:57] [PASSED] HDMI-A
[21:22:57] [PASSED] HDMI-B
[21:22:57] [PASSED] TV
[21:22:57] [PASSED] eDP
[21:22:57] [PASSED] Virtual
[21:22:57] [PASSED] DSI
[21:22:57] [PASSED] DPI
[21:22:57] [PASSED] Writeback
[21:22:57] [PASSED] SPI
[21:22:57] [PASSED] USB
[21:22:57] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[21:22:57] =============== [PASSED] drmm_connector_init ===============
[21:22:57] ========= drm_connector_dynamic_init (6 subtests) ==========
[21:22:57] [PASSED] drm_test_drm_connector_dynamic_init
[21:22:57] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[21:22:57] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[21:22:57] [PASSED] drm_test_drm_connector_dynamic_init_properties
[21:22:57] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[21:22:57] [PASSED] Unknown
[21:22:57] [PASSED] VGA
[21:22:57] [PASSED] DVI-I
[21:22:57] [PASSED] DVI-D
[21:22:57] [PASSED] DVI-A
[21:22:57] [PASSED] Composite
[21:22:57] [PASSED] SVIDEO
[21:22:57] [PASSED] LVDS
[21:22:57] [PASSED] Component
[21:22:57] [PASSED] DIN
[21:22:57] [PASSED] DP
[21:22:57] [PASSED] HDMI-A
[21:22:57] [PASSED] HDMI-B
[21:22:57] [PASSED] TV
[21:22:57] [PASSED] eDP
[21:22:57] [PASSED] Virtual
[21:22:57] [PASSED] DSI
[21:22:57] [PASSED] DPI
[21:22:57] [PASSED] Writeback
[21:22:57] [PASSED] SPI
[21:22:57] [PASSED] USB
[21:22:57] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[21:22:57] ======== drm_test_drm_connector_dynamic_init_name  =========
[21:22:57] [PASSED] Unknown
[21:22:57] [PASSED] VGA
[21:22:57] [PASSED] DVI-I
[21:22:57] [PASSED] DVI-D
[21:22:57] [PASSED] DVI-A
[21:22:57] [PASSED] Composite
[21:22:57] [PASSED] SVIDEO
[21:22:57] [PASSED] LVDS
[21:22:57] [PASSED] Component
[21:22:57] [PASSED] DIN
[21:22:57] [PASSED] DP
[21:22:57] [PASSED] HDMI-A
[21:22:57] [PASSED] HDMI-B
[21:22:57] [PASSED] TV
[21:22:57] [PASSED] eDP
[21:22:57] [PASSED] Virtual
[21:22:57] [PASSED] DSI
[21:22:57] [PASSED] DPI
[21:22:57] [PASSED] Writeback
[21:22:57] [PASSED] SPI
[21:22:57] [PASSED] USB
[21:22:57] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[21:22:57] =========== [PASSED] drm_connector_dynamic_init ============
[21:22:57] ==== drm_connector_dynamic_register_early (4 subtests) =====
[21:22:57] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[21:22:57] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[21:22:57] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[21:22:57] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[21:22:57] ====== [PASSED] drm_connector_dynamic_register_early =======
[21:22:57] ======= drm_connector_dynamic_register (7 subtests) ========
[21:22:57] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[21:22:57] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[21:22:57] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[21:22:57] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[21:22:57] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[21:22:57] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[21:22:57] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[21:22:57] ========= [PASSED] drm_connector_dynamic_register ==========
[21:22:57] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[21:22:57] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[21:22:57] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[21:22:57] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[21:22:57] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[21:22:57] ========== drm_test_get_tv_mode_from_name_valid  ===========
[21:22:57] [PASSED] NTSC
[21:22:57] [PASSED] NTSC-443
[21:22:57] [PASSED] NTSC-J
[21:22:57] [PASSED] PAL
[21:22:57] [PASSED] PAL-M
[21:22:57] [PASSED] PAL-N
[21:22:57] [PASSED] SECAM
[21:22:57] [PASSED] Mono
[21:22:57] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[21:22:57] [PASSED] drm_test_get_tv_mode_from_name_truncated
[21:22:57] ============ [PASSED] drm_get_tv_mode_from_name ============
[21:22:57] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[21:22:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[21:22:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[21:22:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[21:22:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[21:22:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[21:22:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[21:22:57] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[21:22:57] [PASSED] VIC 96
[21:22:57] [PASSED] VIC 97
[21:22:57] [PASSED] VIC 101
[21:22:57] [PASSED] VIC 102
[21:22:57] [PASSED] VIC 106
[21:22:57] [PASSED] VIC 107
[21:22:57] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[21:22:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[21:22:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[21:22:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[21:22:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[21:22:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[21:22:57] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[21:22:57] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[21:22:57] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[21:22:57] [PASSED] Automatic
[21:22:57] [PASSED] Full
[21:22:57] [PASSED] Limited 16:235
[21:22:57] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[21:22:57] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[21:22:57] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[21:22:57] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[21:22:57] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[21:22:57] [PASSED] RGB
[21:22:57] [PASSED] YUV 4:2:0
[21:22:57] [PASSED] YUV 4:2:2
[21:22:57] [PASSED] YUV 4:4:4
[21:22:57] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[21:22:57] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[21:22:57] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[21:22:57] ============= drm_damage_helper (21 subtests) ==============
[21:22:57] [PASSED] drm_test_damage_iter_no_damage
[21:22:57] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[21:22:57] [PASSED] drm_test_damage_iter_no_damage_src_moved
[21:22:57] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[21:22:57] [PASSED] drm_test_damage_iter_no_damage_not_visible
[21:22:57] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[21:22:57] [PASSED] drm_test_damage_iter_no_damage_no_fb
[21:22:57] [PASSED] drm_test_damage_iter_simple_damage
[21:22:57] [PASSED] drm_test_damage_iter_single_damage
[21:22:57] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[21:22:57] [PASSED] drm_test_damage_iter_single_damage_outside_src
[21:22:57] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[21:22:57] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[21:22:57] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[21:22:57] [PASSED] drm_test_damage_iter_single_damage_src_moved
[21:22:57] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[21:22:57] [PASSED] drm_test_damage_iter_damage
[21:22:57] [PASSED] drm_test_damage_iter_damage_one_intersect
[21:22:57] [PASSED] drm_test_damage_iter_damage_one_outside
[21:22:57] [PASSED] drm_test_damage_iter_damage_src_moved
[21:22:57] [PASSED] drm_test_damage_iter_damage_not_visible
[21:22:57] ================ [PASSED] drm_damage_helper ================
[21:22:57] ============== drm_dp_mst_helper (3 subtests) ==============
[21:22:57] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[21:22:57] [PASSED] Clock 154000 BPP 30 DSC disabled
[21:22:57] [PASSED] Clock 234000 BPP 30 DSC disabled
[21:22:57] [PASSED] Clock 297000 BPP 24 DSC disabled
[21:22:57] [PASSED] Clock 332880 BPP 24 DSC enabled
[21:22:57] [PASSED] Clock 324540 BPP 24 DSC enabled
[21:22:57] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[21:22:57] ============== drm_test_dp_mst_calc_pbn_div  ===============
[21:22:57] [PASSED] Link rate 2000000 lane count 4
[21:22:57] [PASSED] Link rate 2000000 lane count 2
[21:22:57] [PASSED] Link rate 2000000 lane count 1
[21:22:57] [PASSED] Link rate 1350000 lane count 4
[21:22:57] [PASSED] Link rate 1350000 lane count 2
[21:22:57] [PASSED] Link rate 1350000 lane count 1
[21:22:57] [PASSED] Link rate 1000000 lane count 4
[21:22:57] [PASSED] Link rate 1000000 lane count 2
[21:22:57] [PASSED] Link rate 1000000 lane count 1
[21:22:57] [PASSED] Link rate 810000 lane count 4
[21:22:57] [PASSED] Link rate 810000 lane count 2
[21:22:57] [PASSED] Link rate 810000 lane count 1
[21:22:57] [PASSED] Link rate 540000 lane count 4
[21:22:57] [PASSED] Link rate 540000 lane count 2
[21:22:57] [PASSED] Link rate 540000 lane count 1
[21:22:57] [PASSED] Link rate 270000 lane count 4
[21:22:57] [PASSED] Link rate 270000 lane count 2
[21:22:57] [PASSED] Link rate 270000 lane count 1
[21:22:57] [PASSED] Link rate 162000 lane count 4
[21:22:57] [PASSED] Link rate 162000 lane count 2
[21:22:57] [PASSED] Link rate 162000 lane count 1
[21:22:57] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[21:22:57] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[21:22:57] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[21:22:57] [PASSED] DP_POWER_UP_PHY with port number
[21:22:57] [PASSED] DP_POWER_DOWN_PHY with port number
[21:22:57] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[21:22:57] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[21:22:57] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[21:22:57] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[21:22:57] [PASSED] DP_QUERY_PAYLOAD with port number
[21:22:57] [PASSED] DP_QUERY_PAYLOAD with VCPI
[21:22:57] [PASSED] DP_REMOTE_DPCD_READ with port number
[21:22:57] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[21:22:57] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[21:22:57] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[21:22:57] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[21:22:57] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[21:22:57] [PASSED] DP_REMOTE_I2C_READ with port number
[21:22:57] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[21:22:57] [PASSED] DP_REMOTE_I2C_READ with transactions array
[21:22:57] [PASSED] DP_REMOTE_I2C_WRITE with port number
[21:22:57] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[21:22:57] [PASSED] DP_REMOTE_I2C_WRITE with data array
[21:22:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[21:22:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[21:22:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[21:22:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[21:22:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[21:22:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[21:22:57] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[21:22:57] ================ [PASSED] drm_dp_mst_helper ================
[21:22:57] ================== drm_exec (7 subtests) ===================
[21:22:57] [PASSED] sanitycheck
[21:22:57] [PASSED] test_lock
[21:22:57] [PASSED] test_lock_unlock
[21:22:57] [PASSED] test_duplicates
[21:22:57] [PASSED] test_prepare
[21:22:57] [PASSED] test_prepare_array
[21:22:57] [PASSED] test_multiple_loops
[21:22:57] ==================== [PASSED] drm_exec =====================
[21:22:57] =========== drm_format_helper_test (17 subtests) ===========
[21:22:57] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[21:22:57] [PASSED] single_pixel_source_buffer
[21:22:57] [PASSED] single_pixel_clip_rectangle
[21:22:57] [PASSED] well_known_colors
[21:22:57] [PASSED] destination_pitch
[21:22:57] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[21:22:57] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[21:22:57] [PASSED] single_pixel_source_buffer
[21:22:57] [PASSED] single_pixel_clip_rectangle
[21:22:57] [PASSED] well_known_colors
[21:22:57] [PASSED] destination_pitch
[21:22:57] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[21:22:57] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[21:22:57] [PASSED] single_pixel_source_buffer
[21:22:57] [PASSED] single_pixel_clip_rectangle
[21:22:57] [PASSED] well_known_colors
[21:22:57] [PASSED] destination_pitch
[21:22:57] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[21:22:57] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[21:22:57] [PASSED] single_pixel_source_buffer
[21:22:57] [PASSED] single_pixel_clip_rectangle
[21:22:57] [PASSED] well_known_colors
[21:22:57] [PASSED] destination_pitch
[21:22:57] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[21:22:57] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[21:22:57] [PASSED] single_pixel_source_buffer
[21:22:57] [PASSED] single_pixel_clip_rectangle
[21:22:57] [PASSED] well_known_colors
[21:22:57] [PASSED] destination_pitch
[21:22:57] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[21:22:57] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[21:22:57] [PASSED] single_pixel_source_buffer
[21:22:57] [PASSED] single_pixel_clip_rectangle
[21:22:57] [PASSED] well_known_colors
[21:22:57] [PASSED] destination_pitch
[21:22:57] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[21:22:57] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[21:22:57] [PASSED] single_pixel_source_buffer
[21:22:57] [PASSED] single_pixel_clip_rectangle
[21:22:57] [PASSED] well_known_colors
[21:22:57] [PASSED] destination_pitch
[21:22:57] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[21:22:57] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[21:22:57] [PASSED] single_pixel_source_buffer
[21:22:57] [PASSED] single_pixel_clip_rectangle
[21:22:57] [PASSED] well_known_colors
[21:22:57] [PASSED] destination_pitch
[21:22:57] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[21:22:57] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[21:22:57] [PASSED] single_pixel_source_buffer
[21:22:57] [PASSED] single_pixel_clip_rectangle
[21:22:57] [PASSED] well_known_colors
[21:22:57] [PASSED] destination_pitch
[21:22:57] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[21:22:57] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[21:22:57] [PASSED] single_pixel_source_buffer
[21:22:57] [PASSED] single_pixel_clip_rectangle
[21:22:57] [PASSED] well_known_colors
[21:22:57] [PASSED] destination_pitch
[21:22:57] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[21:22:57] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[21:22:57] [PASSED] single_pixel_source_buffer
[21:22:57] [PASSED] single_pixel_clip_rectangle
[21:22:57] [PASSED] well_known_colors
[21:22:57] [PASSED] destination_pitch
[21:22:57] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[21:22:57] ============== drm_test_fb_xrgb8888_to_mono  ===============
[21:22:57] [PASSED] single_pixel_source_buffer
[21:22:57] [PASSED] single_pixel_clip_rectangle
[21:22:57] [PASSED] well_known_colors
[21:22:57] [PASSED] destination_pitch
[21:22:57] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[21:22:57] ==================== drm_test_fb_swab  =====================
[21:22:57] [PASSED] single_pixel_source_buffer
[21:22:57] [PASSED] single_pixel_clip_rectangle
[21:22:57] [PASSED] well_known_colors
[21:22:57] [PASSED] destination_pitch
[21:22:57] ================ [PASSED] drm_test_fb_swab =================
[21:22:57] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[21:22:57] [PASSED] single_pixel_source_buffer
[21:22:57] [PASSED] single_pixel_clip_rectangle
[21:22:57] [PASSED] well_known_colors
[21:22:57] [PASSED] destination_pitch
[21:22:57] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[21:22:57] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[21:22:57] [PASSED] single_pixel_source_buffer
[21:22:57] [PASSED] single_pixel_clip_rectangle
[21:22:57] [PASSED] well_known_colors
[21:22:57] [PASSED] destination_pitch
[21:22:57] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[21:22:57] ================= drm_test_fb_clip_offset  =================
[21:22:57] [PASSED] pass through
[21:22:57] [PASSED] horizontal offset
[21:22:57] [PASSED] vertical offset
[21:22:57] [PASSED] horizontal and vertical offset
[21:22:57] [PASSED] horizontal offset (custom pitch)
[21:22:57] [PASSED] vertical offset (custom pitch)
[21:22:57] [PASSED] horizontal and vertical offset (custom pitch)
[21:22:57] ============= [PASSED] drm_test_fb_clip_offset =============
[21:22:57] =================== drm_test_fb_memcpy  ====================
[21:22:57] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[21:22:57] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[21:22:57] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[21:22:57] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[21:22:57] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[21:22:57] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[21:22:57] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[21:22:57] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[21:22:57] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[21:22:57] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[21:22:57] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[21:22:57] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[21:22:57] =============== [PASSED] drm_test_fb_memcpy ================
[21:22:57] ============= [PASSED] drm_format_helper_test ==============
[21:22:57] ================= drm_format (18 subtests) =================
[21:22:57] [PASSED] drm_test_format_block_width_invalid
[21:22:57] [PASSED] drm_test_format_block_width_one_plane
[21:22:57] [PASSED] drm_test_format_block_width_two_plane
[21:22:57] [PASSED] drm_test_format_block_width_three_plane
[21:22:57] [PASSED] drm_test_format_block_width_tiled
[21:22:57] [PASSED] drm_test_format_block_height_invalid
[21:22:57] [PASSED] drm_test_format_block_height_one_plane
[21:22:57] [PASSED] drm_test_format_block_height_two_plane
[21:22:57] [PASSED] drm_test_format_block_height_three_plane
[21:22:57] [PASSED] drm_test_format_block_height_tiled
[21:22:57] [PASSED] drm_test_format_min_pitch_invalid
[21:22:57] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[21:22:57] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[21:22:57] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[21:22:57] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[21:22:57] [PASSED] drm_test_format_min_pitch_two_plane
[21:22:57] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[21:22:57] [PASSED] drm_test_format_min_pitch_tiled
[21:22:57] =================== [PASSED] drm_format ====================
[21:22:57] ============== drm_framebuffer (10 subtests) ===============
[21:22:57] ========== drm_test_framebuffer_check_src_coords  ==========
[21:22:57] [PASSED] Success: source fits into fb
[21:22:57] [PASSED] Fail: overflowing fb with x-axis coordinate
[21:22:57] [PASSED] Fail: overflowing fb with y-axis coordinate
[21:22:57] [PASSED] Fail: overflowing fb with source width
[21:22:57] [PASSED] Fail: overflowing fb with source height
[21:22:57] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[21:22:57] [PASSED] drm_test_framebuffer_cleanup
[21:22:57] =============== drm_test_framebuffer_create  ===============
[21:22:57] [PASSED] ABGR8888 normal sizes
[21:22:57] [PASSED] ABGR8888 max sizes
[21:22:57] [PASSED] ABGR8888 pitch greater than min required
[21:22:57] [PASSED] ABGR8888 pitch less than min required
[21:22:57] [PASSED] ABGR8888 Invalid width
[21:22:57] [PASSED] ABGR8888 Invalid buffer handle
[21:22:57] [PASSED] No pixel format
[21:22:57] [PASSED] ABGR8888 Width 0
[21:22:57] [PASSED] ABGR8888 Height 0
[21:22:57] [PASSED] ABGR8888 Out of bound height * pitch combination
[21:22:57] [PASSED] ABGR8888 Large buffer offset
[21:22:57] [PASSED] ABGR8888 Buffer offset for inexistent plane
[21:22:57] [PASSED] ABGR8888 Invalid flag
[21:22:57] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[21:22:57] [PASSED] ABGR8888 Valid buffer modifier
[21:22:57] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[21:22:57] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[21:22:57] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[21:22:57] [PASSED] NV12 Normal sizes
[21:22:57] [PASSED] NV12 Max sizes
[21:22:57] [PASSED] NV12 Invalid pitch
[21:22:57] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[21:22:57] [PASSED] NV12 different  modifier per-plane
[21:22:57] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[21:22:57] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[21:22:57] [PASSED] NV12 Modifier for inexistent plane
[21:22:57] [PASSED] NV12 Handle for inexistent plane
[21:22:57] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[21:22:57] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[21:22:57] [PASSED] YVU420 Normal sizes
[21:22:57] [PASSED] YVU420 Max sizes
[21:22:57] [PASSED] YVU420 Invalid pitch
[21:22:57] [PASSED] YVU420 Different pitches
[21:22:57] [PASSED] YVU420 Different buffer offsets/pitches
[21:22:57] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[21:22:57] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[21:22:57] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[21:22:57] [PASSED] YVU420 Valid modifier
[21:22:57] [PASSED] YVU420 Different modifiers per plane
[21:22:57] [PASSED] YVU420 Modifier for inexistent plane
[21:22:57] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[21:22:57] [PASSED] X0L2 Normal sizes
[21:22:57] [PASSED] X0L2 Max sizes
[21:22:57] [PASSED] X0L2 Invalid pitch
[21:22:57] [PASSED] X0L2 Pitch greater than minimum required
[21:22:57] [PASSED] X0L2 Handle for inexistent plane
[21:22:57] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[21:22:57] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[21:22:57] [PASSED] X0L2 Valid modifier
[21:22:57] [PASSED] X0L2 Modifier for inexistent plane
[21:22:57] =========== [PASSED] drm_test_framebuffer_create ===========
[21:22:57] [PASSED] drm_test_framebuffer_free
[21:22:57] [PASSED] drm_test_framebuffer_init
[21:22:57] [PASSED] drm_test_framebuffer_init_bad_format
[21:22:57] [PASSED] drm_test_framebuffer_init_dev_mismatch
[21:22:57] [PASSED] drm_test_framebuffer_lookup
[21:22:57] [PASSED] drm_test_framebuffer_lookup_inexistent
[21:22:57] [PASSED] drm_test_framebuffer_modifiers_not_supported
[21:22:57] ================= [PASSED] drm_framebuffer =================
[21:22:57] ================ drm_gem_shmem (8 subtests) ================
[21:22:57] [PASSED] drm_gem_shmem_test_obj_create
[21:22:57] [PASSED] drm_gem_shmem_test_obj_create_private
[21:22:57] [PASSED] drm_gem_shmem_test_pin_pages
[21:22:57] [PASSED] drm_gem_shmem_test_vmap
[21:22:57] [PASSED] drm_gem_shmem_test_get_pages_sgt
[21:22:57] [PASSED] drm_gem_shmem_test_get_sg_table
[21:22:57] [PASSED] drm_gem_shmem_test_madvise
[21:22:57] [PASSED] drm_gem_shmem_test_purge
[21:22:57] ================== [PASSED] drm_gem_shmem ==================
[21:22:57] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[21:22:57] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[21:22:57] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[21:22:57] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[21:22:57] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[21:22:57] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[21:22:57] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[21:22:57] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[21:22:57] [PASSED] Automatic
[21:22:57] [PASSED] Full
[21:22:57] [PASSED] Limited 16:235
[21:22:57] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[21:22:57] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[21:22:57] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[21:22:57] [PASSED] drm_test_check_disable_connector
[21:22:57] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[21:22:57] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[21:22:57] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[21:22:57] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[21:22:57] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[21:22:57] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[21:22:57] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[21:22:57] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[21:22:57] [PASSED] drm_test_check_output_bpc_dvi
[21:22:57] [PASSED] drm_test_check_output_bpc_format_vic_1
[21:22:57] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[21:22:57] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[21:22:57] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[21:22:57] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[21:22:57] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[21:22:57] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[21:22:57] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[21:22:57] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[21:22:57] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[21:22:57] [PASSED] drm_test_check_broadcast_rgb_value
[21:22:57] [PASSED] drm_test_check_bpc_8_value
[21:22:57] [PASSED] drm_test_check_bpc_10_value
[21:22:57] [PASSED] drm_test_check_bpc_12_value
[21:22:57] [PASSED] drm_test_check_format_value
[21:22:57] [PASSED] drm_test_check_tmds_char_value
[21:22:57] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[21:22:57] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[21:22:57] [PASSED] drm_test_check_mode_valid
[21:22:57] [PASSED] drm_test_check_mode_valid_reject
[21:22:57] [PASSED] drm_test_check_mode_valid_reject_rate
[21:22:57] [PASSED] drm_test_check_mode_valid_reject_max_clock
[21:22:57] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[21:22:57] ================= drm_managed (2 subtests) =================
[21:22:57] [PASSED] drm_test_managed_release_action
[21:22:57] [PASSED] drm_test_managed_run_action
[21:22:57] =================== [PASSED] drm_managed ===================
[21:22:57] =================== drm_mm (6 subtests) ====================
[21:22:57] [PASSED] drm_test_mm_init
[21:22:57] [PASSED] drm_test_mm_debug
[21:22:57] [PASSED] drm_test_mm_align32
[21:22:57] [PASSED] drm_test_mm_align64
[21:22:57] [PASSED] drm_test_mm_lowest
[21:22:57] [PASSED] drm_test_mm_highest
[21:22:57] ===================== [PASSED] drm_mm ======================
[21:22:57] ============= drm_modes_analog_tv (5 subtests) =============
[21:22:57] [PASSED] drm_test_modes_analog_tv_mono_576i
[21:22:57] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[21:22:57] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[21:22:57] [PASSED] drm_test_modes_analog_tv_pal_576i
[21:22:57] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[21:22:57] =============== [PASSED] drm_modes_analog_tv ===============
[21:22:57] ============== drm_plane_helper (2 subtests) ===============
[21:22:57] =============== drm_test_check_plane_state  ================
[21:22:57] [PASSED] clipping_simple
[21:22:57] [PASSED] clipping_rotate_reflect
[21:22:57] [PASSED] positioning_simple
[21:22:57] [PASSED] upscaling
[21:22:57] [PASSED] downscaling
[21:22:57] [PASSED] rounding1
[21:22:57] [PASSED] rounding2
[21:22:57] [PASSED] rounding3
[21:22:57] [PASSED] rounding4
[21:22:57] =========== [PASSED] drm_test_check_plane_state ============
[21:22:57] =========== drm_test_check_invalid_plane_state  ============
[21:22:57] [PASSED] positioning_invalid
[21:22:57] [PASSED] upscaling_invalid
[21:22:57] [PASSED] downscaling_invalid
[21:22:57] ======= [PASSED] drm_test_check_invalid_plane_state ========
[21:22:57] ================ [PASSED] drm_plane_helper =================
[21:22:57] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[21:22:57] ====== drm_test_connector_helper_tv_get_modes_check  =======
[21:22:57] [PASSED] None
[21:22:57] [PASSED] PAL
[21:22:57] [PASSED] NTSC
[21:22:57] [PASSED] Both, NTSC Default
[21:22:57] [PASSED] Both, PAL Default
[21:22:57] [PASSED] Both, NTSC Default, with PAL on command-line
[21:22:57] [PASSED] Both, PAL Default, with NTSC on command-line
[21:22:57] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[21:22:57] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[21:22:57] ================== drm_rect (9 subtests) ===================
[21:22:57] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[21:22:57] [PASSED] drm_test_rect_clip_scaled_not_clipped
[21:22:57] [PASSED] drm_test_rect_clip_scaled_clipped
[21:22:57] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[21:22:57] ================= drm_test_rect_intersect  =================
[21:22:57] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[21:22:57] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[21:22:57] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[21:22:57] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[21:22:57] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[21:22:57] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[21:22:57] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[21:22:57] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[21:22:57] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[21:22:57] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[21:22:57] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[21:22:57] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[21:22:57] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[21:22:57] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[21:22:57] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[21:22:57] ============= [PASSED] drm_test_rect_intersect =============
[21:22:57] ================ drm_test_rect_calc_hscale  ================
[21:22:57] [PASSED] normal use
[21:22:57] [PASSED] out of max range
[21:22:57] [PASSED] out of min range
[21:22:57] [PASSED] zero dst
[21:22:57] [PASSED] negative src
[21:22:57] [PASSED] negative dst
[21:22:57] ============ [PASSED] drm_test_rect_calc_hscale ============
[21:22:57] ================ drm_test_rect_calc_vscale  ================
[21:22:57] [PASSED] normal use
[21:22:57] [PASSED] out of max range
[21:22:57] [PASSED] out of min range
[21:22:57] [PASSED] zero dst
[21:22:57] [PASSED] negative src
stty: 'standard input': Inappropriate ioctl for device
[21:22:57] [PASSED] negative dst
[21:22:57] ============ [PASSED] drm_test_rect_calc_vscale ============
[21:22:57] ================== drm_test_rect_rotate  ===================
[21:22:57] [PASSED] reflect-x
[21:22:57] [PASSED] reflect-y
[21:22:57] [PASSED] rotate-0
[21:22:57] [PASSED] rotate-90
[21:22:57] [PASSED] rotate-180
[21:22:57] [PASSED] rotate-270
[21:22:57] ============== [PASSED] drm_test_rect_rotate ===============
[21:22:57] ================ drm_test_rect_rotate_inv  =================
[21:22:57] [PASSED] reflect-x
[21:22:57] [PASSED] reflect-y
[21:22:57] [PASSED] rotate-0
[21:22:57] [PASSED] rotate-90
[21:22:57] [PASSED] rotate-180
[21:22:57] [PASSED] rotate-270
[21:22:57] ============ [PASSED] drm_test_rect_rotate_inv =============
[21:22:57] ==================== [PASSED] drm_rect =====================
[21:22:57] ============ drm_sysfb_modeset_test (1 subtest) ============
[21:22:57] ============ drm_test_sysfb_build_fourcc_list  =============
[21:22:57] [PASSED] no native formats
[21:22:57] [PASSED] XRGB8888 as native format
[21:22:57] [PASSED] remove duplicates
[21:22:57] [PASSED] convert alpha formats
[21:22:57] [PASSED] random formats
[21:22:57] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[21:22:57] ============= [PASSED] drm_sysfb_modeset_test ==============
[21:22:57] ============================================================
[21:22:57] Testing complete. Ran 621 tests: passed: 621
[21:22:57] Elapsed time: 30.262s total, 1.681s configuring, 28.414s building, 0.146s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[21:22:57] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:22:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[21:23:08] Starting KUnit Kernel (1/1)...
[21:23:08] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:23:08] ================= ttm_device (5 subtests) ==================
[21:23:08] [PASSED] ttm_device_init_basic
[21:23:08] [PASSED] ttm_device_init_multiple
[21:23:08] [PASSED] ttm_device_fini_basic
[21:23:08] [PASSED] ttm_device_init_no_vma_man
[21:23:08] ================== ttm_device_init_pools  ==================
[21:23:08] [PASSED] No DMA allocations, no DMA32 required
[21:23:08] [PASSED] DMA allocations, DMA32 required
[21:23:08] [PASSED] No DMA allocations, DMA32 required
[21:23:08] [PASSED] DMA allocations, no DMA32 required
[21:23:08] ============== [PASSED] ttm_device_init_pools ==============
[21:23:08] =================== [PASSED] ttm_device ====================
[21:23:08] ================== ttm_pool (8 subtests) ===================
[21:23:08] ================== ttm_pool_alloc_basic  ===================
[21:23:08] [PASSED] One page
[21:23:08] [PASSED] More than one page
[21:23:08] [PASSED] Above the allocation limit
[21:23:08] [PASSED] One page, with coherent DMA mappings enabled
[21:23:08] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:23:08] ============== [PASSED] ttm_pool_alloc_basic ===============
[21:23:08] ============== ttm_pool_alloc_basic_dma_addr  ==============
[21:23:08] [PASSED] One page
[21:23:08] [PASSED] More than one page
[21:23:08] [PASSED] Above the allocation limit
[21:23:08] [PASSED] One page, with coherent DMA mappings enabled
[21:23:08] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:23:08] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[21:23:08] [PASSED] ttm_pool_alloc_order_caching_match
[21:23:08] [PASSED] ttm_pool_alloc_caching_mismatch
[21:23:08] [PASSED] ttm_pool_alloc_order_mismatch
[21:23:08] [PASSED] ttm_pool_free_dma_alloc
[21:23:08] [PASSED] ttm_pool_free_no_dma_alloc
[21:23:08] [PASSED] ttm_pool_fini_basic
[21:23:08] ==================== [PASSED] ttm_pool =====================
[21:23:08] ================ ttm_resource (8 subtests) =================
[21:23:08] ================= ttm_resource_init_basic  =================
[21:23:08] [PASSED] Init resource in TTM_PL_SYSTEM
[21:23:08] [PASSED] Init resource in TTM_PL_VRAM
[21:23:08] [PASSED] Init resource in a private placement
[21:23:08] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[21:23:08] ============= [PASSED] ttm_resource_init_basic =============
[21:23:08] [PASSED] ttm_resource_init_pinned
[21:23:08] [PASSED] ttm_resource_fini_basic
[21:23:08] [PASSED] ttm_resource_manager_init_basic
[21:23:08] [PASSED] ttm_resource_manager_usage_basic
[21:23:08] [PASSED] ttm_resource_manager_set_used_basic
[21:23:08] [PASSED] ttm_sys_man_alloc_basic
[21:23:08] [PASSED] ttm_sys_man_free_basic
[21:23:08] ================== [PASSED] ttm_resource ===================
[21:23:08] =================== ttm_tt (15 subtests) ===================
[21:23:08] ==================== ttm_tt_init_basic  ====================
[21:23:08] [PASSED] Page-aligned size
[21:23:08] [PASSED] Extra pages requested
[21:23:08] ================ [PASSED] ttm_tt_init_basic ================
[21:23:08] [PASSED] ttm_tt_init_misaligned
[21:23:08] [PASSED] ttm_tt_fini_basic
[21:23:08] [PASSED] ttm_tt_fini_sg
[21:23:08] [PASSED] ttm_tt_fini_shmem
[21:23:08] [PASSED] ttm_tt_create_basic
[21:23:08] [PASSED] ttm_tt_create_invalid_bo_type
[21:23:08] [PASSED] ttm_tt_create_ttm_exists
[21:23:08] [PASSED] ttm_tt_create_failed
[21:23:08] [PASSED] ttm_tt_destroy_basic
[21:23:08] [PASSED] ttm_tt_populate_null_ttm
[21:23:08] [PASSED] ttm_tt_populate_populated_ttm
[21:23:08] [PASSED] ttm_tt_unpopulate_basic
[21:23:08] [PASSED] ttm_tt_unpopulate_empty_ttm
[21:23:08] [PASSED] ttm_tt_swapin_basic
[21:23:08] ===================== [PASSED] ttm_tt ======================
[21:23:08] =================== ttm_bo (14 subtests) ===================
[21:23:08] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[21:23:08] [PASSED] Cannot be interrupted and sleeps
[21:23:08] [PASSED] Cannot be interrupted, locks straight away
[21:23:08] [PASSED] Can be interrupted, sleeps
[21:23:08] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[21:23:08] [PASSED] ttm_bo_reserve_locked_no_sleep
[21:23:08] [PASSED] ttm_bo_reserve_no_wait_ticket
[21:23:08] [PASSED] ttm_bo_reserve_double_resv
[21:23:08] [PASSED] ttm_bo_reserve_interrupted
[21:23:08] [PASSED] ttm_bo_reserve_deadlock
[21:23:08] [PASSED] ttm_bo_unreserve_basic
[21:23:08] [PASSED] ttm_bo_unreserve_pinned
[21:23:08] [PASSED] ttm_bo_unreserve_bulk
[21:23:08] [PASSED] ttm_bo_put_basic
[21:23:08] [PASSED] ttm_bo_put_shared_resv
[21:23:08] [PASSED] ttm_bo_pin_basic
[21:23:08] [PASSED] ttm_bo_pin_unpin_resource
[21:23:08] [PASSED] ttm_bo_multiple_pin_one_unpin
[21:23:08] ===================== [PASSED] ttm_bo ======================
[21:23:08] ============== ttm_bo_validate (21 subtests) ===============
[21:23:08] ============== ttm_bo_init_reserved_sys_man  ===============
[21:23:08] [PASSED] Buffer object for userspace
[21:23:08] [PASSED] Kernel buffer object
[21:23:08] [PASSED] Shared buffer object
[21:23:08] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[21:23:08] ============== ttm_bo_init_reserved_mock_man  ==============
[21:23:08] [PASSED] Buffer object for userspace
[21:23:08] [PASSED] Kernel buffer object
[21:23:08] [PASSED] Shared buffer object
[21:23:08] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[21:23:08] [PASSED] ttm_bo_init_reserved_resv
[21:23:08] ================== ttm_bo_validate_basic  ==================
[21:23:08] [PASSED] Buffer object for userspace
[21:23:08] [PASSED] Kernel buffer object
[21:23:08] [PASSED] Shared buffer object
[21:23:08] ============== [PASSED] ttm_bo_validate_basic ==============
[21:23:08] [PASSED] ttm_bo_validate_invalid_placement
[21:23:08] ============= ttm_bo_validate_same_placement  ==============
[21:23:08] [PASSED] System manager
[21:23:08] [PASSED] VRAM manager
[21:23:08] ========= [PASSED] ttm_bo_validate_same_placement ==========
[21:23:08] [PASSED] ttm_bo_validate_failed_alloc
[21:23:08] [PASSED] ttm_bo_validate_pinned
[21:23:08] [PASSED] ttm_bo_validate_busy_placement
[21:23:08] ================ ttm_bo_validate_multihop  =================
[21:23:08] [PASSED] Buffer object for userspace
[21:23:08] [PASSED] Kernel buffer object
[21:23:08] [PASSED] Shared buffer object
[21:23:08] ============ [PASSED] ttm_bo_validate_multihop =============
[21:23:08] ========== ttm_bo_validate_no_placement_signaled  ==========
[21:23:08] [PASSED] Buffer object in system domain, no page vector
[21:23:08] [PASSED] Buffer object in system domain with an existing page vector
[21:23:08] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[21:23:08] ======== ttm_bo_validate_no_placement_not_signaled  ========
[21:23:08] [PASSED] Buffer object for userspace
[21:23:08] [PASSED] Kernel buffer object
[21:23:08] [PASSED] Shared buffer object
[21:23:08] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[21:23:08] [PASSED] ttm_bo_validate_move_fence_signaled
[21:23:09] ========= ttm_bo_validate_move_fence_not_signaled  =========
[21:23:09] [PASSED] Waits for GPU
[21:23:09] [PASSED] Tries to lock straight away
[21:23:09] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[21:23:09] [PASSED] ttm_bo_validate_happy_evict
[21:23:09] [PASSED] ttm_bo_validate_all_pinned_evict
[21:23:09] [PASSED] ttm_bo_validate_allowed_only_evict
[21:23:09] [PASSED] ttm_bo_validate_deleted_evict
[21:23:09] [PASSED] ttm_bo_validate_busy_domain_evict
[21:23:09] [PASSED] ttm_bo_validate_evict_gutting
[21:23:09] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[21:23:09] ================= [PASSED] ttm_bo_validate =================
[21:23:09] ============================================================
[21:23:09] Testing complete. Ran 101 tests: passed: 101
[21:23:09] Elapsed time: 11.619s total, 1.683s configuring, 9.670s building, 0.227s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe: Add user commands to WA BB via configfs

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1449 bytes --]

== Series Details ==

Series: drm/xe: Add user commands to WA BB via configfs
URL   : https://patchwork.freedesktop.org/series/154618/
State : success

== Summary ==

CI Bug Log - changes from xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93_BAT -> xe-pw-154618v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-154618v1_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@xe_pat@pat-index-xe2@render:
    - bat-bmg-2:          [FAIL][1] ([Intel XE#5507]) -> [PASS][2] +1 other test pass
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/bat-bmg-2/igt@xe_pat@pat-index-xe2@render.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/bat-bmg-2/igt@xe_pat@pat-index-xe2@render.html

  
  [Intel XE#5507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5507


Build changes
-------------

  * Linux: xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93 -> xe-pw-154618v1

  IGT_8541: 8541
  xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93: c3610fc0ab7c1c668031b3804549187d75550e93
  xe-pw-154618v1: 154618v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/index.html

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✗ Xe.CI.Full: failure for drm/xe: Add user commands to WA BB via configfs

[Patchwork]

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== Series Details ==

Series: drm/xe: Add user commands to WA BB via configfs
URL   : https://patchwork.freedesktop.org/series/154618/
State : failure

== Summary ==

CI Bug Log - changes from xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93_FULL -> xe-pw-154618v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-154618v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-154618v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-154618v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-6.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-6.html

  * igt@xe_create@create-contexts:
    - shard-adlp:         [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-adlp-8/igt@xe_create@create-contexts.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-adlp-4/igt@xe_create@create-contexts.html

  
#### Warnings ####

  * igt@xe_exec_basic@multigpu-no-exec-userptr:
    - shard-adlp:         [SKIP][5] ([Intel XE#1392] / [Intel XE#5575]) -> [DMESG-WARN][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-adlp-3/igt@xe_exec_basic@multigpu-no-exec-userptr.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-adlp-9/igt@xe_exec_basic@multigpu-no-exec-userptr.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-adlp:         [SKIP][7] ([Intel XE#944]) -> [FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-adlp-8/igt@xe_query@multigpu-query-uc-fw-version-huc.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-adlp-4/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  
Known issues
------------

  Here are the changes found in xe-pw-154618v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@test-cursor-atomic:
    - shard-adlp:         [PASS][9] -> [DMESG-WARN][10] ([Intel XE#2953] / [Intel XE#4173]) +2 other tests dmesg-warn
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-adlp-4/igt@kms_async_flips@test-cursor-atomic.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-adlp-1/igt@kms_async_flips@test-cursor-atomic.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-0:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#1124])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-adlp:         [PASS][12] -> [DMESG-FAIL][13] ([Intel XE#4543])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-adlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-adlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#1124])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-432/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
    - shard-bmg:          [PASS][15] -> [SKIP][16] ([Intel XE#2314] / [Intel XE#2894])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-8/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-8/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#2887]) +1 other test skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][19] ([Intel XE#787]) +76 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-432/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [PASS][20] -> [INCOMPLETE][21] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-dp-4:
    - shard-dg2-set2:     [PASS][22] -> [DMESG-WARN][23] ([Intel XE#1727] / [Intel XE#3113])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-dp-4.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-dp-4.html

  * igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-d-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][24] ([Intel XE#455] / [Intel XE#787]) +13 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-432/igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-d-dp-2.html

  * igt@kms_chamelium_frames@hdmi-crc-multiple:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#373])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_chamelium_frames@hdmi-crc-multiple.html

  * igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
    - shard-dg2-set2:     NOTRUN -> [SKIP][26] ([Intel XE#373])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-432/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html

  * igt@kms_content_protection@atomic@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][27] ([Intel XE#1178]) +1 other test fail
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-3/igt@kms_content_protection@atomic@pipe-a-dp-2.html

  * igt@kms_content_protection@uevent@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][28] ([Intel XE#1188])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-8/igt@kms_content_protection@uevent@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-dg2-set2:     NOTRUN -> [SKIP][29] ([Intel XE#308])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-432/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-128x42:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#1424])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_cursor_crc@cursor-random-128x42.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#2321])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-64x21:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#2320])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-7/igt@kms_cursor_crc@cursor-sliding-64x21.html

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-bmg:          [PASS][33] -> [SKIP][34] ([Intel XE#2291]) +2 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-8/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-6/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#309])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-bmg:          [PASS][36] -> [SKIP][37] ([Intel XE#1340])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#4354])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#1421]) +1 other test skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop:
    - shard-bmg:          [PASS][40] -> [SKIP][41] ([Intel XE#2316]) +3 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-2/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop.html

  * igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1:
    - shard-adlp:         [PASS][42] -> [DMESG-WARN][43] ([Intel XE#4543]) +2 other tests dmesg-warn
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-adlp-8/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-adlp-8/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          NOTRUN -> [FAIL][44] ([Intel XE#301]) +1 other test fail
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@wf_vblank-ts-check:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][45] ([Intel XE#2049]) +1 other test incomplete
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-463/igt@kms_flip@wf_vblank-ts-check.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#1401] / [Intel XE#1745])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][47] ([Intel XE#1401])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-msflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#651]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen:
    - shard-dg2-set2:     NOTRUN -> [SKIP][49] ([Intel XE#651]) +3 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#656]) +9 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#1469])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#2311]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#2313]) +4 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][54] ([Intel XE#653]) +4 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#4298])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_psr2_sf@pr-cursor-plane-update-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][56] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-435/igt@kms_psr2_sf@pr-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#1406] / [Intel XE#2893])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#1128] / [Intel XE#1406])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-psr2-sprite-plane-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-7/igt@kms_psr@fbc-psr2-sprite-plane-onoff.html

  * igt@kms_psr@pr-sprite-plane-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#1406])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_psr@pr-sprite-plane-onoff.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-bmg:          NOTRUN -> [SKIP][61] ([Intel XE#1406] / [Intel XE#2414])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-dg2-set2:     NOTRUN -> [SKIP][62] ([Intel XE#1127])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-432/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#3414] / [Intel XE#3904])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_vrr@negative-basic:
    - shard-bmg:          [PASS][64] -> [SKIP][65] ([Intel XE#1499])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-2/igt@kms_vrr@negative-basic.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-6/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][66] ([Intel XE#455])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-432/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@xe_copy_basic@mem-copy-linear-0x3fff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][67] ([Intel XE#1123])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-432/igt@xe_copy_basic@mem-copy-linear-0x3fff.html

  * igt@xe_eudebug@basic-client:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#4837]) +2 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@xe_eudebug@basic-client.html

  * igt@xe_eudebug@basic-vm-access-faultable:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#4837]) +2 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-7/igt@xe_eudebug@basic-vm-access-faultable.html

  * igt@xe_eudebug@multigpu-basic-client-many:
    - shard-dg2-set2:     NOTRUN -> [SKIP][70] ([Intel XE#4837])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-432/igt@xe_eudebug@multigpu-basic-client-many.html

  * igt@xe_evict@evict-large:
    - shard-lnl:          NOTRUN -> [SKIP][71] ([Intel XE#688])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@xe_evict@evict-large.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][72] ([Intel XE#1392])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html

  * igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#2322])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-7/igt@xe_exec_basic@multigpu-no-exec-basic-defer-mmap.html

  * igt@xe_exec_basic@multigpu-no-exec-rebind:
    - shard-dg2-set2:     [PASS][74] -> [SKIP][75] ([Intel XE#1392]) +2 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-dg2-466/igt@xe_exec_basic@multigpu-no-exec-rebind.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-rebind.html

  * igt@xe_exec_basic@multigpu-once-null:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#1392]) +1 other test skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@xe_exec_basic@multigpu-once-null.html

  * igt@xe_exec_fault_mode@twice-basic-prefetch:
    - shard-dg2-set2:     NOTRUN -> [SKIP][77] ([Intel XE#288]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-432/igt@xe_exec_fault_mode@twice-basic-prefetch.html

  * igt@xe_exec_system_allocator@twice-large-mmap-new-huge:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#4943]) +1 other test skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-7/igt@xe_exec_system_allocator@twice-large-mmap-new-huge.html

  * igt@xe_exec_system_allocator@twice-malloc-fork-read:
    - shard-dg2-set2:     NOTRUN -> [SKIP][79] ([Intel XE#4915]) +37 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-435/igt@xe_exec_system_allocator@twice-malloc-fork-read.html

  * igt@xe_exec_system_allocator@twice-mmap-new-huge-nomemset:
    - shard-lnl:          NOTRUN -> [SKIP][80] ([Intel XE#4943]) +4 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@xe_exec_system_allocator@twice-mmap-new-huge-nomemset.html

  * igt@xe_mmap@pci-membarrier-parallel:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#5100])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@xe_mmap@pci-membarrier-parallel.html

  * igt@xe_pm@s2idle-vm-bind-prefetch:
    - shard-adlp:         [PASS][82] -> [INCOMPLETE][83] ([Intel XE#4504])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-adlp-3/igt@xe_pm@s2idle-vm-bind-prefetch.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-adlp-9/igt@xe_pm@s2idle-vm-bind-prefetch.html

  * igt@xe_pm@s4-d3cold-basic-exec:
    - shard-dg2-set2:     NOTRUN -> [SKIP][84] ([Intel XE#2284] / [Intel XE#366])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-463/igt@xe_pm@s4-d3cold-basic-exec.html

  * igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_render0:
    - shard-adlp:         [PASS][85] -> [TIMEOUT][86] ([Intel XE#5213]) +1 other test timeout
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-adlp-3/igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_render0.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-adlp-9/igt@xe_pmu@all-fn-engine-activity-load@engine-drm_xe_engine_class_render0.html

  * igt@xe_pmu@fn-engine-activity-sched-if-idle:
    - shard-dg2-set2:     NOTRUN -> [SKIP][87] ([Intel XE#4650])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-435/igt@xe_pmu@fn-engine-activity-sched-if-idle.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq:
    - shard-dg2-set2:     NOTRUN -> [SKIP][88] ([Intel XE#4733])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-435/igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq.html

  * igt@xe_query@multigpu-query-gt-list:
    - shard-dg2-set2:     NOTRUN -> [SKIP][89] ([Intel XE#944]) +1 other test skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-435/igt@xe_query@multigpu-query-gt-list.html

  * igt@xe_sriov_scheduling@equal-throughput:
    - shard-adlp:         [PASS][90] -> [DMESG-FAIL][91] ([Intel XE#5213]) +1 other test dmesg-fail
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-adlp-8/igt@xe_sriov_scheduling@equal-throughput.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-adlp-4/igt@xe_sriov_scheduling@equal-throughput.html

  
#### Possible fixes ####

  * igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1:
    - shard-adlp:         [FAIL][92] ([Intel XE#3884]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-adlp-4/igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-adlp-8/igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-180:
    - shard-lnl:          [INCOMPLETE][94] ([Intel XE#5643]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-lnl-2/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-2/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][96] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
    - shard-bmg:          [SKIP][98] ([Intel XE#2291]) -> [PASS][99] +2 other tests pass
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html

  * igt@kms_feature_discovery@display-2x:
    - shard-bmg:          [SKIP][100] ([Intel XE#2373]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-6/igt@kms_feature_discovery@display-2x.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-3/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset:
    - shard-bmg:          [SKIP][102] ([Intel XE#2316]) -> [PASS][103] +2 other tests pass
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-3/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
    - shard-lnl:          [FAIL][104] ([Intel XE#3098]) -> [PASS][105] +1 other test pass
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-lnl-7/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-lnl-3/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-adlp:         [DMESG-WARN][106] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][107] +6 other tests pass
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-adlp-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-adlp-1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
    - shard-dg2-set2:     [FAIL][108] ([Intel XE#301]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-dg2-432/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-434/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend@c-dp4:
    - shard-dg2-set2:     [INCOMPLETE][110] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][111] +1 other test pass
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-dg2-435/igt@kms_flip@flip-vs-suspend@c-dp4.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-463/igt@kms_flip@flip-vs-suspend@c-dp4.html

  * igt@kms_flip@flip-vs-wf_vblank-interruptible@c-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][112] ([Intel XE#4543]) -> [PASS][113] +2 other tests pass
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-adlp-8/igt@kms_flip@flip-vs-wf_vblank-interruptible@c-hdmi-a1.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-adlp-4/igt@kms_flip@flip-vs-wf_vblank-interruptible@c-hdmi-a1.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-bmg:          [SKIP][114] ([Intel XE#1503]) -> [PASS][115] +1 other test pass
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-6/igt@kms_hdr@static-toggle-suspend.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-8/igt@kms_hdr@static-toggle-suspend.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-mmap:
    - shard-dg2-set2:     [SKIP][116] ([Intel XE#1392]) -> [PASS][117] +5 other tests pass
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-dg2-432/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-434/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html

  * igt@xe_pmu@fn-engine-activity-load:
    - shard-bmg:          [FAIL][118] ([Intel XE#5937]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-2/igt@xe_pmu@fn-engine-activity-load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-6/igt@xe_pmu@fn-engine-activity-load.html

  * igt@xe_pmu@gt-frequency:
    - shard-dg2-set2:     [FAIL][120] ([Intel XE#4819]) -> [PASS][121] +1 other test pass
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-dg2-432/igt@xe_pmu@gt-frequency.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-466/igt@xe_pmu@gt-frequency.html

  
#### Warnings ####

  * igt@kms_content_protection@atomic:
    - shard-bmg:          [SKIP][122] ([Intel XE#2341]) -> [FAIL][123] ([Intel XE#1178]) +1 other test fail
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-6/igt@kms_content_protection@atomic.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-3/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@lic-type-0:
    - shard-bmg:          [FAIL][124] ([Intel XE#1178]) -> [SKIP][125] ([Intel XE#2341])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-8/igt@kms_content_protection@lic-type-0.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-6/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@uevent:
    - shard-bmg:          [SKIP][126] ([Intel XE#2341]) -> [FAIL][127] ([Intel XE#1188])
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-6/igt@kms_content_protection@uevent.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-8/igt@kms_content_protection@uevent.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-bmg:          [FAIL][128] -> [SKIP][129] ([Intel XE#2316])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-2/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-6/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][130] ([Intel XE#2311]) -> [SKIP][131] ([Intel XE#2312]) +11 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][132] ([Intel XE#2312]) -> [SKIP][133] ([Intel XE#2311]) +8 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][134] ([Intel XE#5390]) -> [SKIP][135] ([Intel XE#2312]) +5 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
    - shard-bmg:          [SKIP][136] ([Intel XE#2312]) -> [SKIP][137] ([Intel XE#5390]) +6 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][138] ([Intel XE#2312]) -> [SKIP][139] ([Intel XE#2313]) +9 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][140] ([Intel XE#2313]) -> [SKIP][141] ([Intel XE#2312]) +9 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][142] ([Intel XE#3544]) -> [SKIP][143] ([Intel XE#3374] / [Intel XE#3544])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][144] ([Intel XE#2426]) -> [SKIP][145] ([Intel XE#2509])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_peer2peer@write:
    - shard-dg2-set2:     [FAIL][146] ([Intel XE#1173]) -> [SKIP][147] ([Intel XE#1061])
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93/shard-dg2-466/igt@xe_peer2peer@write.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/shard-dg2-432/igt@xe_peer2peer@write.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1469]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1469
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
  [Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3884]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3884
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4819
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5503
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5643]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5643
  [Intel XE#5786]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5786
  [Intel XE#5937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5937
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93 -> xe-pw-154618v1

  IGT_8541: 8541
  xe-3776-c3610fc0ab7c1c668031b3804549187d75550e93: c3610fc0ab7c1c668031b3804549187d75550e93
  xe-pw-154618v1: 154618v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-154618v1/index.html

[-- Attachment #2: Type: text/html, Size: 49125 bytes --]

Re: [PATCH v5 0/7] drm/xe: Add user commands to WA BB via configfs

[Raag Jadav]

On Tue, Sep 16, 2025 at 02:15:37PM -0700, Lucas De Marchi wrote:
> Integrate WA BB (aka post context restore bb) with configfs to allow
> validation to experiment with the GPU, executing commands on every
> context switch.
> 
> Setting some registers to experiment:
> 
> 	# echo 0 > /sys/bus/pci/drivers_autoprobe
> 	# modprobe xe
> 	# mkdir  /sys/kernel/config/xe/0000:03:00.0
> 	# cat > /sys/kernel/config/xe/0000\:03\:00.0/ctx_restore_post_bb  <<EOF
> 	bcs cmd 11000001 4F100 cafebabe
> 	vcs cmd 11000001 4F104 0FF1CE
> 	rcs cmd 11000001 4F108 BAADF00D

I know, and I share your pain :D

Raag

Re: [PATCH v5 0/7] drm/xe: Add user commands to WA BB via configfs

[Lucas De Marchi]

On Tue, 16 Sep 2025 14:15:37 -0700, Lucas De Marchi wrote:
> Integrate WA BB (aka post context restore bb) with configfs to allow
> validation to experiment with the GPU, executing commands on every
> context switch.
> 
> Setting some registers to experiment:
> 
> 	# echo 0 > /sys/bus/pci/drivers_autoprobe
> 	# modprobe xe
> 	# mkdir  /sys/kernel/config/xe/0000:03:00.0
> 	# cat > /sys/kernel/config/xe/0000\:03\:00.0/ctx_restore_post_bb  <<EOF
> 	bcs cmd 11000001 4F100 cafebabe
> 	vcs cmd 11000001 4F104 0FF1CE
> 	rcs cmd 11000001 4F108 BAADF00D
> 	EOF
> 	# echo 0000:03:00.0 > /sys/bus/pci/drivers/xe/bind
> 	# intel_reg read mmio:4F100 mmio:4f104 mmio:4f108
>                                     (0x0004f100): 0xcafebabe
>                                     (0x0004f104): 0x000ff1ce
>                                     (0x0004f108): 0xbaadf00d
> 
> [...]

Thanks for the reviews. Merged to drm-xe-next.

[1/7] drm/xe/configfs: Extract function to parse engine
      commit: 7166cc3a6aae9aaa529f52e1468006e67e3e6846
[2/7] drm/xe/configfs: Allow to select by class only
      commit: e2a9854d806e1cb95861a0f3c7125caaefd7ef03
[3/7] drm/xe/lrc: Allow to add user commands on context switch
      commit: 6c6988c5e03df145e6c5cabc50d67b11f5aa2e56
[4/7] drm/xe/configfs: Add post context restore bb
      commit: 39ac06f70062b6867836ea631e196cf2f60c1513
[5/7] drm/xe/lrc: Allow INDIRECT_CTX for more engine classes
      commit: c9dfd66cb91ef32f76e51f75e315c07907df2b85
[6/7] drm/xe/lrc: Allow to add user commands mid context switch
      commit: 7a4756b2fd0431f109b07b904a7442f00838abf9
[7/7] drm/xe/configfs: Add mid context restore bb
      commit: b30d5de3d40c3fa642079bac0d91f17091c5f877

--
Lucas De Marchi