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From: Andrea Parri <parri.andrea@gmail.com>
To: Guo Ren <guoren@kernel.org>
Cc: Xu Lu <luxu.kernel@bytedance.com>,
	robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, alex@ghiti.fr, ajones@ventanamicro.com,
	brs@rivosinc.com, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	apw@canonical.com, joe@perches.com
Subject: Re: [PATCH v2 0/4] riscv: Add Zalasr ISA extension support
Date: Thu, 18 Sep 2025 23:24:41 +0200	[thread overview]
Message-ID: <aMx4mS0K8f_aDV_q@andrea> (raw)
In-Reply-To: <aMw3504EwlnDOJI0@gmail.com>

[merging replies]

> > I prefer option c) at first, it has fewer modification and influence.
> Another reason is that store-release-to-load-acquire would give out a
> FENCE rw, rw according to RVWMO PPO 7th rule instead of FENCE.TSO, which
> is stricter than the Linux requirement you've mentioned.

I mean, if "fewer modification" and "not-a-full-fence" were the only
arguments, we would probably just stick with the current scheme (b),
right?  What other arguments are available?  Don't get me wrong: no a
priori objection from my end; I was really just wondering about the
various interests/rationales in the RISC-V kernel community.  (It may
surprise you, but some communities did consider that "UNLOCK+LOCK is
not a full memory barrier" a disadvantage, because briefly "locking
should provide strong ordering guarantees and be easy to reason about";
in fact, not just "locking" if we consider x86 or arm64...)


> > asm volatile(ALTERNATIVE("fence rw, w;\t\nsb %0, 0(%1)\t\n",	\
> > -			  SB_RL(%0, %1) "\t\nnop\t\n",		\
> > +			  SB_RL(%0, %1) "\t\n fence.tso;\t\n",	\
> > 			  0, RISCV_ISA_EXT_ZALASR, 1)		\
> > 			  : : "r" (v), "r" (p) : "memory");	\

nit: Why placing the fence after the store?  I imagine that FENCE.TSO
could precede the store, this way, the store would actually not need
to have that .RL annotation.  More importantly,

That for (part of) smp_store_release().  Let me stress that my option
(c) was meant to include similar changes for _every releases (that is,
cmpxchg_release(), atomic_inc_return_release(), and many other), even
if most of such releases do not currently create "problematic pairs"
with a corresponding acquire: the concern is that future changes in the
RISC-V atomics implementation or in generic locking code will introduce
pairs of the form FENCE RW,W + .AQ or .RL + FENCE R,RW without anyone
noticing...  In other words, I was suggesting that RISC-V _continues
to meet the ordering property under discussion "by design" rather than
"by Andrea or whoever's code auditing/review" (assuming it's feasible,
i.e. that it doesn't clash with other people's arguments?); options (a)
and (b) were also "designed" following this same criterion.

  Andrea

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Andrea Parri <parri.andrea@gmail.com>
To: Guo Ren <guoren@kernel.org>
Cc: Xu Lu <luxu.kernel@bytedance.com>,
	robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, alex@ghiti.fr, ajones@ventanamicro.com,
	brs@rivosinc.com, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	apw@canonical.com, joe@perches.com
Subject: Re: [PATCH v2 0/4] riscv: Add Zalasr ISA extension support
Date: Thu, 18 Sep 2025 23:24:41 +0200	[thread overview]
Message-ID: <aMx4mS0K8f_aDV_q@andrea> (raw)
In-Reply-To: <aMw3504EwlnDOJI0@gmail.com>

[merging replies]

> > I prefer option c) at first, it has fewer modification and influence.
> Another reason is that store-release-to-load-acquire would give out a
> FENCE rw, rw according to RVWMO PPO 7th rule instead of FENCE.TSO, which
> is stricter than the Linux requirement you've mentioned.

I mean, if "fewer modification" and "not-a-full-fence" were the only
arguments, we would probably just stick with the current scheme (b),
right?  What other arguments are available?  Don't get me wrong: no a
priori objection from my end; I was really just wondering about the
various interests/rationales in the RISC-V kernel community.  (It may
surprise you, but some communities did consider that "UNLOCK+LOCK is
not a full memory barrier" a disadvantage, because briefly "locking
should provide strong ordering guarantees and be easy to reason about";
in fact, not just "locking" if we consider x86 or arm64...)


> > asm volatile(ALTERNATIVE("fence rw, w;\t\nsb %0, 0(%1)\t\n",	\
> > -			  SB_RL(%0, %1) "\t\nnop\t\n",		\
> > +			  SB_RL(%0, %1) "\t\n fence.tso;\t\n",	\
> > 			  0, RISCV_ISA_EXT_ZALASR, 1)		\
> > 			  : : "r" (v), "r" (p) : "memory");	\

nit: Why placing the fence after the store?  I imagine that FENCE.TSO
could precede the store, this way, the store would actually not need
to have that .RL annotation.  More importantly,

That for (part of) smp_store_release().  Let me stress that my option
(c) was meant to include similar changes for _every releases (that is,
cmpxchg_release(), atomic_inc_return_release(), and many other), even
if most of such releases do not currently create "problematic pairs"
with a corresponding acquire: the concern is that future changes in the
RISC-V atomics implementation or in generic locking code will introduce
pairs of the form FENCE RW,W + .AQ or .RL + FENCE R,RW without anyone
noticing...  In other words, I was suggesting that RISC-V _continues
to meet the ordering property under discussion "by design" rather than
"by Andrea or whoever's code auditing/review" (assuming it's feasible,
i.e. that it doesn't clash with other people's arguments?); options (a)
and (b) were also "designed" following this same criterion.

  Andrea

  reply	other threads:[~2025-09-18 21:25 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-02  4:24 [PATCH v2 0/4] riscv: Add Zalasr ISA extension support Xu Lu
2025-09-02  4:24 ` Xu Lu
2025-09-02  4:24 ` [PATCH v2 1/4] riscv: add ISA extension parsing for Zalasr Xu Lu
2025-09-02  4:24   ` Xu Lu
2025-09-02  4:24 ` [PATCH v2 2/4] dt-bindings: riscv: Add Zalasr ISA extension description Xu Lu
2025-09-02  4:24   ` Xu Lu
2025-09-02 19:46   ` Conor Dooley
2025-09-02 19:46     ` Conor Dooley
2025-09-02  4:24 ` [PATCH v2 3/4] riscv: Instroduce Zalasr instructions Xu Lu
2025-09-02  4:24   ` Xu Lu
2025-09-02  4:24 ` [PATCH v2 4/4] riscv: Use Zalasr for smp_load_acquire/smp_store_release Xu Lu
2025-09-02  4:24   ` Xu Lu
2025-09-03  1:06   ` kernel test robot
2025-09-03  1:06     ` kernel test robot
2025-09-02 16:59 ` [PATCH v2 0/4] riscv: Add Zalasr ISA extension support Andrea Parri
2025-09-02 16:59   ` Andrea Parri
2025-09-03 11:41   ` [External] " Xu Lu
2025-09-03 11:41     ` Xu Lu
2025-09-17  4:01   ` Guo Ren
2025-09-17  4:01     ` Guo Ren
2025-09-17  4:57     ` Guo Ren
2025-09-17  4:57       ` Guo Ren
2025-09-18 16:48     ` Guo Ren
2025-09-18 16:48       ` Guo Ren
2025-09-18 21:24       ` Andrea Parri [this message]
2025-09-18 21:24         ` Andrea Parri
2025-09-20  5:59         ` Guo Ren
2025-09-20  5:59           ` Guo Ren
2025-09-19  3:18       ` [External] " Xu Lu
2025-09-19  3:18         ` Xu Lu
2025-09-19  7:45         ` Andrea Parri
2025-09-19  7:45           ` Andrea Parri
2025-09-19  8:22           ` Xu Lu
2025-09-19  8:22             ` Xu Lu
2025-09-20  6:04         ` Guo Ren
2025-09-20  6:04           ` Guo Ren

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