From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 7/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks
Date: Tue, 23 Sep 2025 17:32:28 +0300 [thread overview]
Message-ID: <aNKvfC7TR52Hg6np@intel.com> (raw)
In-Reply-To: <20250923131043.2628282-8-ankit.k.nautiyal@intel.com>
On Tue, Sep 23, 2025 at 06:40:41PM +0530, Ankit Nautiyal wrote:
> Until LNL, intel_dsb_wait_vblanks() waits for the undelayed vblank start.
> However, from PTL onwards, it waits for the start of the safe window,
> defined by the number of lines programmed in TRANS_SET_CONTEXT_LATENCY.
> This change was introduced to move the SCL window out of the vblank region,
> supporting modes with higher refresh rates and smaller vblanks.
>
> As a result, on PTL+ platforms, the DSB wait for vblank completes exactly
> SCL lines earlier than the undelayed vblank start. Since we use
> intel_dsb_wait_vblanks() to time the send push operation, this causes
> issues when SCL lines are non-zero.
>
> So instruct the DSB to wait from (undelayed vblank start - SCL) to
> (delayed vblank start - SCL) in the helper to wait for delayed vblank.
>
> v2:
> - Use helpers for safe window start/end. (Ville)
> - Move the extra wait inside the helper to wait for delayed vblank. (Ville)
> - Update the commit message.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dsb.c | 18 ++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vrr.c | 17 +++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vrr.h | 2 ++
> 3 files changed, 37 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 0584a9597327..e118ba4a0bb7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -815,6 +815,23 @@ void intel_dsb_chain(struct intel_atomic_state *state,
> wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0);
> }
>
> +static
> +void intel_dsb_wait_for_scl_start(struct intel_atomic_state *state,
> + struct intel_dsb *dsb)
> +{
> + struct intel_crtc *crtc = dsb->crtc;
> + const struct intel_crtc_state *crtc_state =
> + intel_pre_commit_crtc_state(state, crtc);
> + int start, end;
> +
> + if (!pre_commit_is_vrr_active(state, crtc))
> + return;
> +
> + start = intel_vrr_safe_window_start(crtc_state);
> + end = intel_vrr_safe_window_end(crtc_state);
> + intel_dsb_wait_scanline_out(state, dsb, start, end);
> +}
> +
> void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
> struct intel_dsb *dsb)
> {
> @@ -824,6 +841,7 @@ void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
> int usecs = intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode,
> dsb_vblank_delay(state, crtc));
>
Maybe we need a bit of explanation for this to
remind the reader what is going on. Eg. somethign like:
/*
* If the push happened before the vmin decision boundary
* we don't know how far we are from the undelayed vblank.
* Wait until we're past the vmin safe window, at which
* point we're SCL lines away from the delayed vblank.
*
* If the push happened after the vmin decision
* boundary the hardware itself guarantees that we're
* SCL lines away from the delayed vblank, and we
* won't be inside the vmin safe window so this is
* extra wait does nothing.
*/
> + intel_dsb_wait_for_scl_start(state, dsb);
It's a bit confusing to have this outside the existing
'if (vrr)' branch. I think I'd put this inside there.
And maybe just inline it there since we already
dug up the correct crtc_state anyway.
> intel_dsb_wait_usec(dsb, usecs);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 40e256bce3cb..8f851d3a3f44 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -800,3 +800,20 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> if (crtc_state->vrr.enable)
> crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> }
> +
> +int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> +
> + if (DISPLAY_VER(display) >= 30)
> + return crtc_state->hw.adjusted_mode.crtc_vdisplay -
> + crtc_state->set_context_latency;
> +
I'd use 'else' here for consistency with the existing code.
> + return crtc_state->hw.adjusted_mode.crtc_vdisplay;
> +}
> +
> +int intel_vrr_safe_window_end(const struct intel_crtc_state *crtc_state)
To be accurate this is the safe window end corresponding to
vmin so I'd call it intel_vrr_vmin_safe_window_end().
> +{
> + return intel_vrr_vmin_vblank_start(crtc_state) -
> + crtc_state->set_context_latency;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index b72e90b4abe5..a304b6c41103 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -41,5 +41,7 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
> void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
> void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
> bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
> +int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
> +int intel_vrr_safe_window_end(const struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_VRR_H__ */
> --
> 2.45.2
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2025-09-23 14:32 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-23 13:10 [PATCH 0/9] Introduce set_context_latency and refactor VRR/DSB timing logic Ankit Nautiyal
2025-09-23 13:10 ` [PATCH 1/9] drm/i915/psr: s/intel_psr_min_vblank_delay/intel_psr_min_set_context_latency Ankit Nautiyal
2025-09-23 13:10 ` [PATCH 2/9] drm/i915/display: Add set_context_latency to crtc_state Ankit Nautiyal
2025-09-23 14:11 ` Ville Syrjälä
2025-09-23 13:10 ` [PATCH 3/9] drm/i915/vrr: Use set_context_latency instead of intel_vrr_real_vblank_delay() Ankit Nautiyal
2025-09-23 13:10 ` [PATCH 4/9] drm/i915/vrr: Use SCL for computing guardband Ankit Nautiyal
2025-09-23 14:12 ` Ville Syrjälä
2025-09-23 13:10 ` [PATCH 5/9] drm/i915/vrr: s/intel_vrr_vblank_delay/intel_vrr_scl_delay Ankit Nautiyal
2025-09-23 14:13 ` Ville Syrjälä
2025-09-24 9:33 ` Nautiyal, Ankit K
2025-09-24 9:49 ` Ville Syrjälä
2025-09-23 13:10 ` [PATCH 6/9] drm/i915/dsb: s/intel_dsb_wait_vblank_delay/intel_dsb_wait_for_delayed_vblank Ankit Nautiyal
2025-09-23 17:21 ` Ville Syrjälä
2025-09-23 13:10 ` [PATCH 7/9] drm/i915/display: Wait for scl start instead of dsb_wait_vblanks Ankit Nautiyal
2025-09-23 14:32 ` Ville Syrjälä [this message]
2025-09-23 13:10 ` [PATCH 8/9] drm/i915/reg_defs: Add REG_FIELD_MAX wrapper for FIELD_MAX() Ankit Nautiyal
2025-09-23 17:27 ` Ville Syrjälä
2025-09-23 13:10 ` [PATCH 9/9] drm/i915/vrr: Clamp guardband as per hardware and timing constraints Ankit Nautiyal
2025-09-23 17:25 ` Ville Syrjälä
2025-09-23 13:32 ` ✓ CI.KUnit: success for Introduce set_context_latency and refactor VRR/DSB timing logic (rev2) Patchwork
2025-09-23 13:47 ` ✗ CI.checksparse: warning " Patchwork
2025-09-23 14:16 ` ✓ Xe.CI.BAT: success " Patchwork
2025-09-23 15:48 ` ✗ Xe.CI.Full: failure " Patchwork
2025-09-23 19:40 ` ✓ i915.CI.BAT: success " Patchwork
2025-09-24 4:25 ` ✗ i915.CI.Full: failure " Patchwork
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