From: Niklas Cassel <cassel@kernel.org>
To: Diederik de Haas <diederik@cknow-tech.com>
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Simon Xue" <xxm@rock-chips.com>,
"Kever Yang" <kever.yang@rock-chips.com>,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Damien Le Moal" <dlemoal@kernel.org>,
"Dragan Simic" <dsimic@manjaro.org>,
"FUKAUMI Naoki" <naoki@radxa.com>,
stable@vger.kernel.org,
"Manivannan Sadhasivam" <manivannan.sadhasivam@oss.qualcomm.com>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org
Subject: Re: [PATCH] PCI: dw-rockchip: Disable L1 substates
Date: Wed, 15 Oct 2025 17:35:43 +0200 [thread overview]
Message-ID: <aO-_T7rKFLSOCllp@ryzen> (raw)
In-Reply-To: <DDIXEBYPYJX8.2BPOQ14F816T2@cknow-tech.com>
Hello Diederik,
On Wed, Oct 15, 2025 at 03:21:48PM +0200, Diederik de Haas wrote:
> On Wed Oct 15, 2025 at 2:31 PM CEST, Niklas Cassel wrote:
> > The L1 substates support requires additional steps to work, see e.g.
> > section '11.6.6.4 L1 Substate' in the RK3588 TRM V1.0.
>
> I visually compared '18.6.6 PCIe Power Management' of Part 2 V1.1
> (20210301) of the RK3568 TRM with '11.6.6 PCIe Power Management' of
> Part 2 V1.0 (20220309) of the RK3588 TRM.
> AFAICT they are word for word the same ... until I got to 'Table 18-14
> PCIe Interrupt Table' (RK3568) and 'Table 11-22 ...' (RK3588) where
> there are differences. I don't understand enough of this material so I
> would appreciate if you could take a look to see if that difference is
> or could be relevant.
What you should compare is "18.6.6.4 L1 Substate" of RK3658 TRM Part2 V1.1,
vs "11.6.6.4 L1 Substate" of RK3588 TRM Part2 V1.0.
But I have just done that, and I can tell you that they are identical.
Shawn also replied here:
https://lore.kernel.org/linux-pci/7df0bf91-8ab1-4e76-83fa-841a4059c634@rock-chips.com/
that there is indeed a lot of things missing for L1 substates to work,
including proper pinmuxing.
Kind regards,
Niklas
WARNING: multiple messages have this Message-ID (diff)
From: Niklas Cassel <cassel@kernel.org>
To: Diederik de Haas <diederik@cknow-tech.com>
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Simon Xue" <xxm@rock-chips.com>,
"Kever Yang" <kever.yang@rock-chips.com>,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Damien Le Moal" <dlemoal@kernel.org>,
"Dragan Simic" <dsimic@manjaro.org>,
"FUKAUMI Naoki" <naoki@radxa.com>,
stable@vger.kernel.org,
"Manivannan Sadhasivam" <manivannan.sadhasivam@oss.qualcomm.com>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org
Subject: Re: [PATCH] PCI: dw-rockchip: Disable L1 substates
Date: Wed, 15 Oct 2025 17:35:43 +0200 [thread overview]
Message-ID: <aO-_T7rKFLSOCllp@ryzen> (raw)
In-Reply-To: <DDIXEBYPYJX8.2BPOQ14F816T2@cknow-tech.com>
Hello Diederik,
On Wed, Oct 15, 2025 at 03:21:48PM +0200, Diederik de Haas wrote:
> On Wed Oct 15, 2025 at 2:31 PM CEST, Niklas Cassel wrote:
> > The L1 substates support requires additional steps to work, see e.g.
> > section '11.6.6.4 L1 Substate' in the RK3588 TRM V1.0.
>
> I visually compared '18.6.6 PCIe Power Management' of Part 2 V1.1
> (20210301) of the RK3568 TRM with '11.6.6 PCIe Power Management' of
> Part 2 V1.0 (20220309) of the RK3588 TRM.
> AFAICT they are word for word the same ... until I got to 'Table 18-14
> PCIe Interrupt Table' (RK3568) and 'Table 11-22 ...' (RK3588) where
> there are differences. I don't understand enough of this material so I
> would appreciate if you could take a look to see if that difference is
> or could be relevant.
What you should compare is "18.6.6.4 L1 Substate" of RK3658 TRM Part2 V1.1,
vs "11.6.6.4 L1 Substate" of RK3588 TRM Part2 V1.0.
But I have just done that, and I can tell you that they are identical.
Shawn also replied here:
https://lore.kernel.org/linux-pci/7df0bf91-8ab1-4e76-83fa-841a4059c634@rock-chips.com/
that there is indeed a lot of things missing for L1 substates to work,
including proper pinmuxing.
Kind regards,
Niklas
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2025-10-15 15:36 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-15 12:31 [PATCH] PCI: dw-rockchip: Disable L1 substates Niklas Cassel
2025-10-15 12:31 ` Niklas Cassel
2025-10-15 12:35 ` Niklas Cassel
2025-10-15 12:35 ` Niklas Cassel
2025-10-15 13:21 ` Diederik de Haas
2025-10-15 13:21 ` Diederik de Haas
2025-10-15 15:35 ` Niklas Cassel [this message]
2025-10-15 15:35 ` Niklas Cassel
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