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From: Drew Fustini <fustini@kernel.org>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, "Palmer Dabbelt" <palmer@dabbelt.com>,
	"Alistair Francis" <Alistair.Francis@wdc.com>,
	"Weiwei Li" <liwei1518@gmail.com>,
	"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	qemu-riscv@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
	"Nicolas Pitre" <npitre@baylibre.com>,
	"Kornel Dulęba" <mindal@semihalf.com>,
	"Atish Kumar Patra" <atishp@rivosinc.com>,
	"Atish Patra" <atish.patra@linux.dev>,
	"Vasudevan Srinivasan" <vasu@rivosinc.com>,
	"Radim Krčmář" <rkrcmar@ventanamicro.com>,
	"yunhui cui" <cuiyunhui@bytedance.com>,
	"Chen Pei" <cp0613@linux.alibaba.com>,
	guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn
Subject: Re: [PATCH 1/7] riscv: implement Ssqosid extension and srmcfg CSR
Date: Thu, 20 Nov 2025 13:34:49 -0800	[thread overview]
Message-ID: <aR+JeXdCIfOCCpI8@x1> (raw)
In-Reply-To: <3592062a-f5f1-4350-87c1-ee9c4753ba15@ventanamicro.com>

On Thu, Nov 20, 2025 at 08:30:50AM -0300, Daniel Henrique Barboza wrote:
[snip]
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 5c91658c3dc4..06a6212c672d 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -1759,6 +1759,37 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
> >       return RISCV_EXCP_NONE;
> >   }
> > +static RISCVException check_srmcfg(CPURISCVState *env, int csrno)
> > +{
> > +    RISCVCPU *cpu = env_archcpu(env);
> > +
> > +    if (!cpu->cfg.ext_ssqosid) {
> > +        return RISCV_EXCP_ILLEGAL_INST;
> > +    }
> 
> env_archcpu() is a bit heavyweight and we usually avoid it. Since you're using the 'cpu' ptr
> solely to access the CFG pointer I suggest using riscv_cpu_cfg() instead:
> 
> if (!riscv_cpu_cfg(env)->ext_ssqosid) {...}

Thanks for letting me know. I will change to riscv_cpu_cfg() in the next
revision.

Drew


  reply	other threads:[~2025-11-20 21:35 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-20  0:42 [PATCH 0/7] riscv: implement Ssqosid extension and CBQRI controllers Drew Fustini
2025-11-20  0:42 ` [PATCH 1/7] riscv: implement Ssqosid extension and srmcfg CSR Drew Fustini
2025-11-20 11:30   ` Daniel Henrique Barboza
2025-11-20 21:34     ` Drew Fustini [this message]
2025-11-20 16:07   ` Radim Krčmář
2025-11-20 20:46     ` Drew Fustini
2025-11-24 16:54       ` Radim Krčmář
2025-11-20  0:42 ` [PATCH 2/7] hw/riscv: define capabilities of CBQRI controllers Drew Fustini
2025-11-20 11:59   ` Daniel Henrique Barboza
2025-11-20  0:42 ` [PATCH 3/7] hw/riscv: implement CBQRI capacity controller Drew Fustini
2025-11-20 11:47   ` Daniel Henrique Barboza
2025-11-21 18:57     ` Drew Fustini
2025-11-20 19:25   ` Radim Krčmář
2025-11-21 19:50     ` Drew Fustini
2025-11-24 17:02       ` Radim Krčmář
2025-11-24 18:37         ` Drew Fustini
2025-11-25 11:55           ` Radim Krčmář
2025-11-20  0:42 ` [PATCH 4/7] hw/riscv: implement CBQRI bandwidth controller Drew Fustini
2025-11-20 11:51   ` Daniel Henrique Barboza
2025-11-24 17:06   ` Radim Krčmář
2025-11-24 18:45     ` Drew Fustini
2025-11-20  0:42 ` [PATCH 5/7] hw/riscv: Kconfig: add CBQRI options Drew Fustini
2025-11-20  0:42 ` [PATCH 6/7] hw/riscv: meson: add CBQRI controllers to the build Drew Fustini
2025-11-20 12:01   ` Daniel Henrique Barboza
2025-11-20 20:56     ` Drew Fustini
2025-11-20  0:42 ` [PATCH 7/7] hw/riscv: add CBQRI controllers to virt machine Drew Fustini
2025-11-20 12:01   ` Daniel Henrique Barboza

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