[PATCH 0/8] arm64: dts: imx8dxl related fix and minor update

[PATCH 0/8] arm64: dts: imx8dxl related fix and minor update

[Frank Li]

imx8dxl dts some fixes and minor update.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Frank Li (7):
      arm64: dts: imx8dxl: Correct pcie-ep interrupt number
      arm64: dts: imx8dxl-ss-conn: swap interrupts number of eqos
      arm64: dts: imx8dxl-evk: add bt information for lpuart1
      arm64: dts: imx8dxl-evk: add state_100mhz and state_200mhz for usdhc
      arm64: dts: imx8-ss-conn: add fsl,tuning-step for usdhc1 and usdhc2
      arm64: dts: imx8-ss-conn: add missed clock enet_2x_txclk for fec[1,2]
      arm64: dts: imx8dxl-ss-conn: delete usb3_lpcg node

Shenwei Wang (1):
      arm64: dts: imx8: add default clock rate for usdhc

 arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi    | 20 ++++++++++++++++----
 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts      | 13 +++++++++++--
 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi |  5 +++--
 arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi |  5 +++++
 4 files changed, 35 insertions(+), 8 deletions(-)
---
base-commit: 0d10adc5de0077ec21554769f55fd5b40a00b8d7
change-id: 20251022-dxl_dts-df1ff201e69a

Best regards,
--
Frank Li <Frank.Li@nxp.com>

[PATCH 1/8] arm64: dts: imx8dxl: Correct pcie-ep interrupt number

[Frank Li]

Correct i.MX8DXL's pcie-ep interrupt number.

Fixes: d03743c5659a9 ("arm64: dts: imx8q: add PCIe EP for i.MX8QM and i.MX8QXP")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi
index ec466e4d7df5467803243404795a9a6a1da890b2..5c0d09c5c08627f9978f0f69dcc84f6b2b917d62 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi
@@ -54,3 +54,8 @@ pcie0_ep: pcie-ep@5f010000 {
 		interrupt-names = "dma";
 	};
 };
+
+&pcieb_ep {
+	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "dma";
+};

-- 
2.34.1

[PATCH 2/8] arm64: dts: imx8dxl-ss-conn: swap interrupts number of eqos

[Frank Li]

Swap interrupt numbers of eqos because the below commit just swap
interrupt-names and missed swap interrupts also.

The driver (drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c) use
interrupt-names to get irq numbers.

Fixes: f29c19a6e488 ("arm64: dts: imx8dxl-ss-conn: Fix Ethernet interrupt-names order")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
index a66ba6d0a8c05646320dc45e460662ab0ae2aa3b..da33a35c6d4660ebf0fa3f7afcf7f7a289c3c419 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
@@ -29,8 +29,8 @@ eqos: ethernet@5b050000 {
 		compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
 		reg = <0x5b050000 0x10000>;
 		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "macirq", "eth_wake_irq";
 		clocks = <&eqos_lpcg IMX_LPCG_CLK_4>,
 			 <&eqos_lpcg IMX_LPCG_CLK_6>,

-- 
2.34.1

Re: [PATCH 2/8] arm64: dts: imx8dxl-ss-conn: swap interrupts number of eqos

[Alexander Dahl]

Hello Frank,

Am Wed, Oct 22, 2025 at 12:50:22PM -0400 schrieb Frank Li:
> Swap interrupt numbers of eqos because the below commit just swap
> interrupt-names and missed swap interrupts also.
> 
> The driver (drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c) use
> interrupt-names to get irq numbers.

This catched my eye, because we are using a SolidRun i.MX 8XLite
System-on-Module on a custom baseboard which uses that SoC.

I had problems with one CPU core stalling when doing network traffic
over the 'end1' interface, which is that eqos interface here.  All I
could see so far were an excessive number of hardware interrupts in
/proc/interrupts for end1.  With this patch this behaviour is gone, I
could not reproduce those lock-up anymore.  Thank you and FWIW:

Tested-by: Alexander Dahl <ada@thorsis.com>

Note: I applied this to v6.12.  The patch has a Fixes: tag, so I
assume it hits stable once it got merged without further action,
right?

Adding Josua Mayer to Cc because it might affect other users of that
SoM.  Josua, would it be possible to upstream the dts/dtsi files for
that SoM? O:-)

Greets
Alex

> 
> Fixes: f29c19a6e488 ("arm64: dts: imx8dxl-ss-conn: Fix Ethernet interrupt-names order")
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
> index a66ba6d0a8c05646320dc45e460662ab0ae2aa3b..da33a35c6d4660ebf0fa3f7afcf7f7a289c3c419 100644
> --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
> @@ -29,8 +29,8 @@ eqos: ethernet@5b050000 {
>  		compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
>  		reg = <0x5b050000 0x10000>;
>  		interrupt-parent = <&gic>;
> -		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
> -			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
>  		interrupt-names = "macirq", "eth_wake_irq";
>  		clocks = <&eqos_lpcg IMX_LPCG_CLK_4>,
>  			 <&eqos_lpcg IMX_LPCG_CLK_6>,
> 
> -- 
> 2.34.1
> 
> 

[PATCH 3/8] arm64: dts: imx8dxl-evk: add bt information for lpuart1

[Frank Li]

Add BT information for lpuart1.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index 25a77cac6f0b5f71603933e75a6930956ac7239c..bd58fa54fea8922327393a47d9060ad33e38cac7 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -598,6 +598,10 @@ &lpuart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lpuart1>;
 	status = "okay";
+
+	bluetooth {
+		compatible = "nxp,88w8987-bt";
+	};
 };
 
 &lsio_mu5 {

-- 
2.34.1

[PATCH 4/8] arm64: dts: imx8dxl-evk: add state_100mhz and state_200mhz for usdhc

[Frank Li]

Default, state_100mhz and state_200mhz use the same settings. But current
kernel driver use these to indicate if sd3.0 support.

Add max-frequency for usdhc2 because board design limitation.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index bd58fa54fea8922327393a47d9060ad33e38cac7..4a070bc0c4db713987ebc038f2189b3fbcdc91ad 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -779,8 +779,10 @@ &usbotg2 {
 };
 
 &usdhc1 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1>;
+	pinctrl-2 = <&pinctrl_usdhc1>;
 	bus-width = <8>;
 	no-sd;
 	no-sdio;
@@ -789,12 +791,15 @@ &usdhc1 {
 };
 
 &usdhc2 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 	bus-width = <4>;
 	vmmc-supply = <&reg_usdhc2_vmmc>;
 	cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
+	max-frequency = <100000000>;
 	status = "okay";
 };
 

-- 
2.34.1

[PATCH 5/8] arm64: dts: imx8: add default clock rate for usdhc

[Frank Li]

From: Shenwei Wang <shenwei.wang@nxp.com>

Add default clock rate for usdhc nodes to support higher transfer speed.

Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index ce6ef160fd5506cf6430be321ca75cb658669335..0b8b32f6976813515bc8d9dce5486074d0ec8b7e 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -77,6 +77,8 @@ usdhc1: mmc@5b010000 {
 			 <&sdhc0_lpcg IMX_LPCG_CLK_5>,
 			 <&sdhc0_lpcg IMX_LPCG_CLK_0>;
 		clock-names = "ipg", "ahb", "per";
+		assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <400000000>;
 		power-domains = <&pd IMX_SC_R_SDHC_0>;
 		status = "disabled";
 	};
@@ -88,6 +90,8 @@ usdhc2: mmc@5b020000 {
 			 <&sdhc1_lpcg IMX_LPCG_CLK_5>,
 			 <&sdhc1_lpcg IMX_LPCG_CLK_0>;
 		clock-names = "ipg", "ahb", "per";
+		assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <200000000>;
 		power-domains = <&pd IMX_SC_R_SDHC_1>;
 		fsl,tuning-start-tap = <20>;
 		fsl,tuning-step = <2>;
@@ -101,6 +105,8 @@ usdhc3: mmc@5b030000 {
 			 <&sdhc2_lpcg IMX_LPCG_CLK_5>,
 			 <&sdhc2_lpcg IMX_LPCG_CLK_0>;
 		clock-names = "ipg", "ahb", "per";
+		assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <200000000>;
 		power-domains = <&pd IMX_SC_R_SDHC_2>;
 		status = "disabled";
 	};

-- 
2.34.1

[PATCH 6/8] arm64: dts: imx8-ss-conn: add fsl,tuning-step for usdhc1 and usdhc2

[Frank Li]

Add fsl,tuning-step for usdhc1 and usdhc2 to improve card compatibility.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index 0b8b32f6976813515bc8d9dce5486074d0ec8b7e..f99b9ce5f6540a1219fa25646208b4d61ec69efc 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -80,6 +80,8 @@ usdhc1: mmc@5b010000 {
 		assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
 		assigned-clock-rates = <400000000>;
 		power-domains = <&pd IMX_SC_R_SDHC_0>;
+		fsl,tuning-start-tap = <20>;
+		fsl,tuning-step = <2>;
 		status = "disabled";
 	};
 
@@ -108,6 +110,8 @@ usdhc3: mmc@5b030000 {
 		assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>;
 		assigned-clock-rates = <200000000>;
 		power-domains = <&pd IMX_SC_R_SDHC_2>;
+		fsl,tuning-start-tap = <20>;
+		fsl,tuning-step = <2>;
 		status = "disabled";
 	};
 

-- 
2.34.1

[PATCH 7/8] arm64: dts: imx8-ss-conn: add missed clock enet_2x_txclk for fec[1,2]

[Frank Li]

Add missed clock enet_2x_txclk for fec[1,2].

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index f99b9ce5f6540a1219fa25646208b4d61ec69efc..176e2e332f87c5444ca4457e3af653a87351b434 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -124,8 +124,9 @@ fec1: ethernet@5b040000 {
 		clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
 			 <&enet0_lpcg IMX_LPCG_CLK_2>,
 			 <&enet0_lpcg IMX_LPCG_CLK_3>,
-			 <&enet0_lpcg IMX_LPCG_CLK_0>;
-		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
+			 <&enet0_lpcg IMX_LPCG_CLK_0>,
+			 <&enet0_lpcg IMX_LPCG_CLK_1>;
+		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
 		assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
 				  <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
 		assigned-clock-rates = <250000000>, <125000000>;
@@ -144,8 +145,9 @@ fec2: ethernet@5b050000 {
 		clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
 			 <&enet1_lpcg IMX_LPCG_CLK_2>,
 			 <&enet1_lpcg IMX_LPCG_CLK_3>,
-			 <&enet1_lpcg IMX_LPCG_CLK_0>;
-		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
+			 <&enet1_lpcg IMX_LPCG_CLK_0>,
+			 <&enet0_lpcg IMX_LPCG_CLK_1>;
+		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
 		assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
 				  <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
 		assigned-clock-rates = <250000000>, <125000000>;

-- 
2.34.1

[PATCH 8/8] arm64: dts: imx8dxl-ss-conn: delete usb3_lpcg node

[Frank Li]

Delete usb3_lpcg node for imx8dxl because not exist at such hardware.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
index da33a35c6d4660ebf0fa3f7afcf7f7a289c3c419..74f9ce493248ee9431e81f23bdd9125c832c02f4 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
@@ -7,6 +7,7 @@
 /delete-node/ &fec2;
 /delete-node/ &usbotg3;
 /delete-node/ &usb3_phy;
+/delete-node/ &usb3_lpcg;
 
 / {
 	conn_enet0_root_clk: clock-conn-enet0-root {

-- 
2.34.1

Re: [PATCH 0/8] arm64: dts: imx8dxl related fix and minor update

[Shawn Guo]

On Wed, Oct 22, 2025 at 12:50:20PM -0400, Frank Li wrote:
> imx8dxl dts some fixes and minor update.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> Frank Li (7):
>       arm64: dts: imx8dxl: Correct pcie-ep interrupt number
>       arm64: dts: imx8dxl-ss-conn: swap interrupts number of eqos
>       arm64: dts: imx8dxl-evk: add bt information for lpuart1
>       arm64: dts: imx8dxl-evk: add state_100mhz and state_200mhz for usdhc
>       arm64: dts: imx8-ss-conn: add fsl,tuning-step for usdhc1 and usdhc2
>       arm64: dts: imx8-ss-conn: add missed clock enet_2x_txclk for fec[1,2]
>       arm64: dts: imx8dxl-ss-conn: delete usb3_lpcg node
> 
> Shenwei Wang (1):
>       arm64: dts: imx8: add default clock rate for usdhc

Applied all, thanks!