Re: [PATCH v6 0/3] Add support for Glymur PCIe Gen5 x4

From: Vinod Koul <vkoul@kernel.org>
To: Qiang Yu <qiang.yu@oss.qualcomm.com>
Cc: Kishon Vijay Abraham I <kishon@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>,
	Wenbin Yao <wenbin.yao@oss.qualcomm.com>,
	Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
	Manivannan Sadhasivam <mani@kernel.org>
Subject: Re: [PATCH v6 0/3] Add support for Glymur PCIe Gen5 x4
Date: Tue, 18 Nov 2025 22:40:59 +0530	[thread overview]
Message-ID: <aRyoo2Ve_hjgc84M@vaman> (raw)
In-Reply-To: <20251103-glymur-pcie-upstream-v6-0-18a5e0a538dc@oss.qualcomm.com>

On 03-11-25, 23:56, Qiang Yu wrote:
> Glymur is the next generation compute SoC of Qualcomm. This patch series
> aims to add support for the fourth, fifth and sixth PCIe instance on it.
> The fifth PCIe instance on Glymur has a Gen5 4-lane PHY and fourth, fifth
> and sixth PCIe instance have a Gen5 2-lane PHY.
> 
> The device tree changes and whatever driver patches that are not part of
> this patch series will be posted separately after official announcement of
> the SOC.

Please rebase on phy/next, this does not apply for me

-- 
~Vinod