From: Niklas Cassel <cassel@kernel.org>
To: Hans Zhang <18255117159@163.com>
Cc: lpieralisi@kernel.org, kwilczynski@kernel.org,
bhelgaas@google.com, helgaas@kernel.org, heiko@sntech.de,
mani@kernel.org, yue.wang@amlogic.com, pali@kernel.org,
neil.armstrong@linaro.org, robh@kernel.org, jingoohan1@gmail.com,
khilman@baylibre.com, jbrunet@baylibre.com,
martin.blumenstingl@googlemail.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org,
linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v6 0/2] PCI: Configure Root Port MPS during host probing
Date: Mon, 24 Nov 2025 10:49:44 +0100 [thread overview]
Message-ID: <aSQqOHH2VLNNpX3D@ryzen> (raw)
In-Reply-To: <20251104165125.174168-1-18255117159@163.com>
On Wed, Nov 05, 2025 at 12:51:23AM +0800, Hans Zhang wrote:
> Current PCIe initialization exhibits a key optimization gap: Root Ports
> may operate with non-optimal Maximum Payload Size (MPS) settings. While
> downstream device configuration is handled during bus enumeration, Root
> Port MPS values inherited from firmware or hardware defaults often fail
> to utilize the full capabilities supported by controller hardware. This
> results in suboptimal data transfer efficiency throughout the PCIe
> hierarchy.
Hello PCI maintainers,
Merge window is opening soon,
what is the status of this series?
Kind regards,
Niklas
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
WARNING: multiple messages have this Message-ID (diff)
From: Niklas Cassel <cassel@kernel.org>
To: Hans Zhang <18255117159@163.com>
Cc: lpieralisi@kernel.org, kwilczynski@kernel.org,
bhelgaas@google.com, helgaas@kernel.org, heiko@sntech.de,
mani@kernel.org, yue.wang@amlogic.com, pali@kernel.org,
neil.armstrong@linaro.org, robh@kernel.org, jingoohan1@gmail.com,
khilman@baylibre.com, jbrunet@baylibre.com,
martin.blumenstingl@googlemail.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org,
linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v6 0/2] PCI: Configure Root Port MPS during host probing
Date: Mon, 24 Nov 2025 10:49:44 +0100 [thread overview]
Message-ID: <aSQqOHH2VLNNpX3D@ryzen> (raw)
In-Reply-To: <20251104165125.174168-1-18255117159@163.com>
On Wed, Nov 05, 2025 at 12:51:23AM +0800, Hans Zhang wrote:
> Current PCIe initialization exhibits a key optimization gap: Root Ports
> may operate with non-optimal Maximum Payload Size (MPS) settings. While
> downstream device configuration is handled during bus enumeration, Root
> Port MPS values inherited from firmware or hardware defaults often fail
> to utilize the full capabilities supported by controller hardware. This
> results in suboptimal data transfer efficiency throughout the PCIe
> hierarchy.
Hello PCI maintainers,
Merge window is opening soon,
what is the status of this series?
Kind regards,
Niklas
WARNING: multiple messages have this Message-ID (diff)
From: Niklas Cassel <cassel@kernel.org>
To: Hans Zhang <18255117159@163.com>
Cc: lpieralisi@kernel.org, kwilczynski@kernel.org,
bhelgaas@google.com, helgaas@kernel.org, heiko@sntech.de,
mani@kernel.org, yue.wang@amlogic.com, pali@kernel.org,
neil.armstrong@linaro.org, robh@kernel.org, jingoohan1@gmail.com,
khilman@baylibre.com, jbrunet@baylibre.com,
martin.blumenstingl@googlemail.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-amlogic@lists.infradead.org,
linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v6 0/2] PCI: Configure Root Port MPS during host probing
Date: Mon, 24 Nov 2025 10:49:44 +0100 [thread overview]
Message-ID: <aSQqOHH2VLNNpX3D@ryzen> (raw)
In-Reply-To: <20251104165125.174168-1-18255117159@163.com>
On Wed, Nov 05, 2025 at 12:51:23AM +0800, Hans Zhang wrote:
> Current PCIe initialization exhibits a key optimization gap: Root Ports
> may operate with non-optimal Maximum Payload Size (MPS) settings. While
> downstream device configuration is handled during bus enumeration, Root
> Port MPS values inherited from firmware or hardware defaults often fail
> to utilize the full capabilities supported by controller hardware. This
> results in suboptimal data transfer efficiency throughout the PCIe
> hierarchy.
Hello PCI maintainers,
Merge window is opening soon,
what is the status of this series?
Kind regards,
Niklas
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2025-11-24 9:49 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-04 16:51 [PATCH v6 0/2] PCI: Configure Root Port MPS during host probing Hans Zhang
2025-11-04 16:51 ` Hans Zhang
2025-11-04 16:51 ` Hans Zhang
2025-11-04 16:51 ` [PATCH v6 1/2] " Hans Zhang
2025-11-04 16:51 ` Hans Zhang
2025-11-04 16:51 ` Hans Zhang
2025-11-12 8:31 ` Shawn Lin
2025-11-12 8:31 ` Shawn Lin
2025-11-12 8:31 ` Shawn Lin
2025-11-12 11:04 ` Hans Zhang
2025-11-12 11:04 ` Hans Zhang
2025-11-12 11:04 ` Hans Zhang
2025-11-26 23:54 ` Bjorn Helgaas
2025-11-26 23:54 ` Bjorn Helgaas
2025-11-26 23:54 ` Bjorn Helgaas
2025-11-27 16:58 ` Hans Zhang
2025-11-27 16:58 ` Hans Zhang
2025-11-27 16:58 ` Hans Zhang
2025-11-04 16:51 ` [PATCH v6 2/2] PCI: dwc: Remove redundant MPS configuration Hans Zhang
2025-11-04 16:51 ` Hans Zhang
2025-11-04 16:51 ` Hans Zhang
2025-11-12 8:06 ` [PATCH v6 0/2] PCI: Configure Root Port MPS during host probing Mahesh Vaidya
2025-11-12 8:06 ` Mahesh Vaidya
2025-11-12 8:06 ` Mahesh Vaidya
2025-11-12 8:16 ` Hans Zhang
2025-11-12 8:16 ` Hans Zhang
2025-11-12 8:16 ` Hans Zhang
2025-11-24 9:49 ` Niklas Cassel [this message]
2025-11-24 9:49 ` Niklas Cassel
2025-11-24 9:49 ` Niklas Cassel
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