From: Alison Schofield <alison.schofield@intel.com>
To: Robert Richter <rrichter@amd.com>
Cc: Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
"Davidlohr Bueso" <dave@stgolabs.net>,
<linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Gregory Price <gourry@gourry.net>,
"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
Terry Bowman <terry.bowman@amd.com>,
Joshua Hahn <joshua.hahnjy@gmail.com>
Subject: Re: [PATCH v6 00/11] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement
Date: Wed, 3 Dec 2025 20:22:17 -0800 [thread overview]
Message-ID: <aTEMeRzI0_zcT-S3@aschofie-mobl2.lan> (raw)
In-Reply-To: <aRs4ILR8EEwnfOtQ@rric.localdomain>
On Mon, Nov 17, 2025 at 03:58:40PM +0100, Robert Richter wrote:
> On 14.11.25 12:01:29, Alison Schofield wrote:
>
> > Does this work 'as is', no changes required, to support DPA->SPA
> > (used in CXL Events) or SPA->DPA (used in poison by region offset)?
>
> The PRM handler could be used for to-SPA translations, but it might
> not fit well to other users such as profiling, tracing and error
> handling. Those users are executing in a critical path from a
> performance or stability point of view. Performing a firmware call
> could cause problems here. Since the to-DPA translation is missing
> too, a different approach to solve address translation might work
> better, such as examining the region parameters. The kernel's address
> translation library could possibly be extended and used too. That
> needs to be figured out. Also, my main focus for the patches is region
> enablement.
I see a dpa-to-spa prm routine. I don't know enough about the cost of
using it to say it's not worth using for CXl trace events that want
to report a SPA (from a DPA).
If we cannot trust what the address translation code will emit in
this case, forcing it to ULLONG_MAX would be safest.
-- Alison
>
> Thanks,
>
> -Robert
next prev parent reply other threads:[~2025-12-04 4:22 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-14 0:40 [PATCH v6 00/11] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Robert Richter
2025-11-14 0:40 ` [PATCH v6 01/11] cxl/region: Rename misleading variable name @hpa to @hpa_range Robert Richter
2025-11-14 0:40 ` [PATCH v6 02/11] cxl/region: Store root decoder in struct cxl_region Robert Richter
2025-11-14 0:40 ` [PATCH v6 03/11] cxl/region: Store HPA range " Robert Richter
2025-11-14 0:40 ` [PATCH v6 04/11] cxl: Simplify cxl_root_ops allocation and handling Robert Richter
2025-11-14 0:40 ` [PATCH v6 05/11] cxl/region: Separate region parameter setup and region construction Robert Richter
2025-11-14 0:40 ` [PATCH v6 06/11] cxl/region: Add @hpa_range argument to function cxl_calc_interleave_pos() Robert Richter
2025-11-14 0:40 ` [PATCH v6 07/11] cxl/region: Use region data to get the root decoder Robert Richter
2025-11-14 0:40 ` [PATCH v6 08/11] cxl: Introduce callback for HPA address ranges translation Robert Richter
2025-11-14 0:40 ` [PATCH v6 09/11] cxl/acpi: Prepare use of EFI runtime services Robert Richter
2025-11-14 0:40 ` [PATCH v6 10/11] cxl: Enable AMD Zen5 address translation using ACPI PRMT Robert Richter
2025-11-14 0:40 ` [PATCH v6 11/11] cxl/atl: Lock decoders that need address translation Robert Richter
2025-11-14 20:01 ` [PATCH v6 00/11] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Alison Schofield
2025-11-17 14:58 ` Robert Richter
2025-11-24 1:14 ` Alison Schofield
2025-11-24 20:10 ` Gregory Price
2025-11-25 3:26 ` Alison Schofield
2025-11-25 13:54 ` Gregory Price
2025-11-25 16:37 ` Alison Schofield
2025-11-25 21:04 ` Gregory Price
2025-12-04 4:22 ` Alison Schofield [this message]
2025-12-05 10:02 ` Robert Richter
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