* [PATCH 0/2] Add MPFS CPU Implementation @ 2025-11-19 12:38 Jamie Gibbons 2025-11-19 12:38 ` [PATCH 1/2] riscv: create a custom CPU implementation for PolarFire SoC Jamie Gibbons 2025-11-19 12:38 ` [PATCH 2/2] riscv: mpfs: move SoC level options to the CPU Kconfig Jamie Gibbons 0 siblings, 2 replies; 6+ messages in thread From: Jamie Gibbons @ 2025-11-19 12:38 UTC (permalink / raw) To: u-boot Cc: Conor Dooley, Valentina Fernandez Alanis, Tom Rini, Leo, Rick Chen, Yao Zi, Junhui Liu, jamie.gibbons Hi all, The following series creates a custom CPU implementation for Microchip's PolarFire SoC as it needs a custom implementation of top_of_ram(). Since there are multiple boards that use the PolarFire SoC, some kconfigs that are determined at a CPU level are moved from the board kconfigs. Thanks Jamie. Conor Dooley (2): riscv: create a custom CPU implementation for PolarFire SoC riscv: mpfs: move SoC level options to the CPU Kconfig arch/riscv/Kconfig | 1 + arch/riscv/cpu/mpfs/Kconfig | 33 ++++++++++++++++++++++ arch/riscv/cpu/mpfs/Makefile | 6 ++++ arch/riscv/cpu/mpfs/cpu.c | 22 +++++++++++++++ arch/riscv/cpu/mpfs/dram.c | 38 ++++++++++++++++++++++++++ arch/riscv/include/asm/arch-mpfs/clk.h | 8 ++++++ board/microchip/mpfs_generic/Kconfig | 24 ++-------------- 7 files changed, 110 insertions(+), 22 deletions(-) create mode 100644 arch/riscv/cpu/mpfs/Kconfig create mode 100644 arch/riscv/cpu/mpfs/Makefile create mode 100644 arch/riscv/cpu/mpfs/cpu.c create mode 100644 arch/riscv/cpu/mpfs/dram.c create mode 100644 arch/riscv/include/asm/arch-mpfs/clk.h -- 2.43.0 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] riscv: create a custom CPU implementation for PolarFire SoC 2025-11-19 12:38 [PATCH 0/2] Add MPFS CPU Implementation Jamie Gibbons @ 2025-11-19 12:38 ` Jamie Gibbons 2025-12-04 7:45 ` Leo Liang 2025-11-19 12:38 ` [PATCH 2/2] riscv: mpfs: move SoC level options to the CPU Kconfig Jamie Gibbons 1 sibling, 1 reply; 6+ messages in thread From: Jamie Gibbons @ 2025-11-19 12:38 UTC (permalink / raw) To: u-boot Cc: Conor Dooley, Valentina Fernandez Alanis, Tom Rini, Leo, Rick Chen, Yao Zi, Junhui Liu, jamie.gibbons From: Conor Dooley <conor.dooley@microchip.com> PolarFire SoC needs a custom implementation of top_of_ram(), so stop using the generic CPU & create a custom CPU instead. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- arch/riscv/Kconfig | 1 + arch/riscv/cpu/mpfs/Kconfig | 16 +++++++++++ arch/riscv/cpu/mpfs/Makefile | 6 ++++ arch/riscv/cpu/mpfs/cpu.c | 22 +++++++++++++++ arch/riscv/cpu/mpfs/dram.c | 38 ++++++++++++++++++++++++++ arch/riscv/include/asm/arch-mpfs/clk.h | 8 ++++++ board/microchip/mpfs_generic/Kconfig | 4 +-- 7 files changed, 93 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/cpu/mpfs/Kconfig create mode 100644 arch/riscv/cpu/mpfs/Makefile create mode 100644 arch/riscv/cpu/mpfs/cpu.c create mode 100644 arch/riscv/cpu/mpfs/dram.c create mode 100644 arch/riscv/include/asm/arch-mpfs/clk.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 265b5320777..79867656b15 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -126,6 +126,7 @@ source "arch/riscv/cpu/cv1800b/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/ast2700/Kconfig" +source "arch/riscv/cpu/mpfs/Kconfig" source "arch/riscv/cpu/generic/Kconfig" source "arch/riscv/cpu/jh7110/Kconfig" source "arch/riscv/cpu/k1/Kconfig" diff --git a/arch/riscv/cpu/mpfs/Kconfig b/arch/riscv/cpu/mpfs/Kconfig new file mode 100644 index 00000000000..3e99c1aae38 --- /dev/null +++ b/arch/riscv/cpu/mpfs/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0+ + +config MICROCHIP_MPFS + bool + select ARCH_EARLY_INIT_R + imply CPU + imply CPU_RISCV + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply SIFIVE_CLINT if RISCV_MMODE + imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE + imply CMD_CPU + imply SPL_CPU + imply SPL_OPENSBI + imply SPL_LOAD_FIT + imply REGMAP + imply SYSCON diff --git a/arch/riscv/cpu/mpfs/Makefile b/arch/riscv/cpu/mpfs/Makefile new file mode 100644 index 00000000000..c4bf2b4c292 --- /dev/null +++ b/arch/riscv/cpu/mpfs/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ + +ifneq ($(CONFIG_SPL_BUILD),y) +obj-y += dram.o +obj-y += cpu.o +endif diff --git a/arch/riscv/cpu/mpfs/cpu.c b/arch/riscv/cpu/mpfs/cpu.c new file mode 100644 index 00000000000..f13c18942f3 --- /dev/null +++ b/arch/riscv/cpu/mpfs/cpu.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <irq_func.h> +#include <asm/cache.h> + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + cache_flush(); + + return 0; +} diff --git a/arch/riscv/cpu/mpfs/dram.c b/arch/riscv/cpu/mpfs/dram.c new file mode 100644 index 00000000000..4398d3e36c8 --- /dev/null +++ b/arch/riscv/cpu/mpfs/dram.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <asm/global_data.h> +#include <fdtdec.h> +#include <init.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define MPFS_TOP_OF_CACHED (SZ_2G + SZ_1G) +#define MPFS_HSS_RESERVATION (SZ_4M) + +int dram_init(void) { + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) { + return fdtdec_setup_memory_banksize(); +} + +phys_size_t board_get_usable_ram_top(phys_size_t total_size) { + /* + * Ensure that if we run from 32-bit memory that all memory used by + * U-Boot is cached addresses, but also account for the reservation at + * the top of 32 bit cached DDR used by the HSS. + */ + if (gd->ram_top >= MPFS_TOP_OF_CACHED - MPFS_HSS_RESERVATION) + return MPFS_TOP_OF_CACHED - MPFS_HSS_RESERVATION - 1; + /* + * If we don't find a 32 bit region just return the top of memory. + * If the address is a 32-bit region, but fits beneath the HSS' + * reservation, ram_top is adequate also. + */ + return gd->ram_top; +} \ No newline at end of file diff --git a/arch/riscv/include/asm/arch-mpfs/clk.h b/arch/riscv/include/asm/arch-mpfs/clk.h new file mode 100644 index 00000000000..fbb1399f3c8 --- /dev/null +++ b/arch/riscv/include/asm/arch-mpfs/clk.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_RISCV_ARCH_MPFS_CLK_H +#define __ASM_RISCV_ARCH_MPFS_CLK_H + +/* Note: This is a placeholder header for driver compilation. */ + +#endif diff --git a/board/microchip/mpfs_generic/Kconfig b/board/microchip/mpfs_generic/Kconfig index 8dcf55a0311..49663a4c562 100644 --- a/board/microchip/mpfs_generic/Kconfig +++ b/board/microchip/mpfs_generic/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "microchip" config SYS_CPU - default "generic" + default "mpfs" config SYS_CONFIG_NAME default "microchip_mpfs_generic" @@ -18,7 +18,7 @@ config TEXT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select GENERIC_RISCV + select MICROCHIP_MPFS select BOARD_EARLY_INIT_F select BOARD_LATE_INIT imply SMP -- 2.43.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] riscv: create a custom CPU implementation for PolarFire SoC 2025-11-19 12:38 ` [PATCH 1/2] riscv: create a custom CPU implementation for PolarFire SoC Jamie Gibbons @ 2025-12-04 7:45 ` Leo Liang 2025-12-08 12:10 ` Jamie.Gibbons 0 siblings, 1 reply; 6+ messages in thread From: Leo Liang @ 2025-12-04 7:45 UTC (permalink / raw) To: Jamie Gibbons Cc: u-boot, Conor Dooley, Valentina Fernandez Alanis, Tom Rini, Rick Chen, Yao Zi, Junhui Liu Hi Jamie, On Wed, Nov 19, 2025 at 12:38:42PM +0000, Jamie Gibbons wrote: > [EXTERNAL MAIL] > > From: Conor Dooley <conor.dooley@microchip.com> > > PolarFire SoC needs a custom implementation of top_of_ram(), so stop > using the generic CPU & create a custom CPU instead. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/Kconfig | 1 + > arch/riscv/cpu/mpfs/Kconfig | 16 +++++++++++ > arch/riscv/cpu/mpfs/Makefile | 6 ++++ > arch/riscv/cpu/mpfs/cpu.c | 22 +++++++++++++++ > arch/riscv/cpu/mpfs/dram.c | 38 ++++++++++++++++++++++++++ > arch/riscv/include/asm/arch-mpfs/clk.h | 8 ++++++ > board/microchip/mpfs_generic/Kconfig | 4 +-- > 7 files changed, 93 insertions(+), 2 deletions(-) > create mode 100644 arch/riscv/cpu/mpfs/Kconfig > create mode 100644 arch/riscv/cpu/mpfs/Makefile > create mode 100644 arch/riscv/cpu/mpfs/cpu.c The cpu.c file only contains "cleanup_before_linux" and seems identical with the one provided in arch/riscv/cpu/generic/cpu.c. Other than that, LGTM. If you don't mind, I could fix this on my side that you don't need to resend the patchset again. Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] riscv: create a custom CPU implementation for PolarFire SoC 2025-12-04 7:45 ` Leo Liang @ 2025-12-08 12:10 ` Jamie.Gibbons 2025-12-09 3:17 ` Leo Liang 0 siblings, 1 reply; 6+ messages in thread From: Jamie.Gibbons @ 2025-12-08 12:10 UTC (permalink / raw) To: ycliang Cc: ziyao, u-boot, trini, Conor.Dooley, Valentina.FernandezAlanis, junhui.liu, rick Hi Leo, On Thu, 2025-12-04 at 15:45 +0800, Leo Liang wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know > the content is safe > > Hi Jamie, > > On Wed, Nov 19, 2025 at 12:38:42PM +0000, Jamie Gibbons wrote: > > [EXTERNAL MAIL] > > > > From: Conor Dooley <conor.dooley@microchip.com> > > > > PolarFire SoC needs a custom implementation of top_of_ram(), so stop > > using the generic CPU & create a custom CPU instead. > > > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > --- > > arch/riscv/Kconfig | 1 + > > arch/riscv/cpu/mpfs/Kconfig | 16 +++++++++++ > > arch/riscv/cpu/mpfs/Makefile | 6 ++++ > > arch/riscv/cpu/mpfs/cpu.c | 22 +++++++++++++++ > > arch/riscv/cpu/mpfs/dram.c | 38 > > ++++++++++++++++++++++++++ > > arch/riscv/include/asm/arch-mpfs/clk.h | 8 ++++++ > > board/microchip/mpfs_generic/Kconfig | 4 +-- > > 7 files changed, 93 insertions(+), 2 deletions(-) > > create mode 100644 arch/riscv/cpu/mpfs/Kconfig > > create mode 100644 arch/riscv/cpu/mpfs/Makefile > > create mode 100644 arch/riscv/cpu/mpfs/cpu.c > > The cpu.c file only contains "cleanup_before_linux" and seems > identical > with the one provided in arch/riscv/cpu/generic/cpu.c. > > Other than that, LGTM. > > If you don't mind, I could fix this on my side that you don't need to > resend the patchset again. > > Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Thank you for your response, review and feedback. Regarding 'mpfs/cpu.c', you're corect that it is currently identical to the generic implementation. Our intent was to provide a placeholder for any future Polarfire-specific logic and also assumed it was manditory, but if duplication is unneccessary, I'm happy for you to adjust as you see fit. In other words, if U-Boot prefers to avoid duplication and this file is not mandatory for build or architextural reasons per CPU implementation, than please go ahead and use the generic version. Thanks, Jamie. ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] riscv: create a custom CPU implementation for PolarFire SoC 2025-12-08 12:10 ` Jamie.Gibbons @ 2025-12-09 3:17 ` Leo Liang 0 siblings, 0 replies; 6+ messages in thread From: Leo Liang @ 2025-12-09 3:17 UTC (permalink / raw) To: Jamie.Gibbons Cc: ziyao, u-boot, trini, Conor.Dooley, Valentina.FernandezAlanis, junhui.liu, rick Hi Jamie, On Mon, Dec 08, 2025 at 12:10:28PM +0000, Jamie.Gibbons@microchip.com wrote: > [EXTERNAL MAIL] > > Hi Leo, > > On Thu, 2025-12-04 at 15:45 +0800, Leo Liang wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know > > the content is safe > > > > Hi Jamie, > > > > On Wed, Nov 19, 2025 at 12:38:42PM +0000, Jamie Gibbons wrote: > > > [EXTERNAL MAIL] > > > > > > From: Conor Dooley <conor.dooley@microchip.com> > > > > > > PolarFire SoC needs a custom implementation of top_of_ram(), so stop > > > using the generic CPU & create a custom CPU instead. > > > > > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > > --- > > > arch/riscv/Kconfig | 1 + > > > arch/riscv/cpu/mpfs/Kconfig | 16 +++++++++++ > > > arch/riscv/cpu/mpfs/Makefile | 6 ++++ > > > arch/riscv/cpu/mpfs/cpu.c | 22 +++++++++++++++ > > > arch/riscv/cpu/mpfs/dram.c | 38 > > > ++++++++++++++++++++++++++ > > > arch/riscv/include/asm/arch-mpfs/clk.h | 8 ++++++ > > > board/microchip/mpfs_generic/Kconfig | 4 +-- > > > 7 files changed, 93 insertions(+), 2 deletions(-) > > > create mode 100644 arch/riscv/cpu/mpfs/Kconfig > > > create mode 100644 arch/riscv/cpu/mpfs/Makefile > > > create mode 100644 arch/riscv/cpu/mpfs/cpu.c > > > > The cpu.c file only contains "cleanup_before_linux" and seems > > identical > > with the one provided in arch/riscv/cpu/generic/cpu.c. > > > > Other than that, LGTM. > > > > If you don't mind, I could fix this on my side that you don't need to > > resend the patchset again. > > > > Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> > > Thank you for your response, review and feedback. > > Regarding 'mpfs/cpu.c', you're corect that it is currently identical to > the generic implementation. Our intent was to provide a placeholder for > any future Polarfire-specific logic and also assumed it was manditory, > but if duplication is unneccessary, I'm happy for you to adjust as you > see fit. > > In other words, if U-Boot prefers to avoid duplication and this file is > not mandatory for build or architextural reasons per CPU implementation, > than please go ahead and use the generic version. Got it! Thanks for the explanation. I’ve updated it to use the generic implementation. If any Polarfire-specific logic is needed in the future, we can add this file back at that time. Best regards, Leo > > Thanks, > Jamie. > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] riscv: mpfs: move SoC level options to the CPU Kconfig 2025-11-19 12:38 [PATCH 0/2] Add MPFS CPU Implementation Jamie Gibbons 2025-11-19 12:38 ` [PATCH 1/2] riscv: create a custom CPU implementation for PolarFire SoC Jamie Gibbons @ 2025-11-19 12:38 ` Jamie Gibbons 1 sibling, 0 replies; 6+ messages in thread From: Jamie Gibbons @ 2025-11-19 12:38 UTC (permalink / raw) To: u-boot Cc: Conor Dooley, Valentina Fernandez Alanis, Tom Rini, Leo, Rick Chen, Yao Zi, Junhui Liu, jamie.gibbons From: Conor Dooley <conor.dooley@microchip.com> There are multiple boards that use the PolarFire SoC, so extract the Kconfig sections that are determined at a CPU level from the board Kconfigs now that we have a CPU Kconfig. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- arch/riscv/cpu/mpfs/Kconfig | 17 +++++++++++++++++ board/microchip/mpfs_generic/Kconfig | 20 -------------------- 2 files changed, 17 insertions(+), 20 deletions(-) diff --git a/arch/riscv/cpu/mpfs/Kconfig b/arch/riscv/cpu/mpfs/Kconfig index 3e99c1aae38..bcf1ede818b 100644 --- a/arch/riscv/cpu/mpfs/Kconfig +++ b/arch/riscv/cpu/mpfs/Kconfig @@ -14,3 +14,20 @@ config MICROCHIP_MPFS imply SPL_LOAD_FIT imply REGMAP imply SYSCON + imply CLK_CCF + imply CLK_MPFS + imply SYS_NS16550 + imply MACB + imply MII + imply CMD_I2C + imply DM_I2C + imply SYS_I2C_MICROCHIP + imply MMC + imply MMC_WRITE + imply MMC_SDHCI + imply MMC_SDHCI_CADENCE + imply MMC_SDHCI_ADMA + imply MMC_HS200_SUPPORT + imply SPI + imply DM_SPI + imply MICROCHIP_QSPI diff --git a/board/microchip/mpfs_generic/Kconfig b/board/microchip/mpfs_generic/Kconfig index 49663a4c562..d38e56c742d 100644 --- a/board/microchip/mpfs_generic/Kconfig +++ b/board/microchip/mpfs_generic/Kconfig @@ -22,11 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_EARLY_INIT_F select BOARD_LATE_INIT imply SMP - imply CLK_CCF - imply CLK_MPFS - imply REGMAP - imply SYSCON - imply SYS_NS16550 imply CMD_DHCP imply CMD_EXT2 imply CMD_EXT4 @@ -39,23 +34,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply EFI_PARTITION imply IP_DYN imply ISO_PARTITION - imply MACB - imply MII imply PHY_LIB imply PHY_VITESSE - imply MMC - imply MMC_WRITE - imply MMC_SDHCI - imply MMC_SDHCI_CADENCE - imply MMC_SDHCI_ADMA - imply MMC_HS200_SUPPORT - imply CMD_I2C - imply DM_I2C - imply SYS_I2C_MICROCHIP - imply MTD - imply SPI - imply DM_SPI - imply MICROCHIP_COREQSPI imply MTD_SPI_NAND imply CMD_MTD imply CMD_MTDPARTS -- 2.43.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-12-09 3:40 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-11-19 12:38 [PATCH 0/2] Add MPFS CPU Implementation Jamie Gibbons 2025-11-19 12:38 ` [PATCH 1/2] riscv: create a custom CPU implementation for PolarFire SoC Jamie Gibbons 2025-12-04 7:45 ` Leo Liang 2025-12-08 12:10 ` Jamie.Gibbons 2025-12-09 3:17 ` Leo Liang 2025-11-19 12:38 ` [PATCH 2/2] riscv: mpfs: move SoC level options to the CPU Kconfig Jamie Gibbons
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