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From: Niklas Cassel <cassel@kernel.org>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	"Val Packett" <val@packett.cool>
Cc: "Jingoo Han" <jingoohan1@gmail.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"FUKAUMI Naoki" <naoki@radxa.com>,
	linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org,
	linux-arm-msm@vger.kernel.org
Subject: Re: [PATCH v2] PCI: dwc: Make Link Up IRQ logic handle already powered on PCIe switches
Date: Tue, 9 Dec 2025 08:45:33 +0100	[thread overview]
Message-ID: <aTfTnZfLDlt24ZKw@ryzen> (raw)
In-Reply-To: <5cdf685c-5a37-1b65-3e87-9262f3ed7bd4@linux.intel.com>

Hello Ilpo,

On Tue, Dec 09, 2025 at 09:11:37AM +0200, Ilpo Järvinen wrote:
> 
> Now this patch looks interesting (and managed to catch my attention 
> despite being a controllers/ patch).
> 
> You're only talking about bus number allocations here but we did hit a 
> similar problem with bridge window allocations where not enough 
> information is available at the time of the initial scan + resource 
> allocation (currently it is one of the issues that prevents fixing one 
> resource overlap bug):
> 
> https://lore.kernel.org/linux-pci/8f9c9950-1612-6e2d-388a-ce69cf3aae1a@linux.intel.com/

I'm quite sure that Val's problem will be solved by applying:
https://lore.kernel.org/linux-pci/20251124-pci-pwrctrl-rework-v1-0-78a72627683d@oss.qualcomm.com/

If not, he could try applying the above series, and then this patch on top.


Kind regards,
Niklas



WARNING: multiple messages have this Message-ID (diff)
From: Niklas Cassel <cassel@kernel.org>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	"Val Packett" <val@packett.cool>
Cc: "Jingoo Han" <jingoohan1@gmail.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"FUKAUMI Naoki" <naoki@radxa.com>,
	linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org,
	linux-arm-msm@vger.kernel.org
Subject: Re: [PATCH v2] PCI: dwc: Make Link Up IRQ logic handle already powered on PCIe switches
Date: Tue, 9 Dec 2025 08:45:33 +0100	[thread overview]
Message-ID: <aTfTnZfLDlt24ZKw@ryzen> (raw)
In-Reply-To: <5cdf685c-5a37-1b65-3e87-9262f3ed7bd4@linux.intel.com>

Hello Ilpo,

On Tue, Dec 09, 2025 at 09:11:37AM +0200, Ilpo Järvinen wrote:
> 
> Now this patch looks interesting (and managed to catch my attention 
> despite being a controllers/ patch).
> 
> You're only talking about bus number allocations here but we did hit a 
> similar problem with bridge window allocations where not enough 
> information is available at the time of the initial scan + resource 
> allocation (currently it is one of the issues that prevents fixing one 
> resource overlap bug):
> 
> https://lore.kernel.org/linux-pci/8f9c9950-1612-6e2d-388a-ce69cf3aae1a@linux.intel.com/

I'm quite sure that Val's problem will be solved by applying:
https://lore.kernel.org/linux-pci/20251124-pci-pwrctrl-rework-v1-0-78a72627683d@oss.qualcomm.com/

If not, he could try applying the above series, and then this patch on top.


Kind regards,
Niklas


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

  reply	other threads:[~2025-12-09  7:45 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-01  6:36 [PATCH v2] PCI: dwc: Make Link Up IRQ logic handle already powered on PCIe switches Niklas Cassel
2025-12-01  6:36 ` Niklas Cassel
2025-12-01  6:40 ` Niklas Cassel
2025-12-01  6:40   ` Niklas Cassel
2025-12-08  5:45 ` Niklas Cassel
2025-12-08  5:45   ` Niklas Cassel
2025-12-08  6:20 ` Krishna Chaitanya Chundru
2025-12-08  6:20   ` Krishna Chaitanya Chundru
2025-12-09  5:12   ` Niklas Cassel
2025-12-09  5:12     ` Niklas Cassel
2025-12-09  5:27     ` Krishna Chaitanya Chundru
2025-12-09  5:27       ` Krishna Chaitanya Chundru
2025-12-09  5:36       ` Niklas Cassel
2025-12-09  5:36         ` Niklas Cassel
2025-12-12  3:52         ` Manivannan Sadhasivam
2025-12-12  3:52           ` Manivannan Sadhasivam
2025-12-12  6:37           ` Niklas Cassel
2025-12-12  6:37             ` Niklas Cassel
2025-12-22  6:15             ` Manivannan Sadhasivam
2025-12-22  6:15               ` Manivannan Sadhasivam
2025-12-09  7:11 ` Ilpo Järvinen
2025-12-09  7:11   ` Ilpo Järvinen
2025-12-09  7:45   ` Niklas Cassel [this message]
2025-12-09  7:45     ` Niklas Cassel

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