[PATCH v2 0/8] hw: Preparatory cleanups previous to remove DEVICE_NATIVE_ENDIAN

[PATCH v2 0/8] hw: Preparatory cleanups previous to remove DEVICE_NATIVE_ENDIAN

[Philippe Mathieu-Daudé]

We want to remove the bogus DEVICE_NATIVE_ENDIAN definition,
by making it explicit (either big or little).

I'll follow with one series for each architecture. These
devices seem used by more than one, so I took them apart.

Also remove from rust API ASAP.

tag: https://gitlab.com/philmd/qemu/-/tags/endian_misc_hw-v2
CI: https://gitlab.com/philmd/qemu/-/pipelines/2231223066

Philippe Mathieu-Daudé (8):
  hw/arm/Kconfig: Have FSL_IMX6UL SoC select IMX_USBPHY
  hw/net/opencores: Clarify MMIO read/write handlers expect 32-bit
    access
  hw/char/serial: Let compiler pick serial_mm_ops[] array length
  hw/misc/pvpanic: Expose MMIO interface as little-endian
  hw/timer/hpet: Mark implementation as being little-endian
  hw/char/pl011: Mark implementation as being little-endian
  rust/system: Stop exposing bogus DEVICE_NATIVE_ENDIAN symbol
  target/hexagon: Include missing 'cpu.h' header in 'internal.h'

 target/hexagon/internal.h        |  2 +-
 hw/char/pl011.c                  |  2 +-
 hw/char/serial-mm.c              |  2 +-
 hw/misc/pvpanic.c                |  1 +
 hw/net/opencores_eth.c           | 15 +++++++++------
 hw/timer/hpet.c                  |  2 +-
 hw/arm/Kconfig                   |  1 +
 hw/usb/Kconfig                   |  1 -
 rust/hw/char/pl011/src/device.rs |  2 +-
 rust/hw/timer/hpet/src/device.rs |  2 +-
 rust/system/src/memory.rs        |  6 ------
 11 files changed, 17 insertions(+), 19 deletions(-)

-- 
2.52.0

[PATCH v2 1/8] hw/arm/Kconfig: Have FSL_IMX6UL SoC select IMX_USBPHY

[Philippe Mathieu-Daudé]

Since commit 17372bd812d, the SoC used by the mcimx6ul-evk
machine requires the IMX USB PHY component.
As this component is only used by 2 machines, do not select
it by default (it will be automatically  selected when
necessary).

Fixes: 17372bd812d ("hw/arm/fsl-imx6ul: Wire up USB controllers")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
---
 hw/arm/Kconfig | 1 +
 hw/usb/Kconfig | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 78775063840..97d747e2062 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -638,6 +638,7 @@ config FSL_IMX6UL
     select IMX
     select IMX_FEC
     select IMX_I2C
+    select IMX_USBPHY
     select WDT_IMX2
     select SDHCI
     select USB_CHIPIDEA
diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
index 69c663be52f..de95686720c 100644
--- a/hw/usb/Kconfig
+++ b/hw/usb/Kconfig
@@ -132,7 +132,6 @@ config USB_CANOKEY
 
 config IMX_USBPHY
     bool
-    default y
     depends on USB
 
 config USB_DWC3
-- 
2.52.0

[PATCH v2 2/8] hw/net/opencores: Clarify MMIO read/write handlers expect 32-bit access

[Philippe Mathieu-Daudé]

The read/write handlers access array of 32-bit register by index:

 277 struct OpenEthState {
  ..
 287     uint32_t regs[REG_MAX];
  ..
 291 };

 546 static uint64_t open_eth_reg_read(void *opaque,
 547                                   hwaddr addr, unsigned int size)
 548 {
  ..
 551     OpenEthState *s = opaque;
 552     unsigned idx = addr / 4;
  ..
 559             v = s->regs[idx];
  ..
 563     return v;
 564 }

This is a 32-bit implementation. Make that explicit in the
MemoryRegionOps structure (this doesn't change the maximum
access size, which -- being unset -- is 64-bit).

Move the structure just after the handlers to ease code review.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/net/opencores_eth.c | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/hw/net/opencores_eth.c b/hw/net/opencores_eth.c
index 7e955c01322..bc4565a9a49 100644
--- a/hw/net/opencores_eth.c
+++ b/hw/net/opencores_eth.c
@@ -682,6 +682,15 @@ static void open_eth_reg_write(void *opaque,
     }
 }
 
+static const MemoryRegionOps open_eth_reg_ops = {
+    .read = open_eth_reg_read,
+    .write = open_eth_reg_write,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
+
 static uint64_t open_eth_desc_read(void *opaque,
         hwaddr addr, unsigned int size)
 {
@@ -705,12 +714,6 @@ static void open_eth_desc_write(void *opaque,
     open_eth_check_start_xmit(s);
 }
 
-
-static const MemoryRegionOps open_eth_reg_ops = {
-    .read = open_eth_reg_read,
-    .write = open_eth_reg_write,
-};
-
 static const MemoryRegionOps open_eth_desc_ops = {
     .read = open_eth_desc_read,
     .write = open_eth_desc_write,
-- 
2.52.0

[PATCH v2 3/8] hw/char/serial: Let compiler pick serial_mm_ops[] array length

[Philippe Mathieu-Daudé]

No need to enforce the MemoryRegionOps array length.
We index by device_endian enum, the compiler will easily
pick the correct length. Besides, this allow further
adjustments in the device_endian enum itself.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/char/serial-mm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/char/serial-mm.c b/hw/char/serial-mm.c
index 13aba780ec5..ce5b589c3fd 100644
--- a/hw/char/serial-mm.c
+++ b/hw/char/serial-mm.c
@@ -44,7 +44,7 @@ static void serial_mm_write(void *opaque, hwaddr addr,
     serial_io_ops.write(&s->serial, addr >> s->regshift, value, 1);
 }
 
-static const MemoryRegionOps serial_mm_ops[3] = {
+static const MemoryRegionOps serial_mm_ops[] = {
     [DEVICE_NATIVE_ENDIAN] = {
         .read = serial_mm_read,
         .write = serial_mm_write,
-- 
2.52.0

[PATCH v2 4/8] hw/misc/pvpanic: Expose MMIO interface as little-endian

[Philippe Mathieu-Daudé]

Make the PVPanic MMIO interface behave like the ISA and PCI
variants: access it using little endianness.

Fixes: a89607c4d0e ("hw/misc/pvpanic: Add MMIO interface")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/misc/pvpanic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/misc/pvpanic.c b/hw/misc/pvpanic.c
index c83247c4087..3e60b226e18 100644
--- a/hw/misc/pvpanic.c
+++ b/hw/misc/pvpanic.c
@@ -62,6 +62,7 @@ static void pvpanic_write(void *opaque, hwaddr addr, uint64_t val,
 }
 
 static const MemoryRegionOps pvpanic_ops = {
+    .endianness = DEVICE_LITTLE_ENDIAN,
     .read = pvpanic_read,
     .write = pvpanic_write,
     .impl = {
-- 
2.52.0

[PATCH v2 5/8] hw/timer/hpet: Mark implementation as being little-endian

[Philippe Mathieu-Daudé]

The HPET component is only built / used by X86 targets, which
are only built in little endianness. Thus we only ever built
as little endian, never testing the big-endian possibility of
the DEVICE_NATIVE_ENDIAN definition. Simplify by only keeping
the little endian variant.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/timer/hpet.c                  | 2 +-
 rust/hw/timer/hpet/src/device.rs | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
index 1acba4fa9db..bfad626d5e1 100644
--- a/hw/timer/hpet.c
+++ b/hw/timer/hpet.c
@@ -648,7 +648,7 @@ static const MemoryRegionOps hpet_ram_ops = {
         .min_access_size = 4,
         .max_access_size = 8,
     },
-    .endianness = DEVICE_NATIVE_ENDIAN,
+    .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
 static void hpet_reset(DeviceState *d)
diff --git a/rust/hw/timer/hpet/src/device.rs b/rust/hw/timer/hpet/src/device.rs
index 3564aa79c6e..4f4be84115e 100644
--- a/rust/hw/timer/hpet/src/device.rs
+++ b/rust/hw/timer/hpet/src/device.rs
@@ -708,7 +708,7 @@ unsafe fn init(mut this: ParentInit<Self>) {
             MemoryRegionOpsBuilder::<HPETState>::new()
                 .read(&HPETState::read)
                 .write(&HPETState::write)
-                .native_endian()
+                .little_endian()
                 .valid_sizes(4, 8)
                 .impl_sizes(4, 8)
                 .build();
-- 
2.52.0

[PATCH v2 6/8] hw/char/pl011: Mark implementation as being little-endian

[Philippe Mathieu-Daudé]

The PL011 component is only built / used by ARM targets, which
are only built in little endianness. Thus we only ever built
as little endian, never testing the big-endian possibility of
the DEVICE_NATIVE_ENDIAN definition. Simplify by only keeping
the little endian variant.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/char/pl011.c                  | 2 +-
 rust/hw/char/pl011/src/device.rs | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 01335d9437d..97cd9bd4c54 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -538,7 +538,7 @@ static void pl011_clock_update(void *opaque, ClockEvent event)
 static const MemoryRegionOps pl011_ops = {
     .read = pl011_read,
     .write = pl011_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
+    .endianness = DEVICE_LITTLE_ENDIAN,
     .impl.min_access_size = 4,
     .impl.max_access_size = 4,
 };
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs
index 04155dabe1a..a6227a99f30 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -495,7 +495,7 @@ unsafe fn init(mut this: ParentInit<Self>) {
         static PL011_OPS: MemoryRegionOps<PL011State> = MemoryRegionOpsBuilder::<PL011State>::new()
             .read(&PL011State::read)
             .write(&PL011State::write)
-            .native_endian()
+            .little_endian()
             .impl_sizes(4, 4)
             .build();
 
-- 
2.52.0

[PATCH v2 7/8] rust/system: Stop exposing bogus DEVICE_NATIVE_ENDIAN symbol

[Philippe Mathieu-Daudé]

We want to remove the bogus DEVICE_NATIVE_ENDIAN definition
(by only having it explicit, either big or little one). Stop
exposing it to rust devices to avoid it spreading further.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 rust/system/src/memory.rs | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/rust/system/src/memory.rs b/rust/system/src/memory.rs
index 4b3316bf767..4e06c16a0b5 100644
--- a/rust/system/src/memory.rs
+++ b/rust/system/src/memory.rs
@@ -78,12 +78,6 @@ pub const fn little_endian(mut self) -> Self {
         self
     }
 
-    #[must_use]
-    pub const fn native_endian(mut self) -> Self {
-        self.0.endianness = device_endian::DEVICE_NATIVE_ENDIAN;
-        self
-    }
-
     #[must_use]
     pub const fn valid_sizes(mut self, min: u32, max: u32) -> Self {
         self.0.valid.min_access_size = min;
-- 
2.52.0

[PATCH v2 8/8] target/hexagon: Include missing 'cpu.h' header in 'internal.h'

[Philippe Mathieu-Daudé]

Both CPUHexagonState and TOTAL_PER_THREAD_REGS are defined
in "cpu.h" which is luckily indirectly included. However when
refactoring unrelated files we get:

  In file included from target/hexagon/helper.h:18,
                   from include/exec/helper-proto.h.inc:56,
                   from include/exec/helper-proto.h:13,
                   from target/hexagon/op_helper.c:22:
  target/hexagon/internal.h: At top level:
  target/hexagon/internal.h:29:25: error: unknown type name ‘CPUHexagonState’; did you mean ‘CPUPluginState’?
     29 | void hexagon_debug_vreg(CPUHexagonState *env, int regnum);
        |                         ^~~~~~~~~~~~~~~
        |                         CPUPluginState
  target/hexagon/internal.h:30:25: error: unknown type name ‘CPUHexagonState’; did you mean ‘CPUPluginState’?
     30 | void hexagon_debug_qreg(CPUHexagonState *env, int regnum);
        |                         ^~~~~~~~~~~~~~~
        |                         CPUPluginState
  target/hexagon/internal.h:31:20: error: unknown type name ‘CPUHexagonState’; did you mean ‘CPUPluginState’?
     31 | void hexagon_debug(CPUHexagonState *env);
        |                    ^~~~~~~~~~~~~~~
        |                    CPUPluginState
  target/hexagon/internal.h:33:44: error: ‘TOTAL_PER_THREAD_REGS’ undeclared here (not in a function)
     33 | extern const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS];
        |                                            ^~~~~~~~~~~~~~~~~~~~~

Fix that by including the missing header.

We don't need the "qemu/log.h" since commit 0cb73cb5a02 ("target/hexagon:
Remove HEX_DEBUG/HEX_DEBUG_LOG"): remove it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/internal.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h
index 32e96f00d97..5fc837ae229 100644
--- a/target/hexagon/internal.h
+++ b/target/hexagon/internal.h
@@ -18,7 +18,7 @@
 #ifndef HEXAGON_INTERNAL_H
 #define HEXAGON_INTERNAL_H
 
-#include "qemu/log.h"
+#include "target/hexagon/cpu.h"
 
 int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-- 
2.52.0

Re: [PATCH v2 6/8] hw/char/pl011: Mark implementation as being little-endian

[Manos Pitsidianakis]

On Wed, Dec 24, 2025 at 3:47 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> The PL011 component is only built / used by ARM targets, which
> are only built in little endianness. Thus we only ever built
> as little endian, never testing the big-endian possibility of
> the DEVICE_NATIVE_ENDIAN definition. Simplify by only keeping
> the little endian variant.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---

FWIW

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  hw/char/pl011.c                  | 2 +-
>  rust/hw/char/pl011/src/device.rs | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/char/pl011.c b/hw/char/pl011.c
> index 01335d9437d..97cd9bd4c54 100644
> --- a/hw/char/pl011.c
> +++ b/hw/char/pl011.c
> @@ -538,7 +538,7 @@ static void pl011_clock_update(void *opaque, ClockEvent event)
>  static const MemoryRegionOps pl011_ops = {
>      .read = pl011_read,
>      .write = pl011_write,
> -    .endianness = DEVICE_NATIVE_ENDIAN,
> +    .endianness = DEVICE_LITTLE_ENDIAN,
>      .impl.min_access_size = 4,
>      .impl.max_access_size = 4,
>  };
> diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs
> index 04155dabe1a..a6227a99f30 100644
> --- a/rust/hw/char/pl011/src/device.rs
> +++ b/rust/hw/char/pl011/src/device.rs
> @@ -495,7 +495,7 @@ unsafe fn init(mut this: ParentInit<Self>) {
>          static PL011_OPS: MemoryRegionOps<PL011State> = MemoryRegionOpsBuilder::<PL011State>::new()
>              .read(&PL011State::read)
>              .write(&PL011State::write)
> -            .native_endian()
> +            .little_endian()
>              .impl_sizes(4, 4)
>              .build();
>
> --
> 2.52.0
>

Re: [PATCH v2 7/8] rust/system: Stop exposing bogus DEVICE_NATIVE_ENDIAN symbol

[Manos Pitsidianakis]

On Wed, Dec 24, 2025 at 3:47 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> We want to remove the bogus DEVICE_NATIVE_ENDIAN definition
> (by only having it explicit, either big or little one). Stop
> exposing it to rust devices to avoid it spreading further.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  rust/system/src/memory.rs | 6 ------
>  1 file changed, 6 deletions(-)
>
> diff --git a/rust/system/src/memory.rs b/rust/system/src/memory.rs
> index 4b3316bf767..4e06c16a0b5 100644
> --- a/rust/system/src/memory.rs
> +++ b/rust/system/src/memory.rs
> @@ -78,12 +78,6 @@ pub const fn little_endian(mut self) -> Self {
>          self
>      }
>
> -    #[must_use]
> -    pub const fn native_endian(mut self) -> Self {
> -        self.0.endianness = device_endian::DEVICE_NATIVE_ENDIAN;
> -        self
> -    }
> -
>      #[must_use]
>      pub const fn valid_sizes(mut self, min: u32, max: u32) -> Self {
>          self.0.valid.min_access_size = min;
> --
> 2.52.0
>

Re: [PATCH v2 4/8] hw/misc/pvpanic: Expose MMIO interface as little-endian

[Philippe Mathieu-Daudé]

+Alex/Phil

On 24/12/25 14:46, Philippe Mathieu-Daudé wrote:
> Make the PVPanic MMIO interface behave like the ISA and PCI
> variants: access it using little endianness.
> 
> Fixes: a89607c4d0e ("hw/misc/pvpanic: Add MMIO interface")
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/misc/pvpanic.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/hw/misc/pvpanic.c b/hw/misc/pvpanic.c
> index c83247c4087..3e60b226e18 100644
> --- a/hw/misc/pvpanic.c
> +++ b/hw/misc/pvpanic.c
> @@ -62,6 +62,7 @@ static void pvpanic_write(void *opaque, hwaddr addr, uint64_t val,
>   }
>   
>   static const MemoryRegionOps pvpanic_ops = {
> +    .endianness = DEVICE_LITTLE_ENDIAN,
>       .read = pvpanic_read,
>       .write = pvpanic_write,
>       .impl = {

Re: [PATCH v2 4/8] hw/misc/pvpanic: Expose MMIO interface as little-endian

[Manos Pitsidianakis]

On Wed, Dec 24, 2025 at 3:47 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Make the PVPanic MMIO interface behave like the ISA and PCI
> variants: access it using little endianness.
>
> Fixes: a89607c4d0e ("hw/misc/pvpanic: Add MMIO interface")
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>

>  hw/misc/pvpanic.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/hw/misc/pvpanic.c b/hw/misc/pvpanic.c
> index c83247c4087..3e60b226e18 100644
> --- a/hw/misc/pvpanic.c
> +++ b/hw/misc/pvpanic.c
> @@ -62,6 +62,7 @@ static void pvpanic_write(void *opaque, hwaddr addr, uint64_t val,
>  }
>
>  static const MemoryRegionOps pvpanic_ops = {
> +    .endianness = DEVICE_LITTLE_ENDIAN,
>      .read = pvpanic_read,
>      .write = pvpanic_write,
>      .impl = {
> --
> 2.52.0
>

Re: [PATCH v2 5/8] hw/timer/hpet: Mark implementation as being little-endian

[Zhao Liu]

On Wed, Dec 24, 2025 at 02:46:41PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Wed, 24 Dec 2025 14:46:41 +0100
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: [PATCH v2 5/8] hw/timer/hpet: Mark implementation as being
>  little-endian
> X-Mailer: git-send-email 2.52.0
> 
> The HPET component is only built / used by X86 targets, which
> are only built in little endianness. Thus we only ever built
> as little endian, never testing the big-endian possibility of
> the DEVICE_NATIVE_ENDIAN definition. Simplify by only keeping
> the little endian variant.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  hw/timer/hpet.c                  | 2 +-
>  rust/hw/timer/hpet/src/device.rs | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Re: [PATCH v2 6/8] hw/char/pl011: Mark implementation as being little-endian

[Zhao Liu]

On Wed, Dec 24, 2025 at 02:46:42PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Wed, 24 Dec 2025 14:46:42 +0100
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: [PATCH v2 6/8] hw/char/pl011: Mark implementation as being
>  little-endian
> X-Mailer: git-send-email 2.52.0
> 
> The PL011 component is only built / used by ARM targets, which
> are only built in little endianness. Thus we only ever built
> as little endian, never testing the big-endian possibility of
> the DEVICE_NATIVE_ENDIAN definition. Simplify by only keeping
> the little endian variant.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  hw/char/pl011.c                  | 2 +-
>  rust/hw/char/pl011/src/device.rs | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Re: [PATCH v2 7/8] rust/system: Stop exposing bogus DEVICE_NATIVE_ENDIAN symbol

[Zhao Liu]

On Wed, Dec 24, 2025 at 02:46:43PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Wed, 24 Dec 2025 14:46:43 +0100
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: [PATCH v2 7/8] rust/system: Stop exposing bogus
>  DEVICE_NATIVE_ENDIAN symbol
> X-Mailer: git-send-email 2.52.0
> 
> We want to remove the bogus DEVICE_NATIVE_ENDIAN definition
> (by only having it explicit, either big or little one). Stop
> exposing it to rust devices to avoid it spreading further.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  rust/system/src/memory.rs | 6 ------
>  1 file changed, 6 deletions(-)

Good. I suppose this could help simplify vm-memory support.

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Re: [PATCH v2 1/8] hw/arm/Kconfig: Have FSL_IMX6UL SoC select IMX_USBPHY

[Richard Henderson]

On 12/25/25 00:46, Philippe Mathieu-Daudé wrote:
> Since commit 17372bd812d, the SoC used by the mcimx6ul-evk
> machine requires the IMX USB PHY component.
> As this component is only used by 2 machines, do not select
> it by default (it will be automatically  selected when
> necessary).
> 
> Fixes: 17372bd812d ("hw/arm/fsl-imx6ul: Wire up USB controllers")
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> Reviewed-by: Thomas Huth<thuth@redhat.com>
> ---
>   hw/arm/Kconfig | 1 +
>   hw/usb/Kconfig | 1 -
>   2 files changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 0/8] hw: Preparatory cleanups previous to remove DEVICE_NATIVE_ENDIAN

[Philippe Mathieu-Daudé]

On 24/12/25 14:46, Philippe Mathieu-Daudé wrote:

> Philippe Mathieu-Daudé (8):
>    hw/arm/Kconfig: Have FSL_IMX6UL SoC select IMX_USBPHY
>    hw/net/opencores: Clarify MMIO read/write handlers expect 32-bit
>      access
>    hw/char/serial: Let compiler pick serial_mm_ops[] array length
>    hw/misc/pvpanic: Expose MMIO interface as little-endian
>    hw/timer/hpet: Mark implementation as being little-endian
>    hw/char/pl011: Mark implementation as being little-endian
>    rust/system: Stop exposing bogus DEVICE_NATIVE_ENDIAN symbol
>    target/hexagon: Include missing 'cpu.h' header in 'internal.h'

Series queued.