From: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
To: Vinod Koul <vkoul@kernel.org>
Cc: conor@kernel.org, gregkh@linuxfoundation.org, pjw@kernel.org,
palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
neil.armstrong@linaro.org, krzk+dt@kernel.org,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
linux-usb@vger.kernel.org
Subject: Re: [PATCH 4/5] phy: usb: Add driver for Canaan K230 USB 2.0 PHY
Date: Sun, 4 Jan 2026 09:37:07 +0800 [thread overview]
Message-ID: <aVnEQ4+coOd397Hk@duge-virtual-machine> (raw)
In-Reply-To: <aVZQ4YVXGryHz0ds@vaman>
On Thu, Jan 01, 2026 at 04:18:01PM +0530, Vinod Koul wrote:
> On 30-12-25, 10:37, Jiayu Du wrote:
> > Add driver for the USB 2.0 PHY in Canaan K230 SoC, which supports PHY
> > initialization, power management and USB mode switching.
> >
> > Add Kconfig/Makefile under drivers/phy/canaan/.
> >
> > Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
...
> > +#define TEST_CTL3_OFFSET 0x0C
>
> Lowercase hex values please.. do you need a test register :-)
Sorry, I will convert the hex to lowercase.
In the TRM manual, the registers are named TEST_CTL and they are
used to describe the otg0 phy port control. The TRM manual is here[1].
The description of this register is located on page 1015.
Therefore, I have retained the names as stated in the TRM manual.
Link:
https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E7%A1%AC%E4%BB%B6%E6%96%87%E6%A1%A3/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
[1]
> > + FIELD_PREP(USB_CTL0_PLLPTUNE_MASK, 0xC) | \
>
> lower hex here and rest
I will fix it in v2.
>
> > + ret = regmap_update_bits(phy->regmap, phy->reg_test_offset +
> > + TEST_CTL3_OFFSET, val, val);
>
> so we are writing to a test register..?
As I mentioned above, this is actually otg0 phy port control
register.
> > + int ret;
> > + u32 offset;
> > + struct regmap *regmap;
> > + struct phy *generic_phy;
> > + struct k230_usb_phy *phy;
> > + struct phy_provider *provider;
> > + struct device *dev = &pdev->dev;
>
> reverse christmas tree order would look better...
I will fix it in v2.
> > +
> > +
>
> why two lines...?
I will fix it in v2.
>
> > +MODULE_LICENSE("GPL");
> > --
> > 2.52.0
>
> --
> ~Vinod
Regards,
Jiayu Du
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
WARNING: multiple messages have this Message-ID (diff)
From: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
To: Vinod Koul <vkoul@kernel.org>
Cc: conor@kernel.org, gregkh@linuxfoundation.org, pjw@kernel.org,
palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
neil.armstrong@linaro.org, krzk+dt@kernel.org,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
linux-usb@vger.kernel.org
Subject: Re: [PATCH 4/5] phy: usb: Add driver for Canaan K230 USB 2.0 PHY
Date: Sun, 4 Jan 2026 09:37:07 +0800 [thread overview]
Message-ID: <aVnEQ4+coOd397Hk@duge-virtual-machine> (raw)
In-Reply-To: <aVZQ4YVXGryHz0ds@vaman>
On Thu, Jan 01, 2026 at 04:18:01PM +0530, Vinod Koul wrote:
> On 30-12-25, 10:37, Jiayu Du wrote:
> > Add driver for the USB 2.0 PHY in Canaan K230 SoC, which supports PHY
> > initialization, power management and USB mode switching.
> >
> > Add Kconfig/Makefile under drivers/phy/canaan/.
> >
> > Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
...
> > +#define TEST_CTL3_OFFSET 0x0C
>
> Lowercase hex values please.. do you need a test register :-)
Sorry, I will convert the hex to lowercase.
In the TRM manual, the registers are named TEST_CTL and they are
used to describe the otg0 phy port control. The TRM manual is here[1].
The description of this register is located on page 1015.
Therefore, I have retained the names as stated in the TRM manual.
Link:
https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E7%A1%AC%E4%BB%B6%E6%96%87%E6%A1%A3/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
[1]
> > + FIELD_PREP(USB_CTL0_PLLPTUNE_MASK, 0xC) | \
>
> lower hex here and rest
I will fix it in v2.
>
> > + ret = regmap_update_bits(phy->regmap, phy->reg_test_offset +
> > + TEST_CTL3_OFFSET, val, val);
>
> so we are writing to a test register..?
As I mentioned above, this is actually otg0 phy port control
register.
> > + int ret;
> > + u32 offset;
> > + struct regmap *regmap;
> > + struct phy *generic_phy;
> > + struct k230_usb_phy *phy;
> > + struct phy_provider *provider;
> > + struct device *dev = &pdev->dev;
>
> reverse christmas tree order would look better...
I will fix it in v2.
> > +
> > +
>
> why two lines...?
I will fix it in v2.
>
> > +MODULE_LICENSE("GPL");
> > --
> > 2.52.0
>
> --
> ~Vinod
Regards,
Jiayu Du
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
To: Vinod Koul <vkoul@kernel.org>
Cc: conor@kernel.org, gregkh@linuxfoundation.org, pjw@kernel.org,
palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
neil.armstrong@linaro.org, krzk+dt@kernel.org,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
linux-usb@vger.kernel.org
Subject: Re: [PATCH 4/5] phy: usb: Add driver for Canaan K230 USB 2.0 PHY
Date: Sun, 4 Jan 2026 09:37:07 +0800 [thread overview]
Message-ID: <aVnEQ4+coOd397Hk@duge-virtual-machine> (raw)
In-Reply-To: <aVZQ4YVXGryHz0ds@vaman>
On Thu, Jan 01, 2026 at 04:18:01PM +0530, Vinod Koul wrote:
> On 30-12-25, 10:37, Jiayu Du wrote:
> > Add driver for the USB 2.0 PHY in Canaan K230 SoC, which supports PHY
> > initialization, power management and USB mode switching.
> >
> > Add Kconfig/Makefile under drivers/phy/canaan/.
> >
> > Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
...
> > +#define TEST_CTL3_OFFSET 0x0C
>
> Lowercase hex values please.. do you need a test register :-)
Sorry, I will convert the hex to lowercase.
In the TRM manual, the registers are named TEST_CTL and they are
used to describe the otg0 phy port control. The TRM manual is here[1].
The description of this register is located on page 1015.
Therefore, I have retained the names as stated in the TRM manual.
Link:
https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E7%A1%AC%E4%BB%B6%E6%96%87%E6%A1%A3/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
[1]
> > + FIELD_PREP(USB_CTL0_PLLPTUNE_MASK, 0xC) | \
>
> lower hex here and rest
I will fix it in v2.
>
> > + ret = regmap_update_bits(phy->regmap, phy->reg_test_offset +
> > + TEST_CTL3_OFFSET, val, val);
>
> so we are writing to a test register..?
As I mentioned above, this is actually otg0 phy port control
register.
> > + int ret;
> > + u32 offset;
> > + struct regmap *regmap;
> > + struct phy *generic_phy;
> > + struct k230_usb_phy *phy;
> > + struct phy_provider *provider;
> > + struct device *dev = &pdev->dev;
>
> reverse christmas tree order would look better...
I will fix it in v2.
> > +
> > +
>
> why two lines...?
I will fix it in v2.
>
> > +MODULE_LICENSE("GPL");
> > --
> > 2.52.0
>
> --
> ~Vinod
Regards,
Jiayu Du
next prev parent reply other threads:[~2026-01-04 1:37 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-30 2:37 [PATCH 0/5] Add USB support for Canaan K230 Jiayu Du
2025-12-30 2:37 ` Jiayu Du
2025-12-30 2:37 ` Jiayu Du
2025-12-30 2:37 ` [PATCH 1/5] dt-bindings: phy: Add Canaan K230 USB2.0 PHY DT schema Jiayu Du
2025-12-30 2:37 ` Jiayu Du
2025-12-30 2:37 ` Jiayu Du
2025-12-30 7:36 ` Krzysztof Kozlowski
2025-12-30 7:36 ` Krzysztof Kozlowski
2025-12-30 7:36 ` Krzysztof Kozlowski
2025-12-30 9:04 ` Jiayu Du
2025-12-30 9:04 ` Jiayu Du
2025-12-30 9:04 ` Jiayu Du
2025-12-30 2:37 ` [PATCH 2/5] dt-bindings: soc: canaan: Add top syscon for Canaan K230 SoC Jiayu Du
2025-12-30 2:37 ` Jiayu Du
2025-12-30 2:37 ` Jiayu Du
2025-12-30 3:41 ` Rob Herring (Arm)
2025-12-30 3:41 ` Rob Herring (Arm)
2025-12-30 3:41 ` Rob Herring (Arm)
2025-12-30 7:39 ` Krzysztof Kozlowski
2025-12-30 7:39 ` Krzysztof Kozlowski
2025-12-30 7:39 ` Krzysztof Kozlowski
2025-12-30 13:14 ` Jiayu Du
2025-12-30 13:14 ` Jiayu Du
2025-12-30 13:14 ` Jiayu Du
2025-12-30 14:00 ` Krzysztof Kozlowski
2025-12-30 14:00 ` Krzysztof Kozlowski
2025-12-30 14:00 ` Krzysztof Kozlowski
2026-01-04 1:40 ` Jiayu Du
2026-01-04 1:40 ` Jiayu Du
2026-01-04 1:40 ` Jiayu Du
2025-12-30 2:37 ` [PATCH 3/5] dt-bindings: usb: dwc2: Add support " Jiayu Du
2025-12-30 2:37 ` Jiayu Du
2025-12-30 2:37 ` Jiayu Du
2025-12-30 3:41 ` Rob Herring (Arm)
2025-12-30 3:41 ` Rob Herring (Arm)
2025-12-30 3:41 ` Rob Herring (Arm)
2025-12-30 2:37 ` [PATCH 4/5] phy: usb: Add driver for Canaan K230 USB 2.0 PHY Jiayu Du
2025-12-30 2:37 ` Jiayu Du
2025-12-30 2:37 ` Jiayu Du
2026-01-01 10:48 ` Vinod Koul
2026-01-01 10:48 ` Vinod Koul
2026-01-01 10:48 ` Vinod Koul
2026-01-04 1:37 ` Jiayu Du [this message]
2026-01-04 1:37 ` Jiayu Du
2026-01-04 1:37 ` Jiayu Du
2025-12-30 2:37 ` [PATCH 5/5] riscv: dts: canaan: Add syscon and USB nodes for K230 Jiayu Du
2025-12-30 2:37 ` Jiayu Du
2025-12-30 2:37 ` Jiayu Du
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