From: Simon Horman <horms@kernel.org>
To: Grzegorz Nitka <grzegorz.nitka@intel.com>
Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org,
anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com,
Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Subject: Re: [Intel-wired-lan] [PATCH iwl-net] ice: fix 'adjust' timer programming for E830 devices
Date: Mon, 5 Jan 2026 16:34:41 +0000 [thread overview]
Message-ID: <aVvoIZYBivorDJkC@horms.kernel.org> (raw)
In-Reply-To: <20251218094428.1762860-1-grzegorz.nitka@intel.com>
On Thu, Dec 18, 2025 at 10:44:28AM +0100, Grzegorz Nitka wrote:
> Fix incorrect 'adjust the timer' programming sequence for E830 devices
> series. Only shadow registers GLTSYN_SHADJ were programmed in the
> current implementation. According to the specification [1], write to
> command GLTSYN_CMD register is also required with CMD field set to
> "Adjust the Time" value, for the timer adjustment to take the effect.
>
> The flow was broken for the adjustment less than S32_MAX/MIN range
> (around +/- 2 seconds). For bigger adjustment, non-atomic programming
> flow is used, involving set timer programming. Non-atomic flow is
> implemented correctly.
>
> Testing hints:
> Run command:
> phc_ctl /dev/ptpX get adj 2 get
> Expected result:
> Returned timstamps differ at least by 2 seconds
>
> [1] Intel® Ethernet Controller E830 Datasheet rev 1.3, chapter 9.7.5.4
> https://cdrdv2.intel.com/v1/dl/getContent/787353?explicitVersion=true
>
> Fixes: f00307522786 ("ice: Implement PTP support for E830 devices")
> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
Reviewed-by: Simon Horman <horms@kernel.org>
WARNING: multiple messages have this Message-ID (diff)
From: Simon Horman <horms@kernel.org>
To: Grzegorz Nitka <grzegorz.nitka@intel.com>
Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org,
anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com,
Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Subject: Re: [PATCH iwl-net] ice: fix 'adjust' timer programming for E830 devices
Date: Mon, 5 Jan 2026 16:34:41 +0000 [thread overview]
Message-ID: <aVvoIZYBivorDJkC@horms.kernel.org> (raw)
In-Reply-To: <20251218094428.1762860-1-grzegorz.nitka@intel.com>
On Thu, Dec 18, 2025 at 10:44:28AM +0100, Grzegorz Nitka wrote:
> Fix incorrect 'adjust the timer' programming sequence for E830 devices
> series. Only shadow registers GLTSYN_SHADJ were programmed in the
> current implementation. According to the specification [1], write to
> command GLTSYN_CMD register is also required with CMD field set to
> "Adjust the Time" value, for the timer adjustment to take the effect.
>
> The flow was broken for the adjustment less than S32_MAX/MIN range
> (around +/- 2 seconds). For bigger adjustment, non-atomic programming
> flow is used, involving set timer programming. Non-atomic flow is
> implemented correctly.
>
> Testing hints:
> Run command:
> phc_ctl /dev/ptpX get adj 2 get
> Expected result:
> Returned timstamps differ at least by 2 seconds
>
> [1] Intel® Ethernet Controller E830 Datasheet rev 1.3, chapter 9.7.5.4
> https://cdrdv2.intel.com/v1/dl/getContent/787353?explicitVersion=true
>
> Fixes: f00307522786 ("ice: Implement PTP support for E830 devices")
> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
Reviewed-by: Simon Horman <horms@kernel.org>
next prev parent reply other threads:[~2026-01-05 16:34 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-18 9:44 [Intel-wired-lan] [PATCH iwl-net] ice: fix 'adjust' timer programming for E830 devices Grzegorz Nitka
2025-12-18 9:44 ` Grzegorz Nitka
2026-01-05 16:34 ` Simon Horman [this message]
2026-01-05 16:34 ` Simon Horman
2026-01-07 10:09 ` [Intel-wired-lan] " Loktionov, Aleksandr
2026-01-07 10:09 ` Loktionov, Aleksandr
2026-03-25 3:09 ` [Intel-wired-lan] " Rinitha, SX
2026-03-25 3:09 ` Rinitha, SX
2026-03-25 23:43 ` Jacob Keller
2026-03-25 23:43 ` Jacob Keller
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