* [PATCH 1/3] dt-bindings: vendor-prefixes: Add 'lge,*' for LG Electronics
2026-01-08 8:22 [PATCH 0/3] arm64: dts: Initial support for LG1215 TV SoC Chanho Min
@ 2026-01-08 8:22 ` Chanho Min
2026-01-08 16:39 ` Krzysztof Kozlowski
2026-01-08 8:22 ` [PATCH 2/3] dt-bindings: arm: lge: Add compatible for LG1215 SoC and reference board Chanho Min
` (2 subsequent siblings)
3 siblings, 1 reply; 13+ messages in thread
From: Chanho Min @ 2026-01-08 8:22 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Neil Armstrong, Kever Yang, Kael D'Alcamo,
Manivannan Sadhasivam, Lad Prabhakar
Cc: Chanho Min, Gunho Lee, devicetree, linux-kernel, linux-arm-kernel
Currently 'lg,*' is used for LG Corporation, but LG Electronics uses
'lge' as vendor prefix for many of its device tree bindings
(lg1k SoCs, etc).
Add 'lge' vendor prefix entry to avoid confusion with 'lg'.
Signed-off-by: Chanho Min <chanho.min@lge.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index c7591b2aec2a..6c31fa4bee6a 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -907,6 +907,8 @@ patternProperties:
description: Lenovo Group Ltd.
"^lg,.*":
description: LG Corporation
+ "^lge,.*":
+ description: LG Electronics
"^lgphilips,.*":
description: LG Display
"^libretech,.*":
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 2/3] dt-bindings: arm: lge: Add compatible for LG1215 SoC and reference board
2026-01-08 8:22 [PATCH 0/3] arm64: dts: Initial support for LG1215 TV SoC Chanho Min
2026-01-08 8:22 ` [PATCH 1/3] dt-bindings: vendor-prefixes: Add 'lge,*' for LG Electronics Chanho Min
@ 2026-01-08 8:22 ` Chanho Min
2026-01-08 16:40 ` Krzysztof Kozlowski
2026-01-08 8:22 ` [PATCH 3/3] arm64: dts: lg: Initial support " Chanho Min
2026-01-08 16:13 ` [PATCH 0/3] arm64: dts: Initial support for LG1215 TV SoC Rob Herring
3 siblings, 1 reply; 13+ messages in thread
From: Chanho Min @ 2026-01-08 8:22 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Neil Armstrong, Kever Yang, Kael D'Alcamo,
Manivannan Sadhasivam, Lad Prabhakar
Cc: Chanho Min, Gunho Lee, devicetree, linux-kernel, linux-arm-kernel
Add compatible strings for the LG1215 SoC and its reference board
(lge,lg1215 and lge,lg1215-ref).
This SoC is the next SoC following the LG1313 series, developed
by LG Electronics.
Signed-off-by: Chanho Min <chanho.min@lge.com>
---
Documentation/devicetree/bindings/arm/lge.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/lge.yaml b/Documentation/devicetree/bindings/arm/lge.yaml
index d983ef7fcbd6..25750047131b 100644
--- a/Documentation/devicetree/bindings/arm/lge.yaml
+++ b/Documentation/devicetree/bindings/arm/lge.yaml
@@ -24,5 +24,10 @@ properties:
- const: lge,lg1313-ref
- const: lge,lg1313
+ - description: Boards with LG1215 SoC
+ items:
+ - const: lge,lg1215-ref
+ - const: lge,lg1215
+
additionalProperties: true
...
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 3/3] arm64: dts: lg: Initial support for LG1215 SoC and reference board
2026-01-08 8:22 [PATCH 0/3] arm64: dts: Initial support for LG1215 TV SoC Chanho Min
2026-01-08 8:22 ` [PATCH 1/3] dt-bindings: vendor-prefixes: Add 'lge,*' for LG Electronics Chanho Min
2026-01-08 8:22 ` [PATCH 2/3] dt-bindings: arm: lge: Add compatible for LG1215 SoC and reference board Chanho Min
@ 2026-01-08 8:22 ` Chanho Min
2026-01-08 16:43 ` Krzysztof Kozlowski
2026-01-08 16:13 ` [PATCH 0/3] arm64: dts: Initial support for LG1215 TV SoC Rob Herring
3 siblings, 1 reply; 13+ messages in thread
From: Chanho Min @ 2026-01-08 8:22 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Neil Armstrong, Kever Yang, Kael D'Alcamo,
Manivannan Sadhasivam, Lad Prabhakar
Cc: Chanho Min, Gunho Lee, devicetree, linux-kernel, linux-arm-kernel
Add initial device tree support for LG Electronics LG1215 SoC
and its reference development board.
This patch introduces:
- lg1215.dtsi : SoC level device tree include file
- lg1215-ref.dts : Reference board specific file
- Makefile update to build lg1215-ref.dtb
Currently supported minimal hardware description:
- Quad ARM Cortex-A78 CPU
- gic-400 interrupt controller
- ARMv8 architected timer
- pmu (Performance Monitoring Unit)
- pl011 UARTs
- pl080 DMA controller
- sp804 timers, sp805 watchdog timers
- Generic DWMAC ethernet controller
This is the minimal initial bring-up version. More peripherals (mmc, gpio,
pinctrl, etc.) will be added in follow-up patches.
Signed-off-by: Chanho Min <chanho.min@lge.com>
---
arch/arm64/boot/dts/lg/Makefile | 1 +
arch/arm64/boot/dts/lg/lg1215-ref.dts | 34 +++
arch/arm64/boot/dts/lg/lg1215.dtsi | 304 ++++++++++++++++++++++++++
3 files changed, 339 insertions(+)
create mode 100644 arch/arm64/boot/dts/lg/lg1215-ref.dts
create mode 100644 arch/arm64/boot/dts/lg/lg1215.dtsi
diff --git a/arch/arm64/boot/dts/lg/Makefile b/arch/arm64/boot/dts/lg/Makefile
index 4c3959e24e1b..e60a5bd35327 100644
--- a/arch/arm64/boot/dts/lg/Makefile
+++ b/arch/arm64/boot/dts/lg/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_LG1K) += lg1312-ref.dtb
dtb-$(CONFIG_ARCH_LG1K) += lg1313-ref.dtb
+dtb-$(CONFIG_ARCH_LG1K) += lg1215-ref.dtb
diff --git a/arch/arm64/boot/dts/lg/lg1215-ref.dts b/arch/arm64/boot/dts/lg/lg1215-ref.dts
new file mode 100644
index 000000000000..fd24ed450037
--- /dev/null
+++ b/arch/arm64/boot/dts/lg/lg1215-ref.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for lg1215 Reference Board.
+ *
+ * Copyright (C) 2026, LG Electronics
+ */
+
+/dts-v1/;
+
+#include "lg1215.dtsi"
+
+/ {
+ model = "LG Electronics, TV SoC LG1215 Reference Board";
+ compatible = "lge,lg1215-ref", "lge,lg1215";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x00000000 0x0 0xbc400000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/lg/lg1215.dtsi b/arch/arm64/boot/dts/lg/lg1215.dtsi
new file mode 100644
index 000000000000..2f926395ae8a
--- /dev/null
+++ b/arch/arm64/boot/dts/lg/lg1215.dtsi
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for lg1215 SoC
+ *
+ * Copyright (C) 2026, LG Electronics
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x00000000>;
+ enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x00010000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x00010000>;
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache@0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-size = <0x00040000>;
+ cache-unified;
+ next-level-cache = <&L3>;
+ };
+ };
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x00000100>;
+ enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x00010000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x00010000>;
+ next-level-cache = <&L2_1>;
+ L2_1: l2-cache@100 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-size = <0x00040000>;
+ cache-unified;
+ next-level-cache = <&L3>;
+ };
+ };
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x00000200>;
+ enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x00010000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x00010000>;
+ next-level-cache = <&L2_2>;
+ L2_2: l2-cache@200 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-size = <0x00040000>;
+ cache-unified;
+ next-level-cache = <&L3>;
+ };
+ };
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x00000300>;
+ enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x00010000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x00010000>;
+ next-level-cache = <&L2_3>;
+ L2_3: l2-cache@300 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-size = <0x00040000>;
+ cache-unified;
+ next-level-cache = <&L3>;
+ };
+ };
+ L3: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-size = <0x00100000>;
+ cache-unified;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0xc4000002>;
+ cpu_on = <0xc4000003>;
+ };
+
+ cpu0_opp_table: opp_table@0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-default {
+ opp-hz = /bits/ 64 <1600000000>;
+ };
+ };
+
+ gic: interrupt-controller@c0000000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xc0001000 0x0 0x1000>, /* GICD */
+ <0x0 0xc0002000 0x0 0x2000>, /* GICC */
+ <0x0 0xc0004000 0x0 0x2000>, /* GICH */
+ <0x0 0xc0006000 0x0 0x2000>; /* GICV */
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x0f) |
+ IRQ_TYPE_LEVEL_LOW)>;
+
+ interrupt-controller;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>,
+ <&cpu2>,
+ <&cpu3>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ clks {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clk_xtal: clk-xtal {
+ compatible = "fixed-clock";
+ clock-output-names = "xtal";
+ clock-frequency = <50000000>;
+
+ #clock-cells = <0>;
+ };
+
+ clk_bus: clk-bus {
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_xtal>;
+ clock-names = "xtal";
+ clock-output-names = "busclk";
+ clock-div = <1>;
+ clock-mult = <4>;
+
+ #clock-cells = <0>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ interrupt-parent = <&gic>;
+
+ dwmac_axi_config: dwmac-axi-config {
+ snps,rd_osr_lmt = <0x07>;
+ snps,wr_osr_lmt = <0x07>;
+ snps,blen = <0 0 16 0 0 0 0>;
+ };
+ ethernet@ca370000 {
+ compatible = "snps,dwmac";
+ reg = <0x0 0xca370000 0x0 0x2000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&clk_bus>, <&clk_bus>;
+ clock-names = "stmmaceth", "pclk";
+ max-frame-size = <1500>;
+ phy-mode = "mii";
+ snps,pbl = <2>;
+ snps,fixed-burst;
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <32>;
+ snps,axi-config = <&dwmac_axi_config>;
+ mac-address = [ 00 00 00 00 00 00 ];
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@1c {
+ compatible = "ethernet-phy-id001c.c800";
+ reg = <0x1c>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ };
+
+ amba {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ timers0: timer@fd100000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x0 0xfd100000 0x0 0x1000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
+ };
+ timers1: timer@fd110000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x0 0xfd110000 0x0 0x1000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>;
+ clock-names = "timer0clk", "timer1clk", "apb_pclk";
+ status = "disabled";
+ };
+ wdog: watchdog@fd200000 {
+ compatible = "arm,sp805", "arm,primecell";
+ reg = <0x0 0xfd200000 0x0 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ };
+ uart0: serial@fe000000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfe000000 0x0 0x1000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_bus>, <&clk_bus>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+ uart1: serial@fe100000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfe100000 0x0 0x1000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_bus>, <&clk_bus>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+ uart2: serial@fe200000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfe200000 0x0 0x1000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_bus>, <&clk_bus>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+ dma: dma@ff200000 {
+ compatible = "arm,pl080", "arm,primecell";
+ reg = <0x0 0xff200000 0x0 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_bus>;
+ clock-names = "apb_pclk";
+ };
+ };
+};
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 0/3] arm64: dts: Initial support for LG1215 TV SoC
2026-01-08 8:22 [PATCH 0/3] arm64: dts: Initial support for LG1215 TV SoC Chanho Min
` (2 preceding siblings ...)
2026-01-08 8:22 ` [PATCH 3/3] arm64: dts: lg: Initial support " Chanho Min
@ 2026-01-08 16:13 ` Rob Herring
3 siblings, 0 replies; 13+ messages in thread
From: Rob Herring @ 2026-01-08 16:13 UTC (permalink / raw)
To: Chanho Min
Cc: Neil Armstrong, Conor Dooley, devicetree, linux-arm-kernel,
Heiko Stuebner, Krzysztof Kozlowski, Kever Yang,
Manivannan Sadhasivam, linux-kernel, Gunho Lee, Kael D'Alcamo,
Lad Prabhakar
On Thu, 08 Jan 2026 17:22:10 +0900, Chanho Min wrote:
> This patch series adds initial device tree support for the LG1215
> TV SoC and its reference board.
>
> Series overview:
> 1/3 - dt-bindings: vendor-prefixes: Add 'lge' prefix for LG Electronics
> 2/3 - dt-bindings: arm: lge: Add compatible for LG1215 SoC and ref board
> 3/3 - arm64: dts: lg: Initial support for LG1215 SoC and reference board
>
> .../devicetree/bindings/arm/lge.yaml | 5 +
> .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> arch/arm64/boot/dts/lg/Makefile | 1 +
> arch/arm64/boot/dts/lg/lg1215-ref.dts | 51 +++
> arch/arm64/boot/dts/lg/lg1215.dtsi | 304 ++++++++++++++++++
> 5 files changed, 363 insertions(+)
> create mode 100644 arch/arm64/boot/dts/lg/lg1215-ref.dts
> create mode 100644 arch/arm64/boot/dts/lg/lg1215.dtsi
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: attempting to guess base-commit...
Base: tags/next-20260108 (best guess, 2/3 blobs matched)
Base: tags/next-20260108 (use --merge-base to override)
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/lg/' for 20260108082213.6545-1-chanho.min@lge.com:
arch/arm64/boot/dts/lg/lg1215-ref.dtb: / (lge,lg1215-ref): opp_table@0: 'anyOf' conditional failed, one must be fixed:
'reg' is a required property
'ranges' is a required property
from schema $id: http://devicetree.org/schemas/root-node.yaml
arch/arm64/boot/dts/lg/lg1215-ref.dtb: cpu@0 (arm,cortex-a78): Unevaluated properties are not allowed ('l2-cache@0' was unexpected)
from schema $id: http://devicetree.org/schemas/arm/cpus.yaml
arch/arm64/boot/dts/lg/lg1215-ref.dtb: cpu@100 (arm,cortex-a78): Unevaluated properties are not allowed ('l2-cache@100' was unexpected)
from schema $id: http://devicetree.org/schemas/arm/cpus.yaml
arch/arm64/boot/dts/lg/lg1215-ref.dtb: cpu@200 (arm,cortex-a78): Unevaluated properties are not allowed ('l2-cache@200' was unexpected)
from schema $id: http://devicetree.org/schemas/arm/cpus.yaml
arch/arm64/boot/dts/lg/lg1215-ref.dtb: cpu@300 (arm,cortex-a78): Unevaluated properties are not allowed ('l2-cache@300' was unexpected)
from schema $id: http://devicetree.org/schemas/arm/cpus.yaml
arch/arm64/boot/dts/lg/lg1215-ref.dtb: opp_table@0 (operating-points-v2): $nodename:0: 'opp_table@0' does not match '^opp-table(-[a-z0-9]+)?$'
from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml
arch/arm64/boot/dts/lg/lg1215-ref.dtb: opp_table@0 (operating-points-v2): Unevaluated properties are not allowed ('opp-default', 'opp-shared' were unexpected)
from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml
arch/arm64/boot/dts/lg/lg1215-ref.dtb: clk-bus (fixed-factor-clock): 'clock-names' does not match any of the regexes: '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml
arch/arm64/boot/dts/lg/lg1215-ref.dtb: soc (simple-bus): dwmac-axi-config: 'ranges' is a required property
from schema $id: http://devicetree.org/schemas/simple-bus.yaml
arch/arm64/boot/dts/lg/lg1215-ref.dtb: amba (simple-bus): $nodename:0: 'amba' does not match '^([a-z][a-z0-9\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$'
from schema $id: http://devicetree.org/schemas/simple-bus.yaml
arch/arm64/boot/dts/lg/lg1215-ref.dtb: watchdog@fd200000 (arm,sp805): clock-names:0: 'wdog_clk' was expected
from schema $id: http://devicetree.org/schemas/watchdog/arm,sp805.yaml
arch/arm64/boot/dts/lg/lg1215-ref.dtb: watchdog@fd200000 (arm,sp805): clock-names: ['apb_pclk'] is too short
from schema $id: http://devicetree.org/schemas/watchdog/arm,sp805.yaml
arch/arm64/boot/dts/lg/lg1215-ref.dtb: watchdog@fd200000 (arm,sp805): clocks: [[13]] is too short
from schema $id: http://devicetree.org/schemas/watchdog/arm,sp805.yaml
arch/arm64/boot/dts/lg/lg1215-ref.dtb: dma@ff200000 (arm,pl080): '#dma-cells' is a required property
from schema $id: http://devicetree.org/schemas/dma/arm-pl08x.yaml
arch/arm64/boot/dts/lg/lg1215-ref.dtb: dma@ff200000 (arm,pl080): $nodename:0: 'dma@ff200000' does not match '^dma-controller(@.*)?$'
from schema $id: http://devicetree.org/schemas/dma/arm-pl08x.yaml
arch/arm64/boot/dts/lg/lg1215-ref.dtb: dma@ff200000 (arm,pl080): '#dma-cells' is a required property
from schema $id: http://devicetree.org/schemas/dma/arm-pl08x.yaml
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