From: "Ahmed S. Darwish" <darwi@linutronix.de>
To: Borislav Petkov <bp@alien8.de>
Cc: Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Andrew Cooper <andrew.cooper3@citrix.com>,
Sean Christopherson <seanjc@google.com>,
David Woodhouse <dwmw2@infradead.org>,
"H. Peter Anvin" <hpa@zytor.com>,
Peter Zijlstra <peterz@infradead.org>,
Sohil Mehta <sohil.mehta@intel.com>,
John Ogness <john.ogness@linutronix.de>,
x86@kernel.org, x86-cpuid@lists.linux.dev,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v5 07/35] x86: Introduce a centralized CPUID data model
Date: Mon, 26 Jan 2026 14:04:51 +0100 [thread overview]
Message-ID: <aXdmc6F5wLthVDEU@lx-t490> (raw)
In-Reply-To: <20260116203117.GAaWqgFYTv1bHLxKV_@fat_crate.local>
Hi Boris,
On Fri, 16 Jan 2026, Borislav Petkov wrote:
>
> Btw, why are we calling them dynamic?
>
> This is confusing. Those leafs simply have multiple subleafs specified
> in ECX.
>
> Let's please not invent our own things here but simply stick to the
> nomenclature in the vendor docs.
>
> This is a very simple explanation IMO:
>
> "The information is accessed by (1) selecting the CPUID function setting
> EAX and optionally ECX for some functions,"
>
>
> and there's no talk about dynamic and whatnot.
>
...
>
> This is where the problem lies: you're calling static leaves those which
> have one subleaf and dynamic those which have multiple.
>
> But if one "static" leaf starts adding subleafs, the "static" one
> becomes "dynamic". And that's confusing. Nothing dynamic about it. You
> simply have CPUID leafs with 1 or more subleafs. And that should be the
> nomenclature we use.
>
Due to the differing leaf/subleaf output formats, at
arch/x86/include/asm/cpuid/leaf_types.h we have the storage types:
struct leaf_0x4_n { ... }; // CPUID(0x4), subleaves 0 -> n
struct leaf_0xd_0 { ... }; // CPUID(0xd), subleaf 0
struct leaf_0xd_1 { ... }; // CPUID(0xd), subleaf 1
struct leaf_0xd_n { ... }; // CPUID(0xd), subleaves 2 -> n
struct leaf_0x10_0 { ... }; // CPUID(0x10), subleaf 0
struct leaf_0x10_n { ... }; // CPUID(0x10), subleaves 1 -> n
where "n" is known at runtime.
Then, for CPUID(0xd) subleaf 0 and 1 call sites we have:
/*
* "Static" access
*/
const struct leaf_0xd_0 *ld_0;
const struct leaf_0xd_1 *ld_1;
ld_0 = cpuid_subleaf(c, 0xd, 0);
// | | └────────┐
// | └─────────┐ |
// * * *
// ld_0 = &c.cpuid.leaf_0xd_0[0];
ld_1 = cpuid_subleaf(c, 0xd, 1);
// | | └────────┐
// | └─────────┐ |
// * * *
// ld_1 = &c.cpuid.leaf_0xd_1[0];
And for CPUID(0xd) subleaves 2 to n, we have:
/*
* "Dynamic" access
*/
const struct leaf_0xd_n *ld;
for (int i = XFEATURE_SSE; i < XFEATURE_MAX; i++) {
ld = cpuid_subleaf_n(c, 0xd, i);
// | | └──────────┐
// | └─────────┐ |
// * * *
// ld = &c.cpuid.leaf_0xd_n[i];
}
Similarly, for CPUID(0x4) call sites we have:
/*
* "Dynamic" CPUID(0x4) subleaf access, 0 -> n
*/
const struct leaf_0x4_n *l4;
for (int i = 0; i < cpuid_subleaf_count(c, 0x4); i++) {
l4 = cpuid_subleaf_n(c, 0x4, i);
// | | └──────────┐
// | └─────────┐ |
// * * *
// l4 = &c.cpuid.leaf_0xd_n[i];
}
So the root-cause of all these "static" vs. "dynamic" distinctions was to
catch call sites, at compile-time, when using the wrong CPUID storage
output type relative to the requested leaf/subleaf.
I'll get rid of this static/dynamic terminology and think of something
better.
(and an ACK for all the other snipped remarks.)
Thanks!
--
Ahmed S. Darwish
Linutronix GmbH
next prev parent reply other threads:[~2026-01-26 13:04 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-05 12:14 [PATCH v5 00/35] x86: Introduce a centralized CPUID data model Ahmed S. Darwish
2025-09-05 12:14 ` [PATCH v5 01/35] ASoC: Intel: avs: Include CPUID header at file scope Ahmed S. Darwish
2025-10-16 10:57 ` Borislav Petkov
2025-10-16 19:21 ` Ahmed S. Darwish
2026-03-20 12:39 ` Borislav Petkov
2025-09-05 12:14 ` [PATCH v5 02/35] treewide: Explicitly include the x86 CPUID headers Ahmed S. Darwish
2025-09-05 12:14 ` [PATCH v5 03/35] x86/cpu: <asm/processor.h>: Do not include the CPUID API header Ahmed S. Darwish
2025-09-05 12:14 ` [PATCH v5 04/35] x86/cpuid: Rename cpuid_leaf()/cpuid_subleaf() APIs Ahmed S. Darwish
2025-10-28 17:50 ` Borislav Petkov
2025-09-05 12:14 ` [PATCH v5 05/35] x86/cpu/cacheinfo: Simplify cacheinfo_amd_init_llc_id() using _cpuid4_info Ahmed S. Darwish
2025-09-05 12:14 ` [PATCH v5 06/35] x86/cpuid: Introduce <asm/cpuid/leaf_types.h> Ahmed S. Darwish
2025-09-05 12:14 ` [PATCH v5 07/35] x86: Introduce a centralized CPUID data model Ahmed S. Darwish
2026-01-16 20:31 ` Borislav Petkov
2026-01-26 13:04 ` Ahmed S. Darwish [this message]
2026-01-29 16:07 ` Borislav Petkov
2026-01-29 17:16 ` Ahmed S. Darwish
2025-09-05 12:14 ` [PATCH v5 08/35] x86/cpuid: Introduce a centralized CPUID parser Ahmed S. Darwish
2025-09-18 13:15 ` Ahmed S. Darwish
2026-01-21 21:45 ` Borislav Petkov
2026-01-26 13:14 ` Ahmed S. Darwish
2025-09-05 12:14 ` [PATCH v5 09/35] x86/cpu: Use parsed CPUID(0x0) Ahmed S. Darwish
2026-03-04 14:58 ` Borislav Petkov
2025-09-05 12:14 ` [PATCH v5 10/35] x86/lib: Add CPUID(0x1) CPU family and model calculation Ahmed S. Darwish
2026-03-04 19:43 ` Borislav Petkov
2026-03-05 8:24 ` Ahmed S. Darwish
2025-09-05 12:14 ` [PATCH v5 11/35] x86/cpu: Use parsed CPUID(0x1) Ahmed S. Darwish
2025-09-05 12:14 ` [PATCH v5 12/35] x86/cpuid: Parse CPUID(0x80000000) Ahmed S. Darwish
2025-09-05 12:14 ` [PATCH v5 13/35] x86/cpu: Use parsed CPUID(0x80000000) Ahmed S. Darwish
2025-09-05 12:14 ` [PATCH v5 14/35] x86/cpuid: Parse CPUID(0x80000002) to CPUID(0x80000004) Ahmed S. Darwish
2025-09-05 12:14 ` [PATCH v5 15/35] x86/cpu: Use parsed CPUID(0x80000002)..CPUID(0x80000004) Ahmed S. Darwish
2025-09-05 12:14 ` [PATCH v5 16/35] x86/cpuid: Introduce a parser leaf x86 vendor table Ahmed S. Darwish
2025-09-05 12:14 ` [PATCH v5 17/35] x86/cpuid: Introduce a parser debugfs interface Ahmed S. Darwish
2025-09-05 12:14 ` [PATCH v5 18/35] x86/cpuid: Parse CPUID(0x2) Ahmed S. Darwish
2025-09-05 12:14 ` [PATCH v5 19/35] x86/cpuid: Warn once on invalid CPUID(0x2) iteration count Ahmed S. Darwish
2025-09-05 12:15 ` [PATCH v5 20/35] x86/cpuid: Introduce parsed CPUID(0x2) API Ahmed S. Darwish
2025-09-05 12:15 ` [PATCH v5 21/35] x86/cpu: Use parsed CPUID(0x2) Ahmed S. Darwish
2025-09-05 12:15 ` [PATCH v5 22/35] x86/cacheinfo: " Ahmed S. Darwish
2025-09-05 12:15 ` [PATCH v5 23/35] x86/cpuid: Remove direct CPUID(0x2) query API Ahmed S. Darwish
2025-09-05 12:15 ` [PATCH v5 24/35] x86/cpuid: Parse 'deterministic cache parameters' CPUID leaves Ahmed S. Darwish
2025-09-05 12:15 ` [PATCH v5 25/35] x86/cacheinfo: Pass a 'struct cpuinfo_x86' refrence to CPUID(0x4) code Ahmed S. Darwish
2025-09-05 12:15 ` [PATCH v5 26/35] x86/cacheinfo: Use parsed CPUID(0x4) Ahmed S. Darwish
2025-09-05 12:15 ` [PATCH v5 27/35] x86/cacheinfo: Use parsed CPUID(0x8000001d) Ahmed S. Darwish
2025-09-05 12:15 ` [PATCH v5 28/35] x86/cpuid: Parse CPUID(0x80000005) and CPUID(0x80000006) Ahmed S. Darwish
2025-09-05 12:15 ` [PATCH v5 29/35] x86/cacheinfo: Use auto-generated data types Ahmed S. Darwish
2025-09-05 12:15 ` [PATCH v5 30/35] x86/cacheinfo: Use parsed CPUID(0x80000005) and CPUID(0x80000006) Ahmed S. Darwish
2025-09-05 12:15 ` [PATCH v5 31/35] x86/cacheinfo: Use parsed CPUID(0x80000006) Ahmed S. Darwish
2025-09-05 12:15 ` [PATCH v5 32/35] x86/cpu: Rescan CPUID table after PSN disable Ahmed S. Darwish
2025-09-05 12:15 ` [PATCH v5 33/35] x86/cpu: Rescan CPUID table after unlocking full CPUID range Ahmed S. Darwish
2025-09-05 12:15 ` [PATCH v5 34/35] x86/cpuid: Parse CPUID(0x16) Ahmed S. Darwish
2025-09-05 12:15 ` [PATCH v5 35/35] x86/tsc: Use parsed CPUID(0x16) Ahmed S. Darwish
2025-09-05 12:52 ` [PATCH v5 00/35] x86: Introduce a centralized CPUID data model Ahmed S. Darwish
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