[PATCH v3 0/8] Hexagon (target/hexagon) Check opcodes versions

[PATCH v3 0/8] Hexagon (target/hexagon) Check opcodes versions

[Taylor Simpson]

Currently, all versions of Hexagon CPU are treated the same, and all
opcodes are able to run on any version.  This series changes the behavior
such that only the opcodes available on the currently executing Hexagon
CPU version can execute.

Changes include:
Mark which Hexagon CPU version is currently executing
Check that each opcode is supported in the Hexagon CPU version
If not, generate INVALID_PACKET opcode, which is converted to SIGILL
Properly handle disassembly (-d in_asm)
Test case added

Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>

Changes in v2:
- Rebase with Brian Cain's "Handle some invalid encodings" series
- Add older opcodes to tag_rev_info.c.inc
- Change tag_rev_info to use HexagonVersion
      Suggested by Richard Henderson <richard.henderson@linaro.org>
- Disassembly includes valid opcodes inside packet with invalid opcodes
- Remove unused function - snpring_a_pkt_debug

Changes in v3:
- Use a struct to hold Hexagon definition rather than a simple enum
      Suggested by Anton Johansson <anjo@rev.ng>

Brian Cain (1):
  tests/tcg/hexagon: Add test for revision-gated instruction decoding

Matheus Tavares Bernardino (1):
  Hexagon (target/hexagon) Introduce tag_rev_info.c.inc

Taylor Simpson (6):
  Hexagon (target/hexagon) Properly handle Hexagon CPU version
  Hexagon (linux-user/hexagon) Identify Hexagon version in ELF file
  Hexagon (target/hexagon) Add Hexagon definition field to DisasContext
  Hexagon (target/hexagon) Check each opcode against current CPU
    definition
  Hexagon (target/hexagon) Disassembly of invalid packets
  Hexagon (target/hexagon) Remove snprint_a_pkt_debug

 target/hexagon/cpu-qom.h             |  27 ++
 target/hexagon/cpu.h                 |   2 +
 target/hexagon/cpu_bits.h            |   4 +-
 target/hexagon/decode.h              |   2 +
 target/hexagon/printinsn.h           |   4 +-
 target/hexagon/translate.h           |   1 +
 disas/hexagon.c                      |   3 +-
 linux-user/hexagon/elfload.c         |  43 +-
 target/hexagon/cpu.c                 |  48 ++-
 target/hexagon/decode.c              |  52 ++-
 target/hexagon/printinsn.c           |  40 +-
 target/hexagon/translate.c           |   1 +
 tests/tcg/hexagon/check_rev_gating.c | 141 ++++++
 target/hexagon/tag_rev_info.c.inc    | 613 +++++++++++++++++++++++++++
 tests/tcg/hexagon/Makefile.target    |   6 +
 15 files changed, 911 insertions(+), 76 deletions(-)
 create mode 100644 tests/tcg/hexagon/check_rev_gating.c
 create mode 100644 target/hexagon/tag_rev_info.c.inc

-- 
2.43.0

[PATCH v3 1/8] Hexagon (target/hexagon) Properly handle Hexagon CPU version

[Taylor Simpson]

Add the following CPU versions that were previously missing
    v5
    v55
    v60
    v61
    v62
    v65

Create a CPUHexagonDef struct to represent the definition of a core
    Currently contains an enum with the known Hexagon CPU versions
Add a field to HexagonCPUClass to note the Hexagon definition

Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
---
 target/hexagon/cpu-qom.h | 27 +++++++++++++++++++++++
 target/hexagon/cpu.h     |  2 ++
 target/hexagon/cpu.c     | 46 ++++++++++++++++++++++++----------------
 3 files changed, 57 insertions(+), 18 deletions(-)

diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h
index 0b149bd5fe..6e1bb04070 100644
--- a/target/hexagon/cpu-qom.h
+++ b/target/hexagon/cpu-qom.h
@@ -11,11 +11,38 @@
 
 #include "hw/core/cpu.h"
 
+typedef enum {
+    HEX_VER_NONE = 0x00,
+    HEX_VER_V5 = 0x04,
+    HEX_VER_V55 = 0x05,
+    HEX_VER_V60 = 0x60,
+    HEX_VER_V61 = 0x61,
+    HEX_VER_V62 = 0x62,
+    HEX_VER_V65 = 0x65,
+    HEX_VER_V66 = 0x66,
+    HEX_VER_V67 = 0x67,
+    HEX_VER_V68 = 0x68,
+    HEX_VER_V69 = 0x69,
+    HEX_VER_V71 = 0x71,
+    HEX_VER_V73 = 0x73,
+    HEX_VER_ANY = 0xff,
+} HexagonVersion;
+
+typedef struct {
+    HexagonVersion hex_version;
+} HexagonCPUDef;
+
 #define TYPE_HEXAGON_CPU "hexagon-cpu"
 
 #define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
 #define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)
 
+#define TYPE_HEXAGON_CPU_V5 HEXAGON_CPU_TYPE_NAME("v5")
+#define TYPE_HEXAGON_CPU_V55 HEXAGON_CPU_TYPE_NAME("v55")
+#define TYPE_HEXAGON_CPU_V60 HEXAGON_CPU_TYPE_NAME("v60")
+#define TYPE_HEXAGON_CPU_V61 HEXAGON_CPU_TYPE_NAME("v61")
+#define TYPE_HEXAGON_CPU_V62 HEXAGON_CPU_TYPE_NAME("v62")
+#define TYPE_HEXAGON_CPU_V65 HEXAGON_CPU_TYPE_NAME("v65")
 #define TYPE_HEXAGON_CPU_V66 HEXAGON_CPU_TYPE_NAME("v66")
 #define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
 #define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 85afd59277..f99647dfb6 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -117,6 +117,8 @@ typedef struct HexagonCPUClass {
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
+
+    const HexagonCPUDef *hex_def;
 } HexagonCPUClass;
 
 struct ArchCPU {
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 58a22ee41f..949d509a15 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -27,13 +27,6 @@
 #include "exec/gdbstub.h"
 #include "accel/tcg/cpu-ops.h"
 
-static void hexagon_v66_cpu_init(Object *obj) { }
-static void hexagon_v67_cpu_init(Object *obj) { }
-static void hexagon_v68_cpu_init(Object *obj) { }
-static void hexagon_v69_cpu_init(Object *obj) { }
-static void hexagon_v71_cpu_init(Object *obj) { }
-static void hexagon_v73_cpu_init(Object *obj) { }
-
 static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)
 {
     ObjectClass *oc;
@@ -377,11 +370,21 @@ static void hexagon_cpu_class_init(ObjectClass *c, const void *data)
     cc->tcg_ops = &hexagon_tcg_ops;
 }
 
-#define DEFINE_CPU(type_name, initfn)      \
-    {                                      \
-        .name = type_name,                 \
-        .parent = TYPE_HEXAGON_CPU,        \
-        .instance_init = initfn            \
+static void hexagon_cpu_class_base_init(ObjectClass *c, const void *data)
+{
+    HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c);
+    /* Make sure all CPU models define a HexagonCPUDef */
+    g_assert(!object_class_is_abstract(c) && data != NULL);
+    mcc->hex_def = data;
+}
+
+#define DEFINE_CPU(type_name, version)         \
+    {                                          \
+        .name = type_name,                     \
+        .parent = TYPE_HEXAGON_CPU,            \
+        .class_data = &(const HexagonCPUDef) { \
+            .hex_version = version,            \
+        }                                      \
     }
 
 static const TypeInfo hexagon_cpu_type_infos[] = {
@@ -394,13 +397,20 @@ static const TypeInfo hexagon_cpu_type_infos[] = {
         .abstract = true,
         .class_size = sizeof(HexagonCPUClass),
         .class_init = hexagon_cpu_class_init,
+        .class_base_init = hexagon_cpu_class_base_init,
     },
-    DEFINE_CPU(TYPE_HEXAGON_CPU_V66,              hexagon_v66_cpu_init),
-    DEFINE_CPU(TYPE_HEXAGON_CPU_V67,              hexagon_v67_cpu_init),
-    DEFINE_CPU(TYPE_HEXAGON_CPU_V68,              hexagon_v68_cpu_init),
-    DEFINE_CPU(TYPE_HEXAGON_CPU_V69,              hexagon_v69_cpu_init),
-    DEFINE_CPU(TYPE_HEXAGON_CPU_V71,              hexagon_v71_cpu_init),
-    DEFINE_CPU(TYPE_HEXAGON_CPU_V73,              hexagon_v73_cpu_init),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V5,               HEX_VER_V5),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V55,              HEX_VER_V55),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V60,              HEX_VER_V60),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V61,              HEX_VER_V61),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V62,              HEX_VER_V62),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V65,              HEX_VER_V65),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V66,              HEX_VER_V66),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V67,              HEX_VER_V67),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V68,              HEX_VER_V68),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V69,              HEX_VER_V69),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V71,              HEX_VER_V71),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V73,              HEX_VER_V73),
 };
 
 DEFINE_TYPES(hexagon_cpu_type_infos)
-- 
2.43.0

Re: [PATCH v3 1/8] Hexagon (target/hexagon) Properly handle Hexagon CPU version

[Anton Johansson via qemu development]

On 17/02/26, Taylor Simpson wrote:
> Add the following CPU versions that were previously missing
>     v5
>     v55
>     v60
>     v61
>     v62
>     v65
> 
> Create a CPUHexagonDef struct to represent the definition of a core

           HexagonCPUDef :)



>     Currently contains an enum with the known Hexagon CPU versions
> Add a field to HexagonCPUClass to note the Hexagon definition
> 
> Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
> Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> ---
>  target/hexagon/cpu-qom.h | 27 +++++++++++++++++++++++
>  target/hexagon/cpu.h     |  2 ++
>  target/hexagon/cpu.c     | 46 ++++++++++++++++++++++++----------------
>  3 files changed, 57 insertions(+), 18 deletions(-)

Otherwise looks good,

Reviewed-by: Anton Johansson <anjo@rev.ng>

[PATCH v3 2/8] Hexagon (linux-user/hexagon) Identify Hexagon version in ELF file

[Taylor Simpson]

Return proper Hexagon CPU version from get_elf_cpu_model

Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
---
 linux-user/hexagon/elfload.c | 43 ++++++++++++++++++++++--------------
 1 file changed, 26 insertions(+), 17 deletions(-)

diff --git a/linux-user/hexagon/elfload.c b/linux-user/hexagon/elfload.c
index d8b545032a..39b0201814 100644
--- a/linux-user/hexagon/elfload.c
+++ b/linux-user/hexagon/elfload.c
@@ -10,23 +10,32 @@ const char *get_elf_cpu_model(uint32_t eflags)
     static char buf[32];
     int err;
 
-    /* For now, treat anything newer than v5 as a v73 */
-    /* FIXME - Disable instructions that are newer than the specified arch */
-    if (eflags == 0x04 ||    /* v5  */
-        eflags == 0x05 ||    /* v55 */
-        eflags == 0x60 ||    /* v60 */
-        eflags == 0x61 ||    /* v61 */
-        eflags == 0x62 ||    /* v62 */
-        eflags == 0x65 ||    /* v65 */
-        eflags == 0x66 ||    /* v66 */
-        eflags == 0x67 ||    /* v67 */
-        eflags == 0x8067 ||  /* v67t */
-        eflags == 0x68 ||    /* v68 */
-        eflags == 0x69 ||    /* v69 */
-        eflags == 0x71 ||    /* v71 */
-        eflags == 0x8071 ||  /* v71t */
-        eflags == 0x73       /* v73 */
-       ) {
+    switch (eflags) {
+    case 0x04:
+        return "v5";
+    case 0x05:
+        return "v55";
+    case 0x60:
+        return "v60";
+    case 0x61:
+        return "v61";
+    case 0x62:
+        return "v62";
+    case 0x65:
+        return "v65";
+    case 0x66:
+        return "v66";
+    case 0x67:
+    case 0x8067:        /* v67t */
+        return "v67";
+    case 0x68:
+        return "v68";
+    case 0x69:
+        return "v69";
+    case 0x71:
+    case 0x8071:        /* v71t */
+        return "v71";
+    case 0x73:
         return "v73";
     }
 
-- 
2.43.0

Re: [PATCH v3 2/8] Hexagon (linux-user/hexagon) Identify Hexagon version in ELF file

[Anton Johansson via qemu development]

On 17/02/26, Taylor Simpson wrote:
> Return proper Hexagon CPU version from get_elf_cpu_model
> 
> Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
> Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> ---
>  linux-user/hexagon/elfload.c | 43 ++++++++++++++++++++++--------------
>  1 file changed, 26 insertions(+), 17 deletions(-)

Agh okay let's go with constants then!:)

Reviewed-by: Anton Johansson <anjo@rev.ng>

[PATCH v3 3/8] Hexagon (target/hexagon) Add Hexagon definition field to DisasContext

[Taylor Simpson]

Initialize the field in hexagon_tr_init_disas_context

Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
---
 target/hexagon/translate.h | 1 +
 target/hexagon/translate.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index b37cb49238..9cdcbd6416 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -30,6 +30,7 @@ typedef struct DisasContext {
     DisasContextBase base;
     Packet *pkt;
     Insn *insn;
+    const HexagonCPUDef *hex_def;
     uint32_t next_PC;
     uint32_t mem_idx;
     uint32_t num_packets;
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 2fdc956bf9..a4c2ef534e 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -988,6 +988,7 @@ static void hexagon_tr_init_disas_context(DisasContextBase *dcbase,
     ctx->branch_cond = TCG_COND_NEVER;
     ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP);
     ctx->short_circuit = hex_cpu->short_circuit;
+    ctx->hex_def = HEXAGON_CPU_GET_CLASS(hex_cpu)->hex_def;
 }
 
 static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.43.0

Re: [PATCH v3 3/8] Hexagon (target/hexagon) Add Hexagon definition field to DisasContext

[Anton Johansson via qemu development]

On 17/02/26, Taylor Simpson wrote:
> Initialize the field in hexagon_tr_init_disas_context
> 
> Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
> Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> ---
>  target/hexagon/translate.h | 1 +
>  target/hexagon/translate.c | 1 +
>  2 files changed, 2 insertions(+)

Reviewed-by: Anton Johansson <anjo@rev.ng>

[PATCH v3 4/8] Hexagon (target/hexagon) Introduce tag_rev_info.c.inc

[Taylor Simpson]

From: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>

Table that records which CPU revision introduced or removed
for each opcode

Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
Co-authored-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
---
 target/hexagon/tag_rev_info.c.inc | 613 ++++++++++++++++++++++++++++++
 1 file changed, 613 insertions(+)
 create mode 100644 target/hexagon/tag_rev_info.c.inc

diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_info.c.inc
new file mode 100644
index 0000000000..11c90f86ad
--- /dev/null
+++ b/target/hexagon/tag_rev_info.c.inc
@@ -0,0 +1,613 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HEXAGON_TAG_ARCH_TABLE_H
+#define HEXAGON_TAG_ARCH_TABLE_H
+
+struct tag_rev_info { HexagonVersion introduced, removed; };
+
+static const struct tag_rev_info tag_rev_info[XX_LAST_OPCODE] = {
+    [A5_ACS] = { .introduced = HEX_VER_V55, .removed = HEX_VER_NONE },
+
+    [J2_jumpfpt] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [J2_jumprfpt] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [J2_jumprtpt] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [J2_jumptpt] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_p] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_p_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_p_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_p_nac] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_p_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_p_xacc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_r] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_r_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_r_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_r_nac] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_r_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_r_xacc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_extractw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_lvsplatw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_pred_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_pred_and_n] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_pred_not] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_pred_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_pred_or_n] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_pred_scalar2] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_pred_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32Ub_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32Ub_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32Ub_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_npred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_npred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_npred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_pred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_pred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_pred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_npred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_npred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_npred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_pred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_pred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_pred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_npred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_npred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_npred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nqpred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nqpred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nqpred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_npred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_npred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_npred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_pred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_pred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_pred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_npred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_npred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_npred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_nqpred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_nqpred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_nqpred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_pred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_pred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_pred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_qpred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_qpred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_qpred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_pred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_pred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_pred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_qpred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_qpred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_qpred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vabsdiffh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vabsdiffub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vabsdiffuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vabsdiffw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vabsh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vabsh_sat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vabsw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vabsw_sat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddb_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddbnq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddbq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddh_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddhnq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddhq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddhsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddhsat_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddhw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddubh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddubsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddubsat_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vadduhsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vadduhsat_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vadduhw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddw_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddwnq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddwq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddwsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddwsat_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_valignb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_valignbi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vand] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vandqrt] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vandqrt_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vandvrt] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vandvrt_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaslh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaslhv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaslw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaslw_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaslwv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrhbrndsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrhubrndsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrhubsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrhv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrw_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrwh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrwhrndsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrwhsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrwuhsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrwv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vassign] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vavgh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vavghrnd] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vavgub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vavgubrnd] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vavguh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vavguhrnd] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vavgw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vavgwrnd] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vccombine] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vcl0h] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vcl0w] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vcmov] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vcombine] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdeal] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdealb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdealb4w] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdealh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdealvdd] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdelta] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpybus] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpybus_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpybus_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpybus_dv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhb_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhb_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhb_dv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhisat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhisat_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhsat_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhsuisat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhsuisat_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhsusat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhsusat_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhvsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhvsat_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdsaduh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdsaduh_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqb_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqb_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqb_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqh_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqh_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqh_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqw_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqw_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqw_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtb_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtb_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtb_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgth] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgth_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgth_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgth_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtub_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtub_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtub_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtuh_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtuh_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtuh_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtuw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtuw_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtuw_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtuw_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtw_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtw_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtw_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vhist] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vhistq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vinsertwr] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlalignb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlalignbi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlsrh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlsrhv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlsrw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlsrwv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlutvvb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlutvvb_oracc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlutvwh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlutvwh_oracc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmaxh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmaxub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmaxuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmaxw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vminh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vminub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vminuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vminw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpabus] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpabus_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpabusv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpabuuv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpahb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpahb_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpybus] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpybus_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpybusv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpybusv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpybv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpybv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyewuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyhsat_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyhsrs] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyhss] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyhus] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyhus_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyhv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyhv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyhvsrs] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyieoh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyiewh_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyiewuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyiewuh_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyih] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyih_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyihb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyihb_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyiowh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyiwb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyiwb_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyiwh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyiwh_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyowh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyowh_rnd] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyowh_rnd_sacc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyowh_sacc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyub_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyubv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyubv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyuh_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyuhv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyuhv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmux] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vnavgh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vnavgub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vnavgw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vnccombine] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vncmov] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vnormamth] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vnormamtw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vnot] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpackeb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpackeh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpackhb_sat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpackhub_sat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpackob] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpackoh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpackwh_sat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpackwuh_sat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpopcounth] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrdelta] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpybus] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpybus_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpybusi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpybusi_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpybusv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpybusv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpybv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpybv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpyub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpyub_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpyubi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpyubi_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpyubv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpyubv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vror] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vroundhb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vroundhub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vroundwh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vroundwuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrsadubi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrsadubi_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsathub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsatwh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshufeh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshuff] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshuffb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshuffeb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshuffh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshuffob] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshuffvdd] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshufoeb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshufoeh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshufoh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubb_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubbnq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubbq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubh_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubhnq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubhq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubhsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubhsat_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubhw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsububh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsububsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsububsat_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubuhsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubuhsat_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubuhw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubw_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubwnq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubwq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubwsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubwsat_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vswap] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vtmpyb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vtmpyb_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vtmpybus] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vtmpybus_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vtmpyhb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vtmpyhb_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vunpackb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vunpackh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vunpackob] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vunpackoh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vunpackub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vunpackuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vxor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vzb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vzh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+
+    [A6_vminub_RdP] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [M6_vabsdiffb] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [M6_vabsdiffub] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [S6_vsplatrbp] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [S6_vtrunehb_ppp] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [S6_vtrunohb_ppp] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_lvsplatb] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_lvsplath] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_pred_scalar2v2] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_shuffeqh] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_shuffeqw] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_npred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_npred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_npred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_pred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_pred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_pred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_npred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_npred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_npred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_npred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_npred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_npred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_pred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_pred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_pred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_npred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_npred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_npred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_pred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_pred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_pred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_npred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_npred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_npred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_pred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_pred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_pred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_pred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_pred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_pred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_npred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_npred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_npred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_pred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_pred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_pred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vaddbsat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vaddbsat_dv] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vaddcarry] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vaddclbh] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vaddclbw] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vaddhw_acc] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vaddubh_acc] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vaddububb_sat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vadduhw_acc] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vadduwsat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vadduwsat_dv] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vandnqrt] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vandnqrt_acc] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vandvnqv] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vandvqv] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vasrhbsat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vasruwuhrndsat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vasrwuhrndsat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vlsrb] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vlutvvb_nm] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vlutvvb_oracci] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vlutvvbi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vlutvwh_nm] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vlutvwh_oracci] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vlutvwhi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vmaxb] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vminb] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vmpauhb] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vmpauhb_acc] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vmpyewuh_64] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vmpyiwub] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vmpyiwub_acc] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vmpyowh_64_acc] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vrounduhub] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vrounduwuh] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vsatuwuh] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vsubbsat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vsubbsat_dv] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vsubcarry] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vsubububb_sat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vsubuwsat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vsubuwsat_dv] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vwhist128] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vwhist128m] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vwhist128q] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vwhist128qm] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vwhist256] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vwhist256_sat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vwhist256q] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vwhist256q_sat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+
+    [A6_vcmpbeq_notany] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vS32b_srls_ai] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vS32b_srls_pi] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vS32b_srls_ppu] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vabsb] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vabsb_sat] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vaslh_acc] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vasrh_acc] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vasruhubrndsat] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vasruhubsat] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vasruwuhsat] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vavgb] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vavgbrnd] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vavguw] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vavguwrnd] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vgathermh] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vgathermhq] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vgathermhw] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vgathermhwq] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vgathermw] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vgathermwq] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vlut4] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vmpabuu] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vmpabuu_acc] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vmpahhsat] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vmpauhuhsat] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vmpsuhuhsat] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vmpyh_acc] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vmpyuhe] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vmpyuhe_acc] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vnavgb] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vprefixqb] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vprefixqh] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vprefixqw] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermh] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermh_add] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermhq] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermhw] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermhw_add] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermhwq] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermw] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermw_add] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermwq] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+
+    [F2_dfadd] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [F2_dfsub] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [M2_mnaci] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [S2_mask] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [V6_vaddcarryo] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [V6_vaddcarrysat] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [V6_vasr_into] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [V6_vrotr] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [V6_vsatdw] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [V6_vsubcarryo] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+
+    [A7_clip] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [A7_croundd_ri] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [A7_croundd_rr] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [A7_vclip] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [F2_dfmax] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [F2_dfmin] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [F2_dfmpyfix] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [F2_dfmpyhh] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [F2_dfmpylh] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [F2_dfmpyll] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [J2_callrh] = { .introduced = 0x73, .removed = HEX_VER_NONE },
+    [J2_jumprh] = { .introduced = 0x73, .removed = HEX_VER_NONE },
+    [L2_loadw_aq] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [L4_loadd_aq] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [M7_dcmpyiw] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_dcmpyiw_acc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_dcmpyiwc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_dcmpyiwc_acc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_dcmpyrw] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_dcmpyrw_acc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_dcmpyrwc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_dcmpyrwc_acc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_wcmpyiw] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_wcmpyiw_rnd] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_wcmpyiwc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_wcmpyiwc_rnd] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_wcmpyrw] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_wcmpyrw_rnd] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_wcmpyrwc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_wcmpyrwc_rnd] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [R6_release_at_vi] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [R6_release_st_vi] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [S2_storew_rl_at_vi] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [S2_storew_rl_st_vi] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [S4_stored_rl_at_vi] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [S4_stored_rl_st_vi] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [V6_v6mpyhubs10] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [V6_v6mpyhubs10_vxx] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [V6_v6mpyvubs10] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [V6_v6mpyvubs10_vxx] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [V6_vasrvuhubrndsat] = { .introduced = HEX_VER_V69, .removed = HEX_VER_NONE },
+    [V6_vasrvuhubsat] = { .introduced = HEX_VER_V69, .removed = HEX_VER_NONE },
+    [V6_vasrvwuhrndsat] = { .introduced = HEX_VER_V69, .removed = HEX_VER_NONE },
+    [V6_vasrvwuhsat] = { .introduced = HEX_VER_V69, .removed = HEX_VER_NONE },
+    [V6_vassign_tmp] = { .introduced = HEX_VER_V69, .removed = HEX_VER_NONE },
+    [V6_vcombine_tmp] = { .introduced = HEX_VER_V69, .removed = HEX_VER_NONE },
+    [V6_vmpyuhvs] = { .introduced = HEX_VER_V69, .removed = HEX_VER_NONE },
+};
+
+#endif /* HEXAGON_TAG_ARCH_TABLE_H */
-- 
2.43.0

Re: [PATCH v3 4/8] Hexagon (target/hexagon) Introduce tag_rev_info.c.inc

[Anton Johansson via qemu development]

On 17/02/26, Taylor Simpson wrote:
> From: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
> 
> Table that records which CPU revision introduced or removed
> for each opcode
> 
> Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
> Co-authored-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> ---
>  target/hexagon/tag_rev_info.c.inc | 613 ++++++++++++++++++++++++++++++
>  1 file changed, 613 insertions(+)
>  create mode 100644 target/hexagon/tag_rev_info.c.inc
> 
> diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_info.c.inc
> new file mode 100644
> index 0000000000..11c90f86ad
> --- /dev/null
> +++ b/target/hexagon/tag_rev_info.c.inc
> @@ -0,0 +1,613 @@
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#ifndef HEXAGON_TAG_ARCH_TABLE_H
> +#define HEXAGON_TAG_ARCH_TABLE_H
> +
> +struct tag_rev_info { HexagonVersion introduced, removed; };
> +
> +static const struct tag_rev_info tag_rev_info[XX_LAST_OPCODE] = {
> +    [A5_ACS] = { .introduced = HEX_VER_V55, .removed = HEX_VER_NONE },

...

> +
> +    [A7_clip] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
> +    [A7_croundd_ri] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
> +    [A7_croundd_rr] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
> +    [A7_vclip] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
> +    [F2_dfmax] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
> +    [F2_dfmin] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
> +    [F2_dfmpyfix] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
> +    [F2_dfmpyhh] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
> +    [F2_dfmpylh] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
> +    [F2_dfmpyll] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
> +    [J2_callrh] = { .introduced = 0x73, .removed = HEX_VER_NONE },
> +    [J2_jumprh] = { .introduced = 0x73, .removed = HEX_VER_NONE },

I assume you missed HEX_VER_V73 here

With that fixed 

Reviewed-by: Anton Johansson <anjo@rev.ng>

Re: [PATCH v3 4/8] Hexagon (target/hexagon) Introduce tag_rev_info.c.inc

[Taylor Simpson]

[-- Attachment #1: Type: text/plain, Size: 2560 bytes --]

On Tue, Feb 24, 2026 at 6:20 AM Anton Johansson <anjo@rev.ng> wrote:

> On 17/02/26, Taylor Simpson wrote:
> > From: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
> >
> > Table that records which CPU revision introduced or removed
> > for each opcode
> >
> > Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
> > Co-authored-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> > Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> > Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> > ---
> >  target/hexagon/tag_rev_info.c.inc | 613 ++++++++++++++++++++++++++++++
> >  1 file changed, 613 insertions(+)
> >  create mode 100644 target/hexagon/tag_rev_info.c.inc
> >
> > diff --git a/target/hexagon/tag_rev_info.c.inc
> b/target/hexagon/tag_rev_info.c.inc
> > new file mode 100644
> > index 0000000000..11c90f86ad
> > --- /dev/null
> > +++ b/target/hexagon/tag_rev_info.c.inc
> > @@ -0,0 +1,613 @@
> > +/*
> > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> > + * SPDX-License-Identifier: GPL-2.0-or-later
> > + */
> > +
> > +#ifndef HEXAGON_TAG_ARCH_TABLE_H
> > +#define HEXAGON_TAG_ARCH_TABLE_H
> > +
> > +struct tag_rev_info { HexagonVersion introduced, removed; };
> > +
> > +static const struct tag_rev_info tag_rev_info[XX_LAST_OPCODE] = {
> > +    [A5_ACS] = { .introduced = HEX_VER_V55, .removed = HEX_VER_NONE },
>
> ...
>
> > +
> > +    [A7_clip] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
> > +    [A7_croundd_ri] = { .introduced = HEX_VER_V67, .removed =
> HEX_VER_NONE },
> > +    [A7_croundd_rr] = { .introduced = HEX_VER_V67, .removed =
> HEX_VER_NONE },
> > +    [A7_vclip] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
> > +    [F2_dfmax] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
> > +    [F2_dfmin] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
> > +    [F2_dfmpyfix] = { .introduced = HEX_VER_V67, .removed =
> HEX_VER_NONE },
> > +    [F2_dfmpyhh] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE
> },
> > +    [F2_dfmpylh] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE
> },
> > +    [F2_dfmpyll] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE
> },
> > +    [J2_callrh] = { .introduced = 0x73, .removed = HEX_VER_NONE },
> > +    [J2_jumprh] = { .introduced = 0x73, .removed = HEX_VER_NONE },
>
> I assume you missed HEX_VER_V73 here
>

Good catch!  Fixed.


>
> With that fixed
>
> Reviewed-by: Anton Johansson <anjo@rev.ng>
>

[-- Attachment #2: Type: text/html, Size: 3712 bytes --]

[PATCH v3 5/8] Hexagon (target/hexagon) Check each opcode against current CPU definition

[Taylor Simpson]

During decoding, check that the opcode is supported in the current
Hexagon CPU definition

Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
---
 target/hexagon/decode.h |  2 ++
 target/hexagon/decode.c | 27 +++++++++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/target/hexagon/decode.h b/target/hexagon/decode.h
index 3f3012b978..d4b049961e 100644
--- a/target/hexagon/decode.h
+++ b/target/hexagon/decode.h
@@ -30,4 +30,6 @@ void decode_send_insn_to(Packet *packet, int start, int newloc);
 int decode_packet(DisasContext *ctx, int max_words, const uint32_t *words,
                   Packet *pkt, bool disas_only);
 
+bool opcode_supported(uint16_t opcode, const HexagonCPUDef *hex_def);
+
 #endif
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index dbc9c630e8..b8a1cd5b12 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -647,6 +647,22 @@ decode_set_slot_number(Packet *pkt)
     return has_valid_slot_assignment(pkt);
 }
 
+bool opcode_supported(uint16_t opcode, const HexagonCPUDef *hex_def)
+{
+    HexagonVersion hex_version = hex_def->hex_version;
+#include "tag_rev_info.c.inc"
+
+    struct tag_rev_info info = tag_rev_info[opcode];
+    if (hex_version == HEX_VER_ANY) {
+        return true;
+    }
+    if ((info.introduced != HEX_VER_NONE && hex_version < info.introduced) ||
+        (info.removed != HEX_VER_NONE && hex_version >= info.removed)) {
+        return false;
+    }
+    return true;
+}
+
 /*
  * Check for GPR write conflicts in the packet.
  * A conflict exists when a register is written by more than one instruction
@@ -746,6 +762,17 @@ int decode_packet(DisasContext *ctx, int max_words, const uint32_t *words,
         /* Ran out of words! */
         return 0;
     }
+
+    /*
+     * Check that all the opcodes are supported in this Hexagon definition
+     * If not, return decode error
+     */
+    for (i = 0; i < num_insns; i++) {
+        if (!opcode_supported(pkt->insn[i].opcode, ctx->hex_def)) {
+            return 0;
+        }
+    }
+
     pkt->encod_pkt_size_in_bytes = words_read * 4;
     pkt->pkt_has_hvx = false;
     for (i = 0; i < num_insns; i++) {
-- 
2.43.0

Re: [PATCH v3 5/8] Hexagon (target/hexagon) Check each opcode against current CPU definition

[Anton Johansson via qemu development]

On 17/02/26, Taylor Simpson wrote:
> During decoding, check that the opcode is supported in the current
> Hexagon CPU definition
> 
> Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
> Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> ---
>  target/hexagon/decode.h |  2 ++
>  target/hexagon/decode.c | 27 +++++++++++++++++++++++++++
>  2 files changed, 29 insertions(+)

Reviewed-by: Anton Johansson <anjo@rev.ng>

[PATCH v3 6/8] Hexagon (target/hexagon) Disassembly of invalid packets

[Taylor Simpson]

We pass the Hexagon CPU definition to disassemble_hexagon.  This allows
decode_packet to know if the opcodes are supported.

Note that we print valid instructions in a packet when one or more is
invalid.  Rather than this
0x0002128c:  0x1eae4fec	{	<invalid>
0x00021290:  0x1c434c04		<invalid>
0x00021294:  0x1e03edf0		<invalid> }

We print this
0x0002128c:  0x1eae4fec	{	<invalid>
0x00021290:  0x1c434c04		V4.w = vadd(V12.w,V3.w)
0x00021294:  0x1e03edf0		V16 = V13 }

Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
---
 target/hexagon/cpu_bits.h  |  4 +++-
 target/hexagon/printinsn.h |  3 ++-
 disas/hexagon.c            |  3 ++-
 target/hexagon/cpu.c       |  2 ++
 target/hexagon/decode.c    | 25 +++++++++++++++++++++----
 target/hexagon/printinsn.c |  9 +++++++--
 6 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index 19beca81c0..aaac6b9ea6 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon/cpu_bits.h
@@ -19,6 +19,7 @@
 #define HEXAGON_CPU_BITS_H
 
 #include "qemu/bitops.h"
+#include "cpu-qom.h"
 
 #define PCALIGN 4
 #define PCALIGN_MASK (PCALIGN - 1)
@@ -65,6 +66,7 @@ static inline bool is_packet_end(uint32_t endocing)
     return ((bits == 0x3) || (bits == 0x0));
 }
 
-int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc, GString *buf);
+int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc, GString *buf,
+                        const HexagonCPUDef *hex_def);
 
 #endif
diff --git a/target/hexagon/printinsn.h b/target/hexagon/printinsn.h
index 2ecd1731d0..6f84ef93c3 100644
--- a/target/hexagon/printinsn.h
+++ b/target/hexagon/printinsn.h
@@ -18,10 +18,11 @@
 #ifndef HEXAGON_PRINTINSN_H
 #define HEXAGON_PRINTINSN_H
 
+#include "cpu-qom.h"
 #include "insn.h"
 
 void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
-                         target_ulong pc);
+                         target_ulong pc, const HexagonCPUDef *hex_def);
 void snprint_a_pkt_debug(GString *buf, Packet *pkt);
 
 #endif
diff --git a/disas/hexagon.c b/disas/hexagon.c
index c1a4ffc5f6..36b8321c26 100644
--- a/disas/hexagon.c
+++ b/disas/hexagon.c
@@ -31,6 +31,7 @@
 
 int print_insn_hexagon(bfd_vma memaddr, struct disassemble_info *info)
 {
+    const HexagonCPUDef *hex_def = (const HexagonCPUDef *)info->target_info;
     uint32_t words[PACKET_WORDS_MAX];
     bool found_end = false;
     GString *buf;
@@ -58,7 +59,7 @@ int print_insn_hexagon(bfd_vma memaddr, struct disassemble_info *info)
     }
 
     buf = g_string_sized_new(PACKET_BUFFER_LEN);
-    len = disassemble_hexagon(words, i, memaddr, buf);
+    len = disassemble_hexagon(words, i, memaddr, buf, hex_def);
     (*info->fprintf_func)(info->stream, "%s", buf->str);
     g_string_free(buf, true);
 
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 949d509a15..001ea3c4ef 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -297,8 +297,10 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
 static void hexagon_cpu_disas_set_info(const CPUState *cs,
                                        disassemble_info *info)
 {
+    const HexagonCPU *cpu = HEXAGON_CPU(cs);
     info->print_insn = print_insn_hexagon;
     info->endian = BFD_ENDIAN_LITTLE;
+    info->target_info = HEXAGON_CPU_GET_CLASS(cpu)->hex_def;
 }
 
 static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index b8a1cd5b12..c4cf430e5a 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -828,19 +828,36 @@ int decode_packet(DisasContext *ctx, int max_words, const uint32_t *words,
 
 /* Used for "-d in_asm" logging */
 int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc,
-                        GString *buf)
+                        GString *buf, const HexagonCPUDef  *hex_def)
 {
+    HexagonCPUDef any_def = {
+        .hex_version = HEX_VER_ANY,  /* Allow decode to accept anything */
+    };
     DisasContext ctx;
     Packet pkt;
 
     memset(&ctx, 0, sizeof(DisasContext));
+    ctx.hex_def = &any_def;
     ctx.pkt = &pkt;
 
     if (decode_packet(&ctx, nwords, words, &pkt, true) > 0) {
-        snprint_a_pkt_disas(buf, &pkt, words, pc);
+        snprint_a_pkt_disas(buf, &pkt, words, pc, hex_def);
         return pkt.encod_pkt_size_in_bytes;
     } else {
-        g_string_assign(buf, "<invalid>");
-        return 0;
+        for (int i = 0; i < nwords; i++) {
+            g_string_append_printf(buf, "0x" TARGET_FMT_lx "\t", words[i]);
+            if (i == 0) {
+                g_string_append(buf, "{");
+            }
+            g_string_append(buf, "\t");
+            g_string_append(buf, "<invalid>");
+            if (i < nwords - 1) {
+                pc += 4;
+                g_string_append_printf(buf, "\n0x" TARGET_FMT_lx ":  ",
+                                       (target_ulong)pc);
+            }
+        }
+        g_string_append(buf, " }");
+        return nwords * sizeof(uint32_t);
     }
 }
diff --git a/target/hexagon/printinsn.c b/target/hexagon/printinsn.c
index 4865cdd133..22b305f018 100644
--- a/target/hexagon/printinsn.c
+++ b/target/hexagon/printinsn.c
@@ -21,6 +21,7 @@
 #include "insn.h"
 #include "reg_fields.h"
 #include "internal.h"
+#include "decode.h"
 
 static const char *sreg2str(unsigned int reg)
 {
@@ -51,7 +52,7 @@ static void snprintinsn(GString *buf, Insn *insn)
 }
 
 void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
-                         target_ulong pc)
+                         target_ulong pc, const HexagonCPUDef *hex_def)
 {
     bool has_endloop0 = false;
     bool has_endloop1 = false;
@@ -83,7 +84,11 @@ void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
         }
 
         g_string_append(buf, "\t");
-        snprintinsn(buf, &(pkt->insn[i]));
+        if (opcode_supported(pkt->insn[i].opcode, hex_def)) {
+            snprintinsn(buf, &(pkt->insn[i]));
+        } else {
+            g_string_append(buf, "<invalid>");
+        }
 
         if (i < pkt->num_insns - 1) {
             /*
-- 
2.43.0

Re: [PATCH v3 6/8] Hexagon (target/hexagon) Disassembly of invalid packets

[Anton Johansson via qemu development]

On 17/02/26, Taylor Simpson wrote:
> We pass the Hexagon CPU definition to disassemble_hexagon.  This allows
> decode_packet to know if the opcodes are supported.
> 
> Note that we print valid instructions in a packet when one or more is
> invalid.  Rather than this
> 0x0002128c:  0x1eae4fec	{	<invalid>
> 0x00021290:  0x1c434c04		<invalid>
> 0x00021294:  0x1e03edf0		<invalid> }
> 
> We print this
> 0x0002128c:  0x1eae4fec	{	<invalid>
> 0x00021290:  0x1c434c04		V4.w = vadd(V12.w,V3.w)
> 0x00021294:  0x1e03edf0		V16 = V13 }
> 
> Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
> Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> ---
>  target/hexagon/cpu_bits.h  |  4 +++-
>  target/hexagon/printinsn.h |  3 ++-
>  disas/hexagon.c            |  3 ++-
>  target/hexagon/cpu.c       |  2 ++
>  target/hexagon/decode.c    | 25 +++++++++++++++++++++----
>  target/hexagon/printinsn.c |  9 +++++++--
>  6 files changed, 37 insertions(+), 9 deletions(-)

Reviewed-by: Anton Johansson <anjo@rev.ng>

[PATCH v3 7/8] tests/tcg/hexagon: Add test for revision-gated instruction decoding

[Taylor Simpson]

From: Brian Cain <brian.cain@oss.qualcomm.com>

Add check_rev_gating, a linux-user test that verifies the decoder
rejects instructions from a newer CPU revision than the one selected
by the ELF binary's e_flags.

Co-authored-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 tests/tcg/hexagon/check_rev_gating.c | 141 +++++++++++++++++++++++++++
 tests/tcg/hexagon/Makefile.target    |   6 ++
 2 files changed, 147 insertions(+)
 create mode 100644 tests/tcg/hexagon/check_rev_gating.c

diff --git a/tests/tcg/hexagon/check_rev_gating.c b/tests/tcg/hexagon/check_rev_gating.c
new file mode 100644
index 0000000000..26b66f5455
--- /dev/null
+++ b/tests/tcg/hexagon/check_rev_gating.c
@@ -0,0 +1,141 @@
+/*
+ * Test that instructions from a newer revision than the running CPU
+ * are rejected with SIGILL.
+ *
+ * Compiled with -mv66 so that e_flags selects CPU v66. The test embeds
+ * a v68 instruction (L2_loadw_aq: "r0 = memw_aq(r0)") via .word
+ * encoding. The revision-gated decoder must reject it, and linux-user
+ * must deliver SIGILL.
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <assert.h>
+#include <signal.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+static void *resume_pc;
+static int signals_handled;
+static int expected_signals;
+
+static void handle_sigill(int sig, siginfo_t *info, void *puc)
+{
+    ucontext_t *uc = (ucontext_t *)puc;
+
+    if (sig != SIGILL) {
+        _exit(EXIT_FAILURE);
+    }
+
+    uc->uc_mcontext.r0 = SIGILL;
+    uc->uc_mcontext.pc = (unsigned long)resume_pc;
+    signals_handled++;
+}
+
+/*
+ * Try to execute an instruction introduced after v66
+ * On a v66 CPU this must raise SIGILL.
+ *
+ * Since we are building for v66, the assembler will reject
+ * the instructions, so introduce them with .word.
+ */
+#define TRY_FUNC(NAME, WORD) \
+static int try_##NAME(void) \
+{ \
+    int sig; \
+    expected_signals++; \
+    asm volatile( \
+        "r0 = #0\n" \
+        "r1 = ##1f\n" \
+        "memw(%1) = r1\n" \
+        WORD \
+        "1:\n" \
+        "%0 = r0\n" \
+        : "=r"(sig) \
+        : "r"(&resume_pc) \
+        : "r0", "r1", "memory"); \
+    return sig; \
+}
+
+TRY_FUNC(v68_loadw_aq,
+         ".word 0x9200c800    /* { r0 = memw_aq(r0) } */\n")
+TRY_FUNC(v68_loadd_aq,
+         ".word 0x9201d800    /* r1:0 = memd_aq(r1) */\n")
+TRY_FUNC(v68_release_at,
+         ".word 0xa0e0c00c    /* release(r0):at */\n")
+TRY_FUNC(v68_release_st,
+         ".word 0xa0e0c02c    /* release(r0):st */\n")
+TRY_FUNC(v68_storew_rl_at,
+         ".word 0xa0a0c108    /* memw_rl(r0):at = r1 */\n")
+TRY_FUNC(v68_stored_rl_at,
+         ".word 0xa0e2c008    /* memd_rl(r2):at = r1:0 */\n")
+TRY_FUNC(v68_storew_rl_st,
+         ".word 0xa0a0c128    /* memw_rl(r0):st = r1 */\n")
+TRY_FUNC(v68_stored_rl_st,
+         ".word 0xa0e2c028    /* memd_rl(r2):st = r1:0 */\n")
+
+TRY_FUNC(v68hvx_v6mpy,
+         ".word 0x1f42e424    /* v5:4.w = v6mpy(v5:4.ub, v3:2.b, #1):v */\n")
+
+TRY_FUNC(v69hvx_vasrvuhubrndsat,
+         ".word 0x1d06c465    /* v5.ub = vasr(v5:4.uh, v6.ub):rnd:sat */\n")
+TRY_FUNC(v69hvx_vasrvuhubsat,
+         ".word 0x1d06c445    /* v5.ub = vasr(v5:4.uh, v6.ub):sat */\n")
+TRY_FUNC(v69hvx_vasrvwuhrndsat,
+         ".word 0x1d06c425    /* v5.uh = vasr(v5:4.w, v6.uh):rnd:sat */\n")
+TRY_FUNC(v69hvx_vasrvwuhsat,
+         ".word 0x1d06c405    /* v5.uh = vasr(v5:4.w, v6.uh):sat */\n")
+TRY_FUNC(v69hvx_vassign_tmp,
+         ".word 0x1e014dcc    /* { v12.tmp = v13 */\n"
+         ".word 0x1c43cc04    /*    v4.w = vadd(v12.w, v3.w) } */\n")
+TRY_FUNC(v69hvx_vcombine_tmp,
+         ".word 0x1eae4fec    /* { v13:12.tmp = vcombine(v15, v14) */\n"
+         ".word 0x1c434c04    /*   v4.w = vadd(v12.w, v3.w) */\n"
+         ".word 0x1e03edf0    /*   v16 = v13 } */\n")
+TRY_FUNC(v69hvx_vmpyuhvs,
+         ".word 0x1fc5e4e4    /* v4.uh = vmpy(V4.uh, v5.uh):>>16 */\n")
+
+TRY_FUNC(v73_callrh,
+         ".word 0x50c5c000    /* callrh r5 */\n")
+TRY_FUNC(v73_jumprh,
+         ".word 0x52c0c000    /* jumprh r0 */\n")
+
+int main(void)
+{
+    struct sigaction act;
+
+    memset(&act, 0, sizeof(act));
+    act.sa_sigaction = handle_sigill;
+    act.sa_flags = SA_SIGINFO;
+    assert(sigaction(SIGILL, &act, NULL) == 0);
+
+    assert(try_v68_loadw_aq() == SIGILL);
+    assert(try_v68_loadd_aq() == SIGILL);
+    assert(try_v68_release_at() == SIGILL);
+    assert(try_v68_release_st() == SIGILL);
+    assert(try_v68_storew_rl_at() == SIGILL);
+    assert(try_v68_stored_rl_at() == SIGILL);
+    assert(try_v68_storew_rl_st() == SIGILL);
+    assert(try_v68_stored_rl_st() == SIGILL);
+
+    assert(try_v68hvx_v6mpy() == SIGILL);
+
+    assert(try_v69hvx_vasrvuhubrndsat() == SIGILL);
+    assert(try_v69hvx_vasrvuhubsat() == SIGILL);
+    assert(try_v69hvx_vasrvwuhrndsat() == SIGILL);
+    assert(try_v69hvx_vasrvwuhsat() == SIGILL);
+    assert(try_v69hvx_vassign_tmp() == SIGILL);
+    assert(try_v69hvx_vcombine_tmp() == SIGILL);
+    assert(try_v69hvx_vmpyuhvs() == SIGILL);
+
+    assert(try_v73_callrh() == SIGILL);
+    assert(try_v73_jumprh() == SIGILL);
+
+    assert(signals_handled == expected_signals);
+
+    puts("PASS");
+    return EXIT_SUCCESS;
+}
diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile.target
index f86f02bb31..0050370806 100644
--- a/tests/tcg/hexagon/Makefile.target
+++ b/tests/tcg/hexagon/Makefile.target
@@ -81,6 +81,7 @@ HEX_TESTS += test_vminh
 HEX_TESTS += test_vpmpyh
 HEX_TESTS += test_vspliceb
 
+HEX_TESTS += check_rev_gating
 HEX_TESTS += v68_scalar
 HEX_TESTS += v68_hvx
 HEX_TESTS += v69_hvx
@@ -106,6 +107,11 @@ read_write_overlap: read_write_overlap.c hex_test.h
 reg_mut: reg_mut.c hex_test.h
 unaligned_pc: unaligned_pc.c
 
+# Compile for v66 so that the ELF selects a v66 CPU; the test then
+# exercises revision gating by executing a v68 .word instruction.
+check_rev_gating: check_rev_gating.c
+	$(CC) $(CFLAGS) -mv66 -O2 $< -o $@ $(LDFLAGS)
+
 # This test has to be compiled for the -mv67t target
 usr: usr.c hex_test.h
 	$(CC) $(CFLAGS) -mv67t -O2 -Wno-inline-asm -Wno-expansion-to-defined $< -o $@ $(LDFLAGS)
-- 
2.43.0

Re: [PATCH v3 7/8] tests/tcg/hexagon: Add test for revision-gated instruction decoding

[Marco Liebel]

On Tue, Feb 17, 2026 at 3:23 PM Taylor Simpson <ltaylorsimpson@gmail.com> wrote:
>
> From: Brian Cain <brian.cain@oss.qualcomm.com>
>
> Add check_rev_gating, a linux-user test that verifies the decoder
> rejects instructions from a newer CPU revision than the one selected
> by the ELF binary's e_flags.
>
> Co-authored-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> ---
>  tests/tcg/hexagon/check_rev_gating.c | 141 +++++++++++++++++++++++++++
>  tests/tcg/hexagon/Makefile.target    |   6 ++
>  2 files changed, 147 insertions(+)
>  create mode 100644 tests/tcg/hexagon/check_rev_gating.c

Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com>

[PATCH v3 8/8] Hexagon (target/hexagon) Remove snprint_a_pkt_debug

[Taylor Simpson]

Function is not used

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
---
 target/hexagon/printinsn.h |  1 -
 target/hexagon/printinsn.c | 31 -------------------------------
 2 files changed, 32 deletions(-)

diff --git a/target/hexagon/printinsn.h b/target/hexagon/printinsn.h
index 6f84ef93c3..de962b5f2e 100644
--- a/target/hexagon/printinsn.h
+++ b/target/hexagon/printinsn.h
@@ -23,6 +23,5 @@
 
 void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
                          target_ulong pc, const HexagonCPUDef *hex_def);
-void snprint_a_pkt_debug(GString *buf, Packet *pkt);
 
 #endif
diff --git a/target/hexagon/printinsn.c b/target/hexagon/printinsn.c
index 22b305f018..a7e46f4bcd 100644
--- a/target/hexagon/printinsn.c
+++ b/target/hexagon/printinsn.c
@@ -118,34 +118,3 @@ void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
         g_string_append(buf, "  :endloop01");
     }
 }
-
-void snprint_a_pkt_debug(GString *buf, Packet *pkt)
-{
-    int slot, opcode;
-
-    if (pkt->num_insns > 1) {
-        g_string_append(buf, "\n{\n");
-    }
-
-    for (int i = 0; i < pkt->num_insns; i++) {
-        if (pkt->insn[i].part1) {
-            continue;
-        }
-        g_string_append(buf, "\t");
-        snprintinsn(buf, &(pkt->insn[i]));
-
-        if (GET_ATTRIB(pkt->insn[i].opcode, A_SUBINSN)) {
-            g_string_append(buf, " //subinsn");
-        }
-        if (pkt->insn[i].extension_valid) {
-            g_string_append(buf, " //constant extended");
-        }
-        slot = pkt->insn[i].slot;
-        opcode = pkt->insn[i].opcode;
-        g_string_append_printf(buf, " //slot=%d:tag=%s\n",
-                               slot, opcode_names[opcode]);
-    }
-    if (pkt->num_insns > 1) {
-        g_string_append(buf, "}\n");
-    }
-}
-- 
2.43.0

Re: [PATCH v3 8/8] Hexagon (target/hexagon) Remove snprint_a_pkt_debug

[Anton Johansson via qemu development]

On 17/02/26, Taylor Simpson wrote:
> Function is not used
> 
> Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> ---
>  target/hexagon/printinsn.h |  1 -
>  target/hexagon/printinsn.c | 31 -------------------------------
>  2 files changed, 32 deletions(-)

Reviewed-by: Anton Johansson <anjo@rev.ng>

Re: [PATCH v3 0/8] Hexagon (target/hexagon) Check opcodes versions

[Brian Cain]

On Tue, Feb 17, 2026 at 3:22 PM Taylor Simpson <ltaylorsimpson@gmail.com> wrote:
>
> Currently, all versions of Hexagon CPU are treated the same, and all
> opcodes are able to run on any version.  This series changes the behavior
> such that only the opcodes available on the currently executing Hexagon
> CPU version can execute.
>
> Changes include:
> Mark which Hexagon CPU version is currently executing
> Check that each opcode is supported in the Hexagon CPU version
> If not, generate INVALID_PACKET opcode, which is converted to SIGILL
> Properly handle disassembly (-d in_asm)
> Test case added

Thanks for the patches Taylor - this is queued on my hex-next-express
tree for post-11 inclusion.

> Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
> Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
>
> Changes in v2:
> - Rebase with Brian Cain's "Handle some invalid encodings" series
> - Add older opcodes to tag_rev_info.c.inc
> - Change tag_rev_info to use HexagonVersion
>       Suggested by Richard Henderson <richard.henderson@linaro.org>
> - Disassembly includes valid opcodes inside packet with invalid opcodes
> - Remove unused function - snpring_a_pkt_debug
>
> Changes in v3:
> - Use a struct to hold Hexagon definition rather than a simple enum
>       Suggested by Anton Johansson <anjo@rev.ng>
>
> Brian Cain (1):
>   tests/tcg/hexagon: Add test for revision-gated instruction decoding
>
> Matheus Tavares Bernardino (1):
>   Hexagon (target/hexagon) Introduce tag_rev_info.c.inc
>
> Taylor Simpson (6):
>   Hexagon (target/hexagon) Properly handle Hexagon CPU version
>   Hexagon (linux-user/hexagon) Identify Hexagon version in ELF file
>   Hexagon (target/hexagon) Add Hexagon definition field to DisasContext
>   Hexagon (target/hexagon) Check each opcode against current CPU
>     definition
>   Hexagon (target/hexagon) Disassembly of invalid packets
>   Hexagon (target/hexagon) Remove snprint_a_pkt_debug
>
>  target/hexagon/cpu-qom.h             |  27 ++
>  target/hexagon/cpu.h                 |   2 +
>  target/hexagon/cpu_bits.h            |   4 +-
>  target/hexagon/decode.h              |   2 +
>  target/hexagon/printinsn.h           |   4 +-
>  target/hexagon/translate.h           |   1 +
>  disas/hexagon.c                      |   3 +-
>  linux-user/hexagon/elfload.c         |  43 +-
>  target/hexagon/cpu.c                 |  48 ++-
>  target/hexagon/decode.c              |  52 ++-
>  target/hexagon/printinsn.c           |  40 +-
>  target/hexagon/translate.c           |   1 +
>  tests/tcg/hexagon/check_rev_gating.c | 141 ++++++
>  target/hexagon/tag_rev_info.c.inc    | 613 +++++++++++++++++++++++++++
>  tests/tcg/hexagon/Makefile.target    |   6 +
>  15 files changed, 911 insertions(+), 76 deletions(-)
>  create mode 100644 tests/tcg/hexagon/check_rev_gating.c
>  create mode 100644 target/hexagon/tag_rev_info.c.inc
>
> --
> 2.43.0
>