From: Sean Christopherson <seanjc@google.com>
To: Namhyung Kim <namhyung@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>, Oliver Upton <oupton@kernel.org>,
Tianrui Zhao <zhaotianrui@loongson.cn>,
Bibo Mao <maobibo@loongson.cn>,
Huacai Chen <chenhuacai@kernel.org>,
Anup Patel <anup@brainfault.org>, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Xin Li <xin@zytor.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Andy Lutomirski <luto@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
kvm@vger.kernel.org, loongarch@lists.linux.dev,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Mingwei Zhang <mizhang@google.com>,
Xudong Hao <xudong.hao@intel.com>,
Sandipan Das <sandipan.das@amd.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>,
Xiong Zhang <xiong.y.zhang@linux.intel.com>,
Manali Shukla <manali.shukla@amd.com>,
Jim Mattson <jmattson@google.com>
Subject: Re: [PATCH v6 42/44] KVM: VMX: Dedup code for adding MSR to VMCS's auto list
Date: Fri, 20 Feb 2026 08:46:07 -0800 [thread overview]
Message-ID: <aZe6UR1EGg0RcB69@google.com> (raw)
In-Reply-To: <aZdlBkLEQyv9q5ll@google.com>
On Thu, Feb 19, 2026, Namhyung Kim wrote:
> Hello,
>
> On Fri, Dec 05, 2025 at 04:17:18PM -0800, Sean Christopherson wrote:
> > Add a helper to add an MSR to a VMCS's "auto" list to deduplicate the code
> > in add_atomic_switch_msr(), and so that the functionality can be used in
> > the future for managing the MSR auto-store list.
> >
> > No functional change intended.
> >
> > Signed-off-by: Sean Christopherson <seanjc@google.com>
> > ---
> > arch/x86/kvm/vmx/vmx.c | 41 +++++++++++++++++++----------------------
> > 1 file changed, 19 insertions(+), 22 deletions(-)
> >
> > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> > index 018e01daab68..3f64d4b1b19c 100644
> > --- a/arch/x86/kvm/vmx/vmx.c
> > +++ b/arch/x86/kvm/vmx/vmx.c
> > @@ -1093,12 +1093,28 @@ static __always_inline void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
> > vm_exit_controls_setbit(vmx, exit);
> > }
> >
> > +static void vmx_add_auto_msr(struct vmx_msrs *m, u32 msr, u64 value,
> > + unsigned long vmcs_count_field, struct kvm *kvm)
> > +{
> > + int i;
> > +
> > + i = vmx_find_loadstore_msr_slot(m, msr);
> > + if (i < 0) {
> > + if (KVM_BUG_ON(m->nr == MAX_NR_LOADSTORE_MSRS, kvm))
> > + return;
> > +
> > + i = m->nr++;
> > + m->val[i].index = msr;
> > + vmcs_write32(vmcs_count_field, m->nr);
> > + }
> > + m->val[i].value = value;
> > +}
> > +
> > static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
> > u64 guest_val, u64 host_val)
> > {
> > struct msr_autoload *m = &vmx->msr_autoload;
> > struct kvm *kvm = vmx->vcpu.kvm;
> > - int i;
> >
> > switch (msr) {
> > case MSR_EFER:
> > @@ -1132,27 +1148,8 @@ static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
> > wrmsrq(MSR_IA32_PEBS_ENABLE, 0);
> > }
> >
> > - i = vmx_find_loadstore_msr_slot(&m->guest, msr);
> > - if (i < 0) {
> > - if (KVM_BUG_ON(m->guest.nr == MAX_NR_LOADSTORE_MSRS, kvm))
> > - return;
> > -
> > - i = m->guest.nr++;
> > - m->guest.val[i].index = msr;
> > - vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
> > - }
> > - m->guest.val[i].value = guest_val;
> > -
> > - i = vmx_find_loadstore_msr_slot(&m->host, msr);
> > - if (i < 0) {
> > - if (KVM_BUG_ON(m->host.nr == MAX_NR_LOADSTORE_MSRS, kvm))
> > - return;
> > -
> > - i = m->host.nr++;
> > - m->host.val[i].index = msr;
> > - vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
> > - }
> > - m->host.val[i].value = host_val;
> > + vmx_add_auto_msr(&m->guest, msr, guest_val, VM_ENTRY_MSR_LOAD_COUNT, kvm);
> > + vmx_add_auto_msr(&m->guest, msr, host_val, VM_EXIT_MSR_LOAD_COUNT, kvm);
>
> Shouldn't it be &m->host for the host_val?
Ouch. Yes. How on earth did this escape testing... Ah, because in practice
only MSR_IA32_PEBS_ENABLE goes through the load lists, and the VM-Entry load list
will use the guest's value due to VM_ENTRY_MSR_LOAD_COUNT not covering the bad
host value.
Did you happen to run into problems when using PEBS events in the host?
Regardless, do you want to send a patch? Either way, I'll figure out a way to
verify the bug and the fix.
--
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Sean Christopherson <seanjc@google.com>
To: Namhyung Kim <namhyung@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>, Oliver Upton <oupton@kernel.org>,
Tianrui Zhao <zhaotianrui@loongson.cn>,
Bibo Mao <maobibo@loongson.cn>,
Huacai Chen <chenhuacai@kernel.org>,
Anup Patel <anup@brainfault.org>, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Xin Li <xin@zytor.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Andy Lutomirski <luto@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
kvm@vger.kernel.org, loongarch@lists.linux.dev,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Mingwei Zhang <mizhang@google.com>,
Xudong Hao <xudong.hao@intel.com>,
Sandipan Das <sandipan.das@amd.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>,
Xiong Zhang <xiong.y.zhang@linux.intel.com>,
Manali Shukla <manali.shukla@amd.com>,
Jim Mattson <jmattson@google.com>
Subject: Re: [PATCH v6 42/44] KVM: VMX: Dedup code for adding MSR to VMCS's auto list
Date: Fri, 20 Feb 2026 08:46:07 -0800 [thread overview]
Message-ID: <aZe6UR1EGg0RcB69@google.com> (raw)
In-Reply-To: <aZdlBkLEQyv9q5ll@google.com>
On Thu, Feb 19, 2026, Namhyung Kim wrote:
> Hello,
>
> On Fri, Dec 05, 2025 at 04:17:18PM -0800, Sean Christopherson wrote:
> > Add a helper to add an MSR to a VMCS's "auto" list to deduplicate the code
> > in add_atomic_switch_msr(), and so that the functionality can be used in
> > the future for managing the MSR auto-store list.
> >
> > No functional change intended.
> >
> > Signed-off-by: Sean Christopherson <seanjc@google.com>
> > ---
> > arch/x86/kvm/vmx/vmx.c | 41 +++++++++++++++++++----------------------
> > 1 file changed, 19 insertions(+), 22 deletions(-)
> >
> > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> > index 018e01daab68..3f64d4b1b19c 100644
> > --- a/arch/x86/kvm/vmx/vmx.c
> > +++ b/arch/x86/kvm/vmx/vmx.c
> > @@ -1093,12 +1093,28 @@ static __always_inline void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
> > vm_exit_controls_setbit(vmx, exit);
> > }
> >
> > +static void vmx_add_auto_msr(struct vmx_msrs *m, u32 msr, u64 value,
> > + unsigned long vmcs_count_field, struct kvm *kvm)
> > +{
> > + int i;
> > +
> > + i = vmx_find_loadstore_msr_slot(m, msr);
> > + if (i < 0) {
> > + if (KVM_BUG_ON(m->nr == MAX_NR_LOADSTORE_MSRS, kvm))
> > + return;
> > +
> > + i = m->nr++;
> > + m->val[i].index = msr;
> > + vmcs_write32(vmcs_count_field, m->nr);
> > + }
> > + m->val[i].value = value;
> > +}
> > +
> > static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
> > u64 guest_val, u64 host_val)
> > {
> > struct msr_autoload *m = &vmx->msr_autoload;
> > struct kvm *kvm = vmx->vcpu.kvm;
> > - int i;
> >
> > switch (msr) {
> > case MSR_EFER:
> > @@ -1132,27 +1148,8 @@ static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
> > wrmsrq(MSR_IA32_PEBS_ENABLE, 0);
> > }
> >
> > - i = vmx_find_loadstore_msr_slot(&m->guest, msr);
> > - if (i < 0) {
> > - if (KVM_BUG_ON(m->guest.nr == MAX_NR_LOADSTORE_MSRS, kvm))
> > - return;
> > -
> > - i = m->guest.nr++;
> > - m->guest.val[i].index = msr;
> > - vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
> > - }
> > - m->guest.val[i].value = guest_val;
> > -
> > - i = vmx_find_loadstore_msr_slot(&m->host, msr);
> > - if (i < 0) {
> > - if (KVM_BUG_ON(m->host.nr == MAX_NR_LOADSTORE_MSRS, kvm))
> > - return;
> > -
> > - i = m->host.nr++;
> > - m->host.val[i].index = msr;
> > - vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
> > - }
> > - m->host.val[i].value = host_val;
> > + vmx_add_auto_msr(&m->guest, msr, guest_val, VM_ENTRY_MSR_LOAD_COUNT, kvm);
> > + vmx_add_auto_msr(&m->guest, msr, host_val, VM_EXIT_MSR_LOAD_COUNT, kvm);
>
> Shouldn't it be &m->host for the host_val?
Ouch. Yes. How on earth did this escape testing... Ah, because in practice
only MSR_IA32_PEBS_ENABLE goes through the load lists, and the VM-Entry load list
will use the guest's value due to VM_ENTRY_MSR_LOAD_COUNT not covering the bad
host value.
Did you happen to run into problems when using PEBS events in the host?
Regardless, do you want to send a patch? Either way, I'll figure out a way to
verify the bug and the fix.
WARNING: multiple messages have this Message-ID (diff)
From: Sean Christopherson <seanjc@google.com>
To: Namhyung Kim <namhyung@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>, Oliver Upton <oupton@kernel.org>,
Tianrui Zhao <zhaotianrui@loongson.cn>,
Bibo Mao <maobibo@loongson.cn>,
Huacai Chen <chenhuacai@kernel.org>,
Anup Patel <anup@brainfault.org>, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Xin Li <xin@zytor.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Andy Lutomirski <luto@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
kvm@vger.kernel.org, loongarch@lists.linux.dev,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Mingwei Zhang <mizhang@google.com>,
Xudong Hao <xudong.hao@intel.com>,
Sandipan Das <sandipan.das@amd.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>,
Xiong Zhang <xiong.y.zhang@linux.intel.com>,
Manali Shukla <manali.shukla@amd.com>,
Jim Mattson <jmattson@google.com>
Subject: Re: [PATCH v6 42/44] KVM: VMX: Dedup code for adding MSR to VMCS's auto list
Date: Fri, 20 Feb 2026 08:46:07 -0800 [thread overview]
Message-ID: <aZe6UR1EGg0RcB69@google.com> (raw)
In-Reply-To: <aZdlBkLEQyv9q5ll@google.com>
On Thu, Feb 19, 2026, Namhyung Kim wrote:
> Hello,
>
> On Fri, Dec 05, 2025 at 04:17:18PM -0800, Sean Christopherson wrote:
> > Add a helper to add an MSR to a VMCS's "auto" list to deduplicate the code
> > in add_atomic_switch_msr(), and so that the functionality can be used in
> > the future for managing the MSR auto-store list.
> >
> > No functional change intended.
> >
> > Signed-off-by: Sean Christopherson <seanjc@google.com>
> > ---
> > arch/x86/kvm/vmx/vmx.c | 41 +++++++++++++++++++----------------------
> > 1 file changed, 19 insertions(+), 22 deletions(-)
> >
> > diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> > index 018e01daab68..3f64d4b1b19c 100644
> > --- a/arch/x86/kvm/vmx/vmx.c
> > +++ b/arch/x86/kvm/vmx/vmx.c
> > @@ -1093,12 +1093,28 @@ static __always_inline void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
> > vm_exit_controls_setbit(vmx, exit);
> > }
> >
> > +static void vmx_add_auto_msr(struct vmx_msrs *m, u32 msr, u64 value,
> > + unsigned long vmcs_count_field, struct kvm *kvm)
> > +{
> > + int i;
> > +
> > + i = vmx_find_loadstore_msr_slot(m, msr);
> > + if (i < 0) {
> > + if (KVM_BUG_ON(m->nr == MAX_NR_LOADSTORE_MSRS, kvm))
> > + return;
> > +
> > + i = m->nr++;
> > + m->val[i].index = msr;
> > + vmcs_write32(vmcs_count_field, m->nr);
> > + }
> > + m->val[i].value = value;
> > +}
> > +
> > static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
> > u64 guest_val, u64 host_val)
> > {
> > struct msr_autoload *m = &vmx->msr_autoload;
> > struct kvm *kvm = vmx->vcpu.kvm;
> > - int i;
> >
> > switch (msr) {
> > case MSR_EFER:
> > @@ -1132,27 +1148,8 @@ static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
> > wrmsrq(MSR_IA32_PEBS_ENABLE, 0);
> > }
> >
> > - i = vmx_find_loadstore_msr_slot(&m->guest, msr);
> > - if (i < 0) {
> > - if (KVM_BUG_ON(m->guest.nr == MAX_NR_LOADSTORE_MSRS, kvm))
> > - return;
> > -
> > - i = m->guest.nr++;
> > - m->guest.val[i].index = msr;
> > - vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
> > - }
> > - m->guest.val[i].value = guest_val;
> > -
> > - i = vmx_find_loadstore_msr_slot(&m->host, msr);
> > - if (i < 0) {
> > - if (KVM_BUG_ON(m->host.nr == MAX_NR_LOADSTORE_MSRS, kvm))
> > - return;
> > -
> > - i = m->host.nr++;
> > - m->host.val[i].index = msr;
> > - vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
> > - }
> > - m->host.val[i].value = host_val;
> > + vmx_add_auto_msr(&m->guest, msr, guest_val, VM_ENTRY_MSR_LOAD_COUNT, kvm);
> > + vmx_add_auto_msr(&m->guest, msr, host_val, VM_EXIT_MSR_LOAD_COUNT, kvm);
>
> Shouldn't it be &m->host for the host_val?
Ouch. Yes. How on earth did this escape testing... Ah, because in practice
only MSR_IA32_PEBS_ENABLE goes through the load lists, and the VM-Entry load list
will use the guest's value due to VM_ENTRY_MSR_LOAD_COUNT not covering the bad
host value.
Did you happen to run into problems when using PEBS events in the host?
Regardless, do you want to send a patch? Either way, I'll figure out a way to
verify the bug and the fix.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2026-02-20 16:46 UTC|newest]
Thread overview: 234+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-06 0:16 [PATCH v6 00/44] KVM: x86: Add support for mediated vPMUs Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` [PATCH v6 01/44] perf: Skip pmu_ctx based on event_type Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-17 12:38 ` [tip: perf/core] " tip-bot2 for Kan Liang
2025-12-06 0:16 ` [PATCH v6 02/44] perf: Add generic exclude_guest support Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-17 12:38 ` [tip: perf/core] " tip-bot2 for Kan Liang
2025-12-06 0:16 ` [PATCH v6 03/44] perf: Move security_perf_event_free() call to __free_event() Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-17 12:38 ` [tip: perf/core] " tip-bot2 for Sean Christopherson
2025-12-06 0:16 ` [PATCH v6 04/44] perf: Add APIs to create/release mediated guest vPMUs Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-08 11:51 ` Peter Zijlstra
2025-12-08 11:51 ` Peter Zijlstra
2025-12-08 11:51 ` Peter Zijlstra
2025-12-08 18:07 ` Sean Christopherson
2025-12-08 18:07 ` Sean Christopherson
2025-12-08 18:07 ` Sean Christopherson
2025-12-17 12:37 ` [tip: perf/core] perf: Use EXPORT_SYMBOL_FOR_KVM() for the mediated APIs tip-bot2 for Peter Zijlstra
2025-12-18 8:31 ` Peter Zijlstra
2025-12-18 8:33 ` Peter Zijlstra
2025-12-18 18:40 ` Sean Christopherson
2025-12-19 7:52 ` Peter Zijlstra
2025-12-19 14:57 ` Sean Christopherson
2025-12-17 12:37 ` [tip: perf/core] perf: Clean up mediated vPMU accounting tip-bot2 for Peter Zijlstra
2025-12-19 7:58 ` [tip: perf/core] perf: Use EXPORT_SYMBOL_FOR_KVM() for the mediated APIs tip-bot2 for Peter Zijlstra
2025-12-17 12:38 ` [tip: perf/core] perf: Add APIs to create/release mediated guest vPMUs tip-bot2 for Kan Liang
2025-12-06 0:16 ` [PATCH v6 05/44] perf: Clean up perf ctx time Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-17 12:38 ` [tip: perf/core] " tip-bot2 for Kan Liang
2025-12-06 0:16 ` [PATCH v6 06/44] perf: Add a EVENT_GUEST flag Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-17 12:38 ` [tip: perf/core] " tip-bot2 for Kan Liang
2025-12-06 0:16 ` [PATCH v6 07/44] perf: Add APIs to load/put guest mediated PMU context Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-17 12:38 ` [tip: perf/core] " tip-bot2 for Kan Liang
2025-12-06 0:16 ` [PATCH v6 08/44] perf/x86/core: Register a new vector for handling mediated guest PMIs Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-17 12:38 ` [tip: perf/core] " tip-bot2 for Sean Christopherson
2025-12-06 0:16 ` [PATCH v6 09/44] perf/x86/core: Add APIs to switch to/from mediated PMI vector (for KVM) Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-17 12:38 ` [tip: perf/core] " tip-bot2 for Sean Christopherson
2025-12-06 0:16 ` [PATCH v6 10/44] perf/x86/core: Do not set bit width for unavailable counters Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-17 12:38 ` [tip: perf/core] " tip-bot2 for Sandipan Das
2025-12-06 0:16 ` [PATCH v6 11/44] perf/x86/core: Plumb mediated PMU capability from x86_pmu to x86_pmu_cap Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-17 12:38 ` [tip: perf/core] " tip-bot2 for Mingwei Zhang
2025-12-06 0:16 ` [PATCH v6 12/44] perf/x86/intel: Support PERF_PMU_CAP_MEDIATED_VPMU Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-17 12:38 ` [tip: perf/core] " tip-bot2 for Kan Liang
2025-12-06 0:16 ` [PATCH v6 13/44] perf/x86/amd: Support PERF_PMU_CAP_MEDIATED_VPMU for AMD host Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-17 12:38 ` [tip: perf/core] " tip-bot2 for Sandipan Das
2026-01-08 19:55 ` Sean Christopherson
2026-01-15 18:13 ` Sean Christopherson
2026-01-16 8:44 ` Peter Zijlstra
2026-01-16 9:36 ` Peter Zijlstra
2026-01-16 9:37 ` Peter Zijlstra
2026-01-16 14:46 ` Sean Christopherson
2025-12-06 0:16 ` [PATCH v6 14/44] KVM: Add a simplified wrapper for registering perf callbacks Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` [PATCH v6 15/44] KVM: x86/pmu: Snapshot host (i.e. perf's) reported PMU capabilities Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-25 6:26 ` Mi, Dapeng
2025-12-25 6:26 ` Mi, Dapeng
2025-12-25 6:26 ` Mi, Dapeng
2025-12-29 23:57 ` Sean Christopherson
2025-12-29 23:57 ` Sean Christopherson
2025-12-29 23:57 ` Sean Christopherson
2025-12-06 0:16 ` [PATCH v6 16/44] KVM: x86/pmu: Start stubbing in mediated PMU support Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` [PATCH v6 17/44] KVM: x86/pmu: Implement Intel mediated PMU requirements and constraints Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` [PATCH v6 18/44] KVM: x86/pmu: Implement AMD mediated PMU requirements Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` [PATCH v6 19/44] KVM: x86/pmu: Register PMI handler for mediated vPMU Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` [PATCH v6 20/44] KVM: x86/pmu: Disable RDPMC interception for compatible " Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` [PATCH v6 21/44] KVM: x86/pmu: Load/save GLOBAL_CTRL via entry/exit fields for mediated PMU Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` [PATCH v6 22/44] KVM: x86/pmu: Disable interception of select PMU MSRs for mediated vPMUs Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` [PATCH v6 23/44] KVM: x86/pmu: Bypass perf checks when emulating mediated PMU counter accesses Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:16 ` Sean Christopherson
2025-12-06 0:17 ` [PATCH v6 24/44] KVM: x86/pmu: Introduce eventsel_hw to prepare for pmu event filtering Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` [PATCH v6 25/44] KVM: x86/pmu: Reprogram mediated PMU event selectors on event filter updates Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` [PATCH v6 26/44] KVM: x86/pmu: Always stuff GuestOnly=1,HostOnly=0 for mediated PMCs on AMD Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` [PATCH v6 27/44] KVM: x86/pmu: Load/put mediated PMU context when entering/exiting guest Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` [PATCH v6 28/44] KVM: x86/pmu: Disallow emulation in the fastpath if mediated PMCs are active Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` [PATCH v6 29/44] KVM: x86/pmu: Handle emulated instruction for mediated vPMU Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` [PATCH v6 30/44] KVM: nVMX: Add macros to simplify nested MSR interception setting Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` [PATCH v6 31/44] KVM: nVMX: Disable PMU MSR interception as appropriate while running L2 Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` [PATCH v6 32/44] KVM: nSVM: " Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` [PATCH v6 33/44] KVM: x86/pmu: Expose enable_mediated_pmu parameter to user space Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` [PATCH v6 34/44] KVM: x86/pmu: Elide WRMSRs when loading guest PMCs if values already match Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` [PATCH v6 35/44] KVM: VMX: Drop intermediate "guest" field from msr_autostore Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-08 9:14 ` Mi, Dapeng
2025-12-08 9:14 ` Mi, Dapeng
2025-12-08 9:14 ` Mi, Dapeng
2025-12-06 0:17 ` [PATCH v6 36/44] KVM: nVMX: Don't update msr_autostore count when saving TSC for vmcs12 Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` [PATCH v6 37/44] KVM: VMX: Dedup code for removing MSR from VMCS's auto-load list Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-08 9:29 ` Mi, Dapeng
2025-12-08 9:29 ` Mi, Dapeng
2025-12-08 9:29 ` Mi, Dapeng
2025-12-09 17:37 ` Sean Christopherson
2025-12-09 17:37 ` Sean Christopherson
2025-12-09 17:37 ` Sean Christopherson
2025-12-10 1:08 ` Mi, Dapeng
2025-12-10 1:08 ` Mi, Dapeng
2025-12-10 1:08 ` Mi, Dapeng
2025-12-06 0:17 ` [PATCH v6 38/44] KVM: VMX: Drop unused @entry_only param from add_atomic_switch_msr() Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-08 9:32 ` Mi, Dapeng
2025-12-08 9:32 ` Mi, Dapeng
2025-12-08 9:32 ` Mi, Dapeng
2025-12-06 0:17 ` [PATCH v6 39/44] KVM: VMX: Bug the VM if either MSR auto-load list is full Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-08 9:32 ` Mi, Dapeng
2025-12-08 9:32 ` Mi, Dapeng
2025-12-08 9:32 ` Mi, Dapeng
2025-12-08 9:34 ` Mi, Dapeng
2025-12-08 9:34 ` Mi, Dapeng
2025-12-08 9:34 ` Mi, Dapeng
2026-01-08 20:04 ` Sean Christopherson
2026-01-08 20:04 ` Sean Christopherson
2026-01-08 20:04 ` Sean Christopherson
2026-01-09 0:29 ` Mi, Dapeng
2026-01-09 0:29 ` Mi, Dapeng
2026-01-09 0:29 ` Mi, Dapeng
2025-12-06 0:17 ` [PATCH v6 40/44] KVM: VMX: Set MSR index auto-load entry if and only if entry is "new" Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-08 9:35 ` Mi, Dapeng
2025-12-08 9:35 ` Mi, Dapeng
2025-12-08 9:35 ` Mi, Dapeng
2025-12-06 0:17 ` [PATCH v6 41/44] KVM: VMX: Compartmentalize adding MSRs to host vs. guest auto-load list Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-08 9:36 ` Mi, Dapeng
2025-12-08 9:36 ` Mi, Dapeng
2025-12-08 9:36 ` Mi, Dapeng
2025-12-06 0:17 ` [PATCH v6 42/44] KVM: VMX: Dedup code for adding MSR to VMCS's auto list Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-08 9:37 ` Mi, Dapeng
2025-12-08 9:37 ` Mi, Dapeng
2025-12-08 9:37 ` Mi, Dapeng
2026-02-19 19:31 ` Namhyung Kim
2026-02-19 19:31 ` Namhyung Kim
2026-02-19 19:31 ` Namhyung Kim
2026-02-20 16:46 ` Sean Christopherson [this message]
2026-02-20 16:46 ` Sean Christopherson
2026-02-20 16:46 ` Sean Christopherson
2026-02-20 19:14 ` Namhyung Kim
2026-02-20 19:14 ` Namhyung Kim
2026-02-20 19:14 ` Namhyung Kim
2025-12-06 0:17 ` [PATCH v6 43/44] KVM: VMX: Initialize vmcs01.VM_EXIT_MSR_STORE_ADDR with list address Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` [PATCH v6 44/44] KVM: VMX: Add mediated PMU support for CPUs without "save perf global ctrl" Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-06 0:17 ` Sean Christopherson
2025-12-08 9:39 ` Mi, Dapeng
2025-12-08 9:39 ` Mi, Dapeng
2025-12-08 9:39 ` Mi, Dapeng
2025-12-09 6:31 ` Mi, Dapeng
2025-12-09 6:31 ` Mi, Dapeng
2025-12-09 6:31 ` Mi, Dapeng
2025-12-08 15:37 ` [PATCH v6 00/44] KVM: x86: Add support for mediated vPMUs Peter Zijlstra
2025-12-08 15:37 ` Peter Zijlstra
2025-12-08 15:37 ` Peter Zijlstra
2025-12-18 9:19 ` Manali Shukla
2025-12-18 9:19 ` Manali Shukla
2025-12-18 9:19 ` Manali Shukla
2026-01-16 15:32 ` Sean Christopherson
2026-01-16 15:32 ` Sean Christopherson
2026-01-16 15:32 ` Sean Christopherson
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