Re: [PATCH v5 3/6] hw/riscv: implement CBQRI capacity controller

[Drew Fustini <fustini@kernel.org>]

On Mon, Mar 02, 2026 at 06:44:59PM +0000, Radim Krcmar wrote:
> 2026-02-01T15:58:09-08:00, Drew Fustini <fustini@kernel.org>:
> > From: Nicolas Pitre <npitre@baylibre.com>
> >
> > Implement a capacity controller according to the Capacity and Bandwidth
> > QoS Register Interface (CBQRI) which supports these capabilities:
> >
> >   - Number of access types: 2 (code and data)
> >   - Usage monitoring operations: CONFIG_EVENT, READ_COUNTER
> >   - Event IDs supported: None, Occupancy
> >   - Capacity allocation ops: CONFIG_LIMIT, READ_LIMIT, FLUSH_RCID
> >
> > Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0
> > Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
> > [fustini: add fields introduced in the ratified spec: cunits, rpfx, p]
> > Signed-off-by: Drew Fustini <fustini@kernel.org>
> > ---
> > diff --git a/hw/riscv/cbqri_capacity.c b/hw/riscv/cbqri_capacity.c
> > @@ -0,0 +1,733 @@
> > [...]
> > +static void riscv_cbqri_cc_write_wrapper(void *opaque, hwaddr addr,
> > +                                             uint64_t value, unsigned size)
> > +{
> > +    if (size == 4) {
> > +        uint64_t reg = riscv_cbqri_cc_read(opaque, addr & ~0x7UL, 8);
> > +        if (addr & 0x7) {
> > +            value = value << 32 | (reg & 0xffffffff);
> > +        } else {
> > +            value = value | (reg & ~0xffffffffUL);
> > +        }
> > +    }
> > +    riscv_cbqri_cc_write(opaque, addr & ~0x7UL, value, 8);
> > +}
> 
> I know I wrote it like this, but I wonder if QEMU prefers ULL or even
> MAKE_64BIT_MASK?  UL shouldn't break unless we compile with MSVC,
> 
> Reviewed-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>

Thanks for the suggestion. I'll take a look at MAKE_64BIT_MASK.

Drew