From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>,
Finley Xiao <finley.xiao@rock-chips.com>,
Frank Zhang <rmxpzlb@gmail.com>,
linux-pm@vger.kernel.org,
Detlev Casanova <detlev.casanova@collabora.com>,
Heiko Stuebner <heiko@sntech.de>,
linux-rockchip@lists.infradead.org, stable@vger.kernel.org,
Chaoyi Chen <chaoyi.chen@rock-chips.com>
Subject: Re: [PATCH v3] pmdomain: rockchip: Fix PD_VCODEC for RK3588
Date: Mon, 2 Mar 2026 23:55:44 +0100 [thread overview]
Message-ID: <aaYVOClMqnXIUvjf@venus> (raw)
In-Reply-To: <1771988101-49877-1-git-send-email-shawn.lin@rock-chips.com>
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Hi,
On Wed, Feb 25, 2026 at 10:55:01AM +0800, Shawn Lin wrote:
> From the RK3588 TRM Table 7-1 RK3588 Voltage Domain and Power Domain Summary,
> PD_RKVDEC0/1 and PD_VENC0/1 rely on VD_VCODEC which require extra voltages to
> be applied, otherwise it breaks RK3588-evb1-v10 board after vdec support landed[1].
> The panic looks like below:
>
> rockchip-pm-domain fd8d8000.power-management:power-controller: failed to set domain 'rkvdec0' on, val=0
> rockchip-pm-domain fd8d8000.power-management:power-controller: failed to set domain 'rkvdec1' on, val=0
> ...
> Hardware name: Rockchip RK3588S EVB1 V10 Board (DT)
> Workqueue: pm genpd_power_off_work_fn
> Call trace:
> show_stack+0x18/0x24 (C)
> dump_stack_lvl+0x40/0x84
> dump_stack+0x18/0x24
> vpanic+0x1ec/0x4fc
> vpanic+0x0/0x4fc
> check_panic_on_warn+0x0/0x94
> arm64_serror_panic+0x6c/0x78
> do_serror+0xc4/0xcc
> el1h_64_error_handler+0x3c/0x5c
> el1h_64_error+0x6c/0x70
> regmap_mmio_read32le+0x18/0x24 (P)
> regmap_bus_reg_read+0xfc/0x130
> regmap_read+0x188/0x1ac
> regmap_read+0x54/0x78
> rockchip_pd_power+0xcc/0x5f0
> rockchip_pd_power_off+0x1c/0x4c
> genpd_power_off+0x84/0x120
> genpd_power_off+0x1b4/0x260
> genpd_power_off_work_fn+0x38/0x58
> process_scheduled_works+0x194/0x2c4
> worker_thread+0x2ac/0x3d8
> kthread+0x104/0x124
> ret_from_fork+0x10/0x20
> SMP: stopping secondary CPUs
> Kernel Offset: disabled
> CPU features: 0x3000000,000e0005,40230521,0400720b
> Memory Limit: none
> ---[ end Kernel panic - not syncing: Asynchronous SError Interrupt ]---
>
> Chaoyi pointed out the PD_VCODEC is the parent of PD_RKVDEC0/1 and PD_VENC0/1, so checking
> the PD_VCODEC is enough.
>
> [1] https://lore.kernel.org/linux-rockchip/20251020212009.8852-2-detlev.casanova@collabora.com/
> Fixes: db6df2e3fc16 ("pmdomain: rockchip: add regulator support")
> Cc: stable@vger.kernel.org
> Suggested-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>
> ---
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Greetings,
-- Sebastian
>
> Changes in v3:
> - drop tags
> - rework it for just changing PD_VCODEC(chaoyi)
>
> Changes in v2:
> - collect tags
> - correct TRM section(Sebastian)
>
> drivers/pmdomain/rockchip/pm-domains.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
> index 997e93c..44d3484 100644
> --- a/drivers/pmdomain/rockchip/pm-domains.c
> +++ b/drivers/pmdomain/rockchip/pm-domains.c
> @@ -1311,7 +1311,7 @@ static const struct rockchip_domain_info rk3576_pm_domains[] = {
> static const struct rockchip_domain_info rk3588_pm_domains[] = {
> [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false, true),
> [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false, true),
> - [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false, false),
> + [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false, true),
> [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false, false),
> [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false, false),
> [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false, false),
> --
> 2.7.4
>
>
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WARNING: multiple messages have this Message-ID (diff)
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>,
Finley Xiao <finley.xiao@rock-chips.com>,
Frank Zhang <rmxpzlb@gmail.com>,
linux-pm@vger.kernel.org,
Detlev Casanova <detlev.casanova@collabora.com>,
Heiko Stuebner <heiko@sntech.de>,
linux-rockchip@lists.infradead.org, stable@vger.kernel.org,
Chaoyi Chen <chaoyi.chen@rock-chips.com>
Subject: Re: [PATCH v3] pmdomain: rockchip: Fix PD_VCODEC for RK3588
Date: Mon, 2 Mar 2026 23:55:44 +0100 [thread overview]
Message-ID: <aaYVOClMqnXIUvjf@venus> (raw)
In-Reply-To: <1771988101-49877-1-git-send-email-shawn.lin@rock-chips.com>
[-- Attachment #1.1: Type: text/plain, Size: 3805 bytes --]
Hi,
On Wed, Feb 25, 2026 at 10:55:01AM +0800, Shawn Lin wrote:
> From the RK3588 TRM Table 7-1 RK3588 Voltage Domain and Power Domain Summary,
> PD_RKVDEC0/1 and PD_VENC0/1 rely on VD_VCODEC which require extra voltages to
> be applied, otherwise it breaks RK3588-evb1-v10 board after vdec support landed[1].
> The panic looks like below:
>
> rockchip-pm-domain fd8d8000.power-management:power-controller: failed to set domain 'rkvdec0' on, val=0
> rockchip-pm-domain fd8d8000.power-management:power-controller: failed to set domain 'rkvdec1' on, val=0
> ...
> Hardware name: Rockchip RK3588S EVB1 V10 Board (DT)
> Workqueue: pm genpd_power_off_work_fn
> Call trace:
> show_stack+0x18/0x24 (C)
> dump_stack_lvl+0x40/0x84
> dump_stack+0x18/0x24
> vpanic+0x1ec/0x4fc
> vpanic+0x0/0x4fc
> check_panic_on_warn+0x0/0x94
> arm64_serror_panic+0x6c/0x78
> do_serror+0xc4/0xcc
> el1h_64_error_handler+0x3c/0x5c
> el1h_64_error+0x6c/0x70
> regmap_mmio_read32le+0x18/0x24 (P)
> regmap_bus_reg_read+0xfc/0x130
> regmap_read+0x188/0x1ac
> regmap_read+0x54/0x78
> rockchip_pd_power+0xcc/0x5f0
> rockchip_pd_power_off+0x1c/0x4c
> genpd_power_off+0x84/0x120
> genpd_power_off+0x1b4/0x260
> genpd_power_off_work_fn+0x38/0x58
> process_scheduled_works+0x194/0x2c4
> worker_thread+0x2ac/0x3d8
> kthread+0x104/0x124
> ret_from_fork+0x10/0x20
> SMP: stopping secondary CPUs
> Kernel Offset: disabled
> CPU features: 0x3000000,000e0005,40230521,0400720b
> Memory Limit: none
> ---[ end Kernel panic - not syncing: Asynchronous SError Interrupt ]---
>
> Chaoyi pointed out the PD_VCODEC is the parent of PD_RKVDEC0/1 and PD_VENC0/1, so checking
> the PD_VCODEC is enough.
>
> [1] https://lore.kernel.org/linux-rockchip/20251020212009.8852-2-detlev.casanova@collabora.com/
> Fixes: db6df2e3fc16 ("pmdomain: rockchip: add regulator support")
> Cc: stable@vger.kernel.org
> Suggested-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>
> ---
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Greetings,
-- Sebastian
>
> Changes in v3:
> - drop tags
> - rework it for just changing PD_VCODEC(chaoyi)
>
> Changes in v2:
> - collect tags
> - correct TRM section(Sebastian)
>
> drivers/pmdomain/rockchip/pm-domains.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
> index 997e93c..44d3484 100644
> --- a/drivers/pmdomain/rockchip/pm-domains.c
> +++ b/drivers/pmdomain/rockchip/pm-domains.c
> @@ -1311,7 +1311,7 @@ static const struct rockchip_domain_info rk3576_pm_domains[] = {
> static const struct rockchip_domain_info rk3588_pm_domains[] = {
> [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false, true),
> [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false, true),
> - [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false, false),
> + [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false, true),
> [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false, false),
> [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false, false),
> [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false, false),
> --
> 2.7.4
>
>
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next prev parent reply other threads:[~2026-03-02 22:56 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-25 2:55 [PATCH v3] pmdomain: rockchip: Fix PD_VCODEC for RK3588 Shawn Lin
2026-02-25 2:55 ` Shawn Lin
2026-02-25 6:51 ` Chaoyi Chen
2026-02-25 6:51 ` Chaoyi Chen
2026-03-02 22:55 ` Sebastian Reichel [this message]
2026-03-02 22:55 ` Sebastian Reichel
2026-03-04 11:24 ` Ulf Hansson
2026-03-04 11:24 ` Ulf Hansson
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