Re: [PATCH v3 19/25] drm/xe: Add ULLS support to LRC

[Francois Dugast <francois.dugast@intel.com>]

On Fri, Feb 27, 2026 at 05:34:55PM -0800, Matthew Brost wrote:
> Define memory layout for ULLS semaphores stored in LRC memory. Add
> support functions to return GGTT address and set semaphore based on a
> job's seqno.
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_lrc.c       | 51 +++++++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_lrc.h       |  3 ++
>  drivers/gpu/drm/xe/xe_lrc_types.h |  4 +++
>  3 files changed, 58 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index 384f9b31421e..44fb600bd228 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -718,6 +718,7 @@ u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc)
>  #define LRC_CTX_JOB_TIMESTAMP_OFFSET 512
>  #define LRC_ENGINE_ID_PPHWSP_OFFSET 1024
>  #define LRC_PARALLEL_PPHWSP_OFFSET 2048
> +#define LRC_ULLS_PPHWSP_OFFSET 2048	/* Mutually exclusive with parallel */
>  
>  #define LRC_SEQNO_OFFSET 0
>  #define LRC_START_SEQNO_OFFSET (LRC_SEQNO_OFFSET + 8)
> @@ -773,6 +774,12 @@ static inline u32 __xe_lrc_engine_id_offset(struct xe_lrc *lrc)
>  	return xe_lrc_pphwsp_offset(lrc) + LRC_ENGINE_ID_PPHWSP_OFFSET;
>  }
>  
> +static u32 __xe_lrc_ulls_offset(struct xe_lrc *lrc)
> +{
> +	/* The ulls is stored in the driver-defined portion of PPHWSP */
> +	return xe_lrc_pphwsp_offset(lrc) + LRC_ULLS_PPHWSP_OFFSET;
> +}
> +
>  static u32 __xe_lrc_ctx_timestamp_offset(struct xe_lrc *lrc)
>  {
>  	return __xe_lrc_regs_offset(lrc) + CTX_TIMESTAMP * sizeof(u32);
> @@ -830,6 +837,7 @@ DECL_MAP_ADDR_HELPERS(ctx_job_timestamp, lrc->bo)
>  DECL_MAP_ADDR_HELPERS(ctx_timestamp, lrc->bo)
>  DECL_MAP_ADDR_HELPERS(ctx_timestamp_udw, lrc->bo)
>  DECL_MAP_ADDR_HELPERS(parallel, lrc->bo)
> +DECL_MAP_ADDR_HELPERS(ulls, lrc->bo)
>  DECL_MAP_ADDR_HELPERS(indirect_ring, lrc->bo)
>  DECL_MAP_ADDR_HELPERS(engine_id, lrc->bo)
>  
> @@ -1860,6 +1868,49 @@ static u32 xe_lrc_engine_id(struct xe_lrc *lrc)
>  	return xe_map_read32(xe, &map);
>  }
>  
> +#define semaphore_offset(seqno) \
> +	(sizeof(u32) * ((seqno) % LRC_MIGRATION_ULLS_SEMAPORE_COUNT))
> +
> +/**
> + * xe_lrc_ulls_semaphore_ggtt_addr() - ULLS semaphore GGTT address
> + * @lrc: Pointer to the lrc.
> + * @seqno: seqno of current job.
> + *
> + * Calculate ULLS semaphore GGTT address based on input seqno
> + *
> + * Returns: ULLS semaphore GGTT address
> + */
> +u32 xe_lrc_ulls_semaphore_ggtt_addr(struct xe_lrc *lrc, u32 seqno)
> +{
> +	xe_assert(lrc_to_xe(lrc), semaphore_offset(seqno) <
> +		  LRC_PPHWSP_SIZE - LRC_ULLS_PPHWSP_OFFSET);
> +
> +	return __xe_lrc_ulls_ggtt_addr(lrc) + semaphore_offset(seqno);
> +}
> +
> +/**
> + * xe_lrc_set_ulls_semaphore() - Set ULLS semaphore
> + * @lrc: Pointer to the lrc.
> + * @seqno: seqno of current job.
> + *
> + * Set ULLS semaphore based on input seqno
> + */
> +void xe_lrc_set_ulls_semaphore(struct xe_lrc *lrc, u32 seqno)
> +{
> +	struct xe_device *xe = lrc_to_xe(lrc);
> +	struct iosys_map map = __xe_lrc_ulls_map(lrc);
> +
> +	xe_assert(xe, semaphore_offset(seqno) <
> +		  LRC_PPHWSP_SIZE - LRC_ULLS_PPHWSP_OFFSET);
> +
> +	xe_device_wmb(xe);	/* Ensure everything before in code is ordered */
> +
> +	iosys_map_incr(&map, semaphore_offset(seqno));
> +	xe_map_write32(xe, &map, LRC_MIGRATION_ULLS_SEMAPORE_SINGAL);
> +
> +	xe_device_wmb(xe);	/* Flush write to hardware */
> +}
> +
>  static int instr_dw(u32 cmd_header)
>  {
>  	/* GFXPIPE "SINGLE_DW" opcodes are a single dword */
> diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h
> index 48f7c26cf129..9e51222191ea 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.h
> +++ b/drivers/gpu/drm/xe/xe_lrc.h
> @@ -111,6 +111,9 @@ void xe_default_lrc_update_memirq_regs_with_address(struct xe_hw_engine *hwe);
>  void xe_lrc_update_memirq_regs_with_address(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
>  					    u32 *regs);
>  
> +u32 xe_lrc_ulls_semaphore_ggtt_addr(struct xe_lrc *lrc, u32 seqno);
> +void xe_lrc_set_ulls_semaphore(struct xe_lrc *lrc, u32 seqno);
> +
>  u32 xe_lrc_read_ctx_reg(struct xe_lrc *lrc, int reg_nr);
>  void xe_lrc_write_ctx_reg(struct xe_lrc *lrc, int reg_nr, u32 val);
>  
> diff --git a/drivers/gpu/drm/xe/xe_lrc_types.h b/drivers/gpu/drm/xe/xe_lrc_types.h
> index 5a718f759ed6..7cf84e32f998 100644
> --- a/drivers/gpu/drm/xe/xe_lrc_types.h
> +++ b/drivers/gpu/drm/xe/xe_lrc_types.h
> @@ -12,6 +12,10 @@
>  
>  struct xe_bo;
>  
> +#define LRC_MIGRATION_ULLS_SEMAPORE_COUNT	64	/* Must be pow2 */
> +#define LRC_MIGRATION_ULLS_SEMAPORE_CLEAR	0
> +#define LRC_MIGRATION_ULLS_SEMAPORE_SINGAL	1

s/SEMAPORE/SEMAPHORE/
s/SINGAL/SIGNAL/

> +
>  /**
>   * struct xe_lrc - Logical ring context (LRC) and submission ring object
>   */
> -- 
> 2.34.1
>