* [PATCH 6.12.y-cip 1/2] arm64: dts: renesas: r9a09g077: Add DT nodes for SCI channels 1-5
2026-03-11 12:36 [PATCH 6.12.y-cip 0/2] arm64: dts: renesas: r9a09g077/r9a09g087: Add DT nodes for SCI channels 1-5 Lad Prabhakar
@ 2026-03-11 12:36 ` Lad Prabhakar
2026-03-11 12:36 ` [PATCH 6.12.y-cip 2/2] arm64: dts: renesas: r9a09g087: " Lad Prabhakar
2026-03-18 22:11 ` [cip-dev] [PATCH 6.12.y-cip 0/2] arm64: dts: renesas: r9a09g077/r9a09g087: " Nobuhiro Iwamatsu (Toshiba)
2 siblings, 0 replies; 6+ messages in thread
From: Lad Prabhakar @ 2026-03-11 12:36 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit be5d60d94b982d46a734750d93624bd85a1c7089 upstream.
The RZ/T2H SoC exposes six SCI controllers; sci0 was already present in
the SoC DTSI. Add the remaining SCI nodes (sci1-sci5).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250812200344.3253781-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: manually fixed merge conflicts]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 70 ++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 78436a486ffe3..2c9bff718cbc3 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -90,6 +90,76 @@ sci0: serial@80005000 {
status = "disabled";
};
+ sci1: serial@80005400 {
+ compatible = "renesas,r9a09g077-rsci";
+ reg = <0 0x80005400 0 0x400>;
+ interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+ clock-names = "operation", "bus";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sci2: serial@80005800 {
+ compatible = "renesas,r9a09g077-rsci";
+ reg = <0 0x80005800 0 0x400>;
+ interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+ clock-names = "operation", "bus";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sci3: serial@80005c00 {
+ compatible = "renesas,r9a09g077-rsci";
+ reg = <0 0x80005c00 0 0x400>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+ clock-names = "operation", "bus";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sci4: serial@80006000 {
+ compatible = "renesas,r9a09g077-rsci";
+ reg = <0 0x80006000 0 0x400>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+ clock-names = "operation", "bus";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sci5: serial@81005000 {
+ compatible = "renesas,r9a09g077-rsci";
+ reg = <0 0x81005000 0 0x400>;
+ interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+ clock-names = "operation", "bus";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
rspi0: spi@80007000 {
compatible = "renesas,r9a09g077-rspi";
reg = <0x0 0x80007000 0x0 0x400>;
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 6.12.y-cip 2/2] arm64: dts: renesas: r9a09g087: Add DT nodes for SCI channels 1-5
2026-03-11 12:36 [PATCH 6.12.y-cip 0/2] arm64: dts: renesas: r9a09g077/r9a09g087: Add DT nodes for SCI channels 1-5 Lad Prabhakar
2026-03-11 12:36 ` [PATCH 6.12.y-cip 1/2] arm64: dts: renesas: r9a09g077: " Lad Prabhakar
@ 2026-03-11 12:36 ` Lad Prabhakar
2026-03-18 22:11 ` [cip-dev] [PATCH 6.12.y-cip 0/2] arm64: dts: renesas: r9a09g077/r9a09g087: " Nobuhiro Iwamatsu (Toshiba)
2 siblings, 0 replies; 6+ messages in thread
From: Lad Prabhakar @ 2026-03-11 12:36 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das
commit 41e194978510a9910be2ed7b4d8b4edb61671a90 upstream.
The RZ/N2H SoC exposes six SCI controllers; sci0 was already present in
the SoC DTSI. Add the remaining SCI nodes (sci1-sci5).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250812200344.3253781-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: manually fixed merge conflicts]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 70 ++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index c056c476e0d7f..47a9888e227dc 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -90,6 +90,76 @@ sci0: serial@80005000 {
status = "disabled";
};
+ sci1: serial@80005400 {
+ compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
+ reg = <0 0x80005400 0 0x400>;
+ interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
+ clock-names = "operation", "bus";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sci2: serial@80005800 {
+ compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
+ reg = <0 0x80005800 0 0x400>;
+ interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
+ clock-names = "operation", "bus";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sci3: serial@80005c00 {
+ compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
+ reg = <0 0x80005c00 0 0x400>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
+ clock-names = "operation", "bus";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sci4: serial@80006000 {
+ compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
+ reg = <0 0x80006000 0 0x400>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
+ clock-names = "operation", "bus";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ sci5: serial@81005000 {
+ compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci";
+ reg = <0 0x81005000 0 0x400>;
+ interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
+ clock-names = "operation", "bus";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
rspi0: spi@80007000 {
compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi";
reg = <0x0 0x80007000 0x0 0x400>;
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [cip-dev] [PATCH 6.12.y-cip 0/2] arm64: dts: renesas: r9a09g077/r9a09g087: Add DT nodes for SCI channels 1-5
2026-03-11 12:36 [PATCH 6.12.y-cip 0/2] arm64: dts: renesas: r9a09g077/r9a09g087: Add DT nodes for SCI channels 1-5 Lad Prabhakar
2026-03-11 12:36 ` [PATCH 6.12.y-cip 1/2] arm64: dts: renesas: r9a09g077: " Lad Prabhakar
2026-03-11 12:36 ` [PATCH 6.12.y-cip 2/2] arm64: dts: renesas: r9a09g087: " Lad Prabhakar
@ 2026-03-18 22:11 ` Nobuhiro Iwamatsu (Toshiba)
2026-03-19 8:48 ` Pavel Machek
2 siblings, 1 reply; 6+ messages in thread
From: Nobuhiro Iwamatsu (Toshiba) @ 2026-03-18 22:11 UTC (permalink / raw)
To: prabhakar.mahadev-lad.rj
Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das
Hi all,
2026年3月11日(水) 21:36 Lad Prabhakar via lists.cip-project.org
<prabhakar.mahadev-lad.rj=bp.renesas.com@lists.cip-project.org>:
>
> Hi all,
>
> The RZ/T2H and RZ/N2H SoCs expose six SCI controllers; sci0 was already
> present in the SoC DTSI. This patch adds the remaining SCI nodes
> (sci1-sci5) to the respective SoC DTSIs.
>
> Note the patches have been picked up from upstream and manually merged
> to resolve conflicts.
>
> Note, these patches apply on top of the RSPI series [0].
>
> [0] https://lore.kernel.org/all/20260309150619.761962-1-cosmin-gabriel.tanislav.xa@renesas.com/
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (2):
> arm64: dts: renesas: r9a09g077: Add DT nodes for SCI channels 1-5
> arm64: dts: renesas: r9a09g087: Add DT nodes for SCI channels 1-5
>
> arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 70 ++++++++++++++++++++++
> arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 70 ++++++++++++++++++++++
> 2 files changed, 140 insertions(+)
I reviewed this series, looks good to me.
I can apply this, if tests are OK and there is no other comment.
Best regards,
Nobuhiro
--
Nobuhiro Iwamatsu
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [cip-dev] [PATCH 6.12.y-cip 0/2] arm64: dts: renesas: r9a09g077/r9a09g087: Add DT nodes for SCI channels 1-5
2026-03-18 22:11 ` [cip-dev] [PATCH 6.12.y-cip 0/2] arm64: dts: renesas: r9a09g077/r9a09g087: " Nobuhiro Iwamatsu (Toshiba)
@ 2026-03-19 8:48 ` Pavel Machek
2026-03-24 9:11 ` nobuhiro.iwamatsu.x90
0 siblings, 1 reply; 6+ messages in thread
From: Pavel Machek @ 2026-03-19 8:48 UTC (permalink / raw)
To: Nobuhiro Iwamatsu (Toshiba)
Cc: prabhakar.mahadev-lad.rj, cip-dev, Nobuhiro Iwamatsu,
Pavel Machek, Biju Das
[-- Attachment #1: Type: text/plain, Size: 1170 bytes --]
Hi!
> > The RZ/T2H and RZ/N2H SoCs expose six SCI controllers; sci0 was already
> > present in the SoC DTSI. This patch adds the remaining SCI nodes
> > (sci1-sci5) to the respective SoC DTSIs.
> >
> > Note the patches have been picked up from upstream and manually merged
> > to resolve conflicts.
> >
> > Note, these patches apply on top of the RSPI series [0].
> >
> > [0] https://lore.kernel.org/all/20260309150619.761962-1-cosmin-gabriel.tanislav.xa@renesas.com/
> >
> > Cheers,
> > Prabhakar
> >
> > Lad Prabhakar (2):
> > arm64: dts: renesas: r9a09g077: Add DT nodes for SCI channels 1-5
> > arm64: dts: renesas: r9a09g087: Add DT nodes for SCI channels 1-5
> >
> > arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 70 ++++++++++++++++++++++
> > arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 70 ++++++++++++++++++++++
> > 2 files changed, 140 insertions(+)
>
> I reviewed this series, looks good to me.
> I can apply this, if tests are OK and there is no other comment.
Looks good to me, too.
Reviewed-by: Pavel Machek <pavel@nabladev.com>
Best regards,
Pavel
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 6+ messages in thread* RE: [cip-dev] [PATCH 6.12.y-cip 0/2] arm64: dts: renesas: r9a09g077/r9a09g087: Add DT nodes for SCI channels 1-5
2026-03-19 8:48 ` Pavel Machek
@ 2026-03-24 9:11 ` nobuhiro.iwamatsu.x90
0 siblings, 0 replies; 6+ messages in thread
From: nobuhiro.iwamatsu.x90 @ 2026-03-24 9:11 UTC (permalink / raw)
To: pavel, iwamatsu; +Cc: prabhakar.mahadev-lad.rj, cip-dev, biju.das.jz
Hi all,
> -----Original Message-----
> From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On Behalf Of Pavel Machek via lists.cip-project.org
> Sent: Thursday, March 19, 2026 5:48 PM
> To: Nobuhiro Iwamatsu (Toshiba) <iwamatsu@gmail.com>
> Cc: prabhakar.mahadev-lad.rj@bp.renesas.com; cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 □ＤＩＴ
> Ｃ○ＣＰＴ) <nobuhiro.iwamatsu.x90@mail.toshiba>; Pavel Machek <pavel@nabladev.com>; Biju Das
> <biju.das.jz@bp.renesas.com>
> Subject: Re: [cip-dev] [PATCH 6.12.y-cip 0/2] arm64: dts: renesas: r9a09g077/r9a09g087: Add DT nodes for SCI channels
> 1-5
>
> Hi!
>
> > > The RZ/T2H and RZ/N2H SoCs expose six SCI controllers; sci0 was
> > > already present in the SoC DTSI. This patch adds the remaining SCI
> > > nodes
> > > (sci1-sci5) to the respective SoC DTSIs.
> > >
> > > Note the patches have been picked up from upstream and manually
> > > merged to resolve conflicts.
> > >
> > > Note, these patches apply on top of the RSPI series [0].
> > >
> > > [0]
> > > https://lore.kernel.org/all/20260309150619.761962-1-cosmin-gabriel.t
> > > anislav.xa@renesas.com/
> > >
> > > Cheers,
> > > Prabhakar
> > >
> > > Lad Prabhakar (2):
> > > arm64: dts: renesas: r9a09g077: Add DT nodes for SCI channels 1-5
> > > arm64: dts: renesas: r9a09g087: Add DT nodes for SCI channels 1-5
> > >
> > > arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 70
> > > ++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a09g087.dtsi |
> > > 70 ++++++++++++++++++++++
> > > 2 files changed, 140 insertions(+)
> >
> > I reviewed this series, looks good to me.
> > I can apply this, if tests are OK and there is no other comment.
>
> Looks good to me, too.
>
> Reviewed-by: Pavel Machek <pavel@nabladev.com>
>
> Best regards,
> Pavel
Thanks, I applied and pushed.
Best regards,
Nobuhiro
^ permalink raw reply [flat|nested] 6+ messages in thread