From: Magnus Kulke <magnuskulke@linux.microsoft.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: qemu-devel@nongnu.org, Wei Liu <wei.liu@kernel.org>,
Wei Liu <liuwe@microsoft.com>,
Magnus Kulke <magnuskulke@microsoft.com>,
Zhao Liu <zhao1.liu@intel.com>
Subject: Re: [PATCH v4 8/9] target/i386/mshv: filter out CET bits in cpuid
Date: Wed, 15 Apr 2026 16:18:32 +0200 [thread overview]
Message-ID: <ad+eOA8gz26GBgzD@example.com> (raw)
In-Reply-To: <32594f82-0268-4844-830a-4147bd1598f6@redhat.com>
On Tue, Apr 14, 2026 at 06:10:19PM +0200, Paolo Bonzini wrote:
> I don't understand this, but it seems to be a Linux bug. Don't *all* xsave
> features cause changes to CPUID[0xD,1].EBX?
oh, you're right, thx. the CPUID[0xD,1].EBX responses (also CPUID[0xD,0])
returned wrong responses in all cases the introduction of CET in QEMU
probably just triggered some overflow, but it was broken before.
We cannot statically register size responses for xsave features that a
guest can dynamically enable/disable.
I was planning to implement a dynamic handler for the xsave size
responses anyway, but maybe there's an easier way: We can provide an ebx
mask = 0 in the payload when we register the cpuid responses at the
hypervisor. If we do that for CPUID[0xD,{0,1}], the hypervisor should
return the answer based on the guest state (XCR0,XSS).
I'll test this approach and probably post a new revision with one of
those options.
next prev parent reply other threads:[~2026-04-15 14:19 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-14 15:54 [PATCH v4 0/9] Support QEMU cpu models in MSHV accelerator Magnus Kulke
2026-04-14 15:54 ` [PATCH v4 1/9] accel/mshv: use mshv_create_partition_v2 payload Magnus Kulke
2026-04-14 15:54 ` [PATCH v4 2/9] target/i386/mshv: fix cpuid propagation bug Magnus Kulke
2026-04-14 15:54 ` [PATCH v4 3/9] target/i386/mshv: fix various cpuid traversal bugs Magnus Kulke
2026-04-14 15:54 ` [PATCH v4 4/9] target/i386/mshv: change cpuid mask to UINT32_MAX Magnus Kulke
2026-04-14 15:54 ` [PATCH v4 5/9] target/i386/mshv: set cpu model name on -cpu host Magnus Kulke
2026-04-14 15:54 ` [PATCH v4 6/9] target/i386: query mshv accel for supported cpuids Magnus Kulke
2026-04-14 15:54 ` [PATCH v4 7/9] target/i386/mshv: populate xsave area offsets Magnus Kulke
2026-04-14 15:54 ` [PATCH v4 8/9] target/i386/mshv: filter out CET bits in cpuid Magnus Kulke
2026-04-14 16:10 ` Paolo Bonzini
2026-04-15 14:18 ` Magnus Kulke [this message]
2026-04-15 14:30 ` Mohamed Mediouni
2026-04-15 15:26 ` Magnus Kulke
2026-04-14 15:54 ` [PATCH v4 9/9] accel/mshv: disable la57 (5lvl paging) Magnus Kulke
2026-04-14 20:56 ` Wei Liu
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