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From: Niklas Cassel <cassel@kernel.org>
To: Anand Moon <linux.amoon@gmail.com>, Shawn Lin <shawn.lin@rock-chips.com>
Cc: Vinod Koul <vkoul@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	"open list:GENERIC PHY FRAMEWORK" <linux-phy@lists.infradead.org>,
	"moderated list:ARM/Rockchip SoC support"
	<linux-arm-kernel@lists.infradead.org>,
	"open list:ARM/Rockchip SoC support"
	<linux-rockchip@lists.infradead.org>,
	open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v1] phy: rockchip-snps-pcie3:phy: Configure clkreq_n and PowerDown for all lanes
Date: Thu, 9 Apr 2026 11:49:52 +0200	[thread overview]
Message-ID: <add2QFfHd5Jv9XU7@fedora> (raw)
In-Reply-To: <20260409044939.7647-1-linux.amoon@gmail.com>

+Shawn

Hello Anand,

On Thu, Apr 09, 2026 at 10:19:30AM +0530, Anand Moon wrote:
> During the rk3588_p3phy_init sequence, the driver now explicitly

Please use imperative mood, active voice.


> configures each lane's CON0 register to ensure
> - PIPE 4.3 Compliance: clkreq_n (bit 6) is forced low (asserted) to meet
>   sideband signal requirements.
> - Active Power State: PowerDown[3:0] (bits 11:8) is set to P0
>   (Normal Operational State) to ensure the PHY is fully powered and ready
>   for link training.
> 
> These changes ensure that all lanes are consistently transitioned from
> reset into a known-good operational state, preventing undefined behavior
> and ensuring the PHY is ready for high-speed data transmission.

First describe the problem, then describe how you fix it.


Kind regards,
Niklas


WARNING: multiple messages have this Message-ID (diff)
From: Niklas Cassel <cassel@kernel.org>
To: Anand Moon <linux.amoon@gmail.com>, Shawn Lin <shawn.lin@rock-chips.com>
Cc: Vinod Koul <vkoul@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	"open list:GENERIC PHY FRAMEWORK" <linux-phy@lists.infradead.org>,
	"moderated list:ARM/Rockchip SoC support"
	<linux-arm-kernel@lists.infradead.org>,
	"open list:ARM/Rockchip SoC support"
	<linux-rockchip@lists.infradead.org>,
	open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v1] phy: rockchip-snps-pcie3:phy: Configure clkreq_n and PowerDown for all lanes
Date: Thu, 9 Apr 2026 11:49:52 +0200	[thread overview]
Message-ID: <add2QFfHd5Jv9XU7@fedora> (raw)
In-Reply-To: <20260409044939.7647-1-linux.amoon@gmail.com>

+Shawn

Hello Anand,

On Thu, Apr 09, 2026 at 10:19:30AM +0530, Anand Moon wrote:
> During the rk3588_p3phy_init sequence, the driver now explicitly

Please use imperative mood, active voice.


> configures each lane's CON0 register to ensure
> - PIPE 4.3 Compliance: clkreq_n (bit 6) is forced low (asserted) to meet
>   sideband signal requirements.
> - Active Power State: PowerDown[3:0] (bits 11:8) is set to P0
>   (Normal Operational State) to ensure the PHY is fully powered and ready
>   for link training.
> 
> These changes ensure that all lanes are consistently transitioned from
> reset into a known-good operational state, preventing undefined behavior
> and ensuring the PHY is ready for high-speed data transmission.

First describe the problem, then describe how you fix it.


Kind regards,
Niklas

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: Niklas Cassel <cassel@kernel.org>
To: Anand Moon <linux.amoon@gmail.com>, Shawn Lin <shawn.lin@rock-chips.com>
Cc: Vinod Koul <vkoul@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	"open list:GENERIC PHY FRAMEWORK" <linux-phy@lists.infradead.org>,
	"moderated list:ARM/Rockchip SoC support"
	<linux-arm-kernel@lists.infradead.org>,
	"open list:ARM/Rockchip SoC support"
	<linux-rockchip@lists.infradead.org>,
	open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v1] phy: rockchip-snps-pcie3:phy: Configure clkreq_n and PowerDown for all lanes
Date: Thu, 9 Apr 2026 11:49:52 +0200	[thread overview]
Message-ID: <add2QFfHd5Jv9XU7@fedora> (raw)
In-Reply-To: <20260409044939.7647-1-linux.amoon@gmail.com>

+Shawn

Hello Anand,

On Thu, Apr 09, 2026 at 10:19:30AM +0530, Anand Moon wrote:
> During the rk3588_p3phy_init sequence, the driver now explicitly

Please use imperative mood, active voice.


> configures each lane's CON0 register to ensure
> - PIPE 4.3 Compliance: clkreq_n (bit 6) is forced low (asserted) to meet
>   sideband signal requirements.
> - Active Power State: PowerDown[3:0] (bits 11:8) is set to P0
>   (Normal Operational State) to ensure the PHY is fully powered and ready
>   for link training.
> 
> These changes ensure that all lanes are consistently transitioned from
> reset into a known-good operational state, preventing undefined behavior
> and ensuring the PHY is ready for high-speed data transmission.

First describe the problem, then describe how you fix it.


Kind regards,
Niklas

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

  reply	other threads:[~2026-04-09  9:50 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-09  4:49 [PATCH v1] phy: rockchip-snps-pcie3:phy: Configure clkreq_n and PowerDown for all lanes Anand Moon
2026-04-09  4:49 ` Anand Moon
2026-04-09  4:49 ` Anand Moon
2026-04-09  9:49 ` Niklas Cassel [this message]
2026-04-09  9:49   ` Niklas Cassel
2026-04-09  9:49   ` Niklas Cassel
2026-04-09 13:30   ` Anand Moon
2026-04-09 13:30     ` Anand Moon
2026-04-09 13:30     ` Anand Moon
2026-04-10  0:46 ` Shawn Lin
2026-04-10  0:46   ` Shawn Lin
2026-04-10  0:46   ` Shawn Lin
2026-04-10  6:26   ` Anand Moon
2026-04-10  6:26     ` Anand Moon
2026-04-10  6:26     ` Anand Moon

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