[PATCH 00/16] Add PIN and SPI support for Spacemit K1

[PATCH 00/16] Add PIN and SPI support for Spacemit K1

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

Add pinctrl, GPIO, and SPI NOR flash support for the Spacemit K1 SoC
and enable U-Boot to boot on K1-based boards.

Notes:
Tested on the Muse Pi Pro.
BananaPi F3 is untestable due to missing SPI NOR flash.

Prerequisite:
-------------
This series depend on another pending-to-merge series [1].

[1] [PATCH v3 00/16] Add board support for Spacemit K1 SoC in SPL
https://lore.kernel.org/u-boot/20260325223232.1553212-1-raymondmaoca@gmail.com/

Raymond Mao (16):
  gpio: add gpio driver for Spacemit K1 SoC
  pinctrl: add pinctrl driver for Spacemit K1 SoC
  dts: k1: fix gpio ranges
  dts: k1: import pinctrl dts file from upstream folder
  dts: k1: remove embedded subnode in pin configs
  configs: k1: enable pinctrl and gpio
  mtd: spi: select SPL_SPI_FLASH_TINY in SPL stage
  mtd: spi: enable spi_nor_remove() in soft reset config
  spi: fsl: add support for Spacemit K1 SoC
  dts: k1: add QSPI controller support
  board: k1: enable SPI NOR flash in SPL
  riscv: binman: Always set default configuration in FIT image
  spacemit: k1: append RISCV_MMODE_TIMERBASE
  spacemit: k1: Add multiple device tree support
  spacemit: k1: Add support for mmc regulator initialization
  spacemit: k1: rename device tree prefix from "k1-" to "k1_"

 arch/riscv/dts/Makefile                   |   2 +-
 arch/riscv/dts/binman.dtsi                |   2 -
 arch/riscv/dts/k1-bananapi-f3.dts         |  28 --
 arch/riscv/dts/k1-pinctrl.dtsi            |  19 -
 arch/riscv/dts/k1.dtsi                    |  21 +-
 arch/riscv/dts/k1_bananapi-f3.dts         | 189 ++++++++
 arch/riscv/dts/k1_muse-pi-pro.dts         | 199 ++++++++
 arch/riscv/dts/k1_pinctrl.dtsi            |  79 ++++
 arch/riscv/dts/{k1-spl.dts => k1_spl.dts} |  62 ++-
 board/spacemit/k1/MAINTAINERS             |   2 +
 board/spacemit/k1/spl.c                   |  56 ++-
 configs/spacemit_k1_defconfig             |  37 +-
 drivers/gpio/Kconfig                      |   8 +
 drivers/gpio/Makefile                     |   1 +
 drivers/gpio/spacemit_gpio.c              | 217 +++++++++
 drivers/mtd/spi/Makefile                  |   5 +-
 drivers/mtd/spi/sf_probe.c                |   8 +-
 drivers/pinctrl/Kconfig                   |   1 +
 drivers/pinctrl/Makefile                  |   1 +
 drivers/pinctrl/spacemit/Kconfig          |   9 +
 drivers/pinctrl/spacemit/Makefile         |   2 +
 drivers/pinctrl/spacemit/pinctrl-k1.c     | 550 ++++++++++++++++++++++
 drivers/spi/fsl_qspi.c                    |   9 +
 include/configs/k1.h                      |  12 +-
 24 files changed, 1422 insertions(+), 97 deletions(-)
 delete mode 100644 arch/riscv/dts/k1-bananapi-f3.dts
 delete mode 100644 arch/riscv/dts/k1-pinctrl.dtsi
 create mode 100644 arch/riscv/dts/k1_bananapi-f3.dts
 create mode 100644 arch/riscv/dts/k1_muse-pi-pro.dts
 create mode 100644 arch/riscv/dts/k1_pinctrl.dtsi
 rename arch/riscv/dts/{k1-spl.dts => k1_spl.dts} (88%)
 create mode 100644 drivers/gpio/spacemit_gpio.c
 create mode 100644 drivers/pinctrl/spacemit/Kconfig
 create mode 100644 drivers/pinctrl/spacemit/Makefile
 create mode 100644 drivers/pinctrl/spacemit/pinctrl-k1.c

-- 
2.25.1

[PATCH 01/16] gpio: add gpio driver for Spacemit K1 SoC

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

Enable gpio driver for Spacemit K1 SoC.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 drivers/gpio/Kconfig         |   8 ++
 drivers/gpio/Makefile        |   1 +
 drivers/gpio/spacemit_gpio.c | 217 +++++++++++++++++++++++++++++++++++
 3 files changed, 226 insertions(+)
 create mode 100644 drivers/gpio/spacemit_gpio.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 1484dd3504c..b51886d41f3 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -449,6 +449,14 @@ config SANDBOX_GPIO_COUNT
 	  of 'anonymous' GPIOs that do not belong to any device or bank.
 	  Select a suitable value depending on your needs.
 
+config SPACEMIT_GPIO
+	bool "Spacemit K1 GPIO driver"
+	depends on DM_GPIO && TARGET_SPACEMIT_K1
+	help
+	  Support the GPIO device in Spacemit SoCs. The GPIOs are arranged
+	  into a number of banks (different for each SoC type) each with 32
+	  GPIOs.
+
 config SUNXI_GPIO
 	bool "Allwinner GPIO driver"
 	depends on ARCH_SUNXI
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fec258f59f5..7760aa8e11a 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_MVEBU_GPIO)	+= mvebu_gpio.o
 obj-$(CONFIG_MSM_GPIO)		+= msm_gpio.o
 obj-$(CONFIG_$(PHASE_)PCF8575_GPIO)	+= pcf8575_gpio.o
 obj-$(CONFIG_$(PHASE_)QCOM_PMIC_GPIO)	+= qcom_pmic_gpio.o qcom_spmi_gpio.o
+obj-$(CONFIG_$(PHASE_)SPACEMIT_GPIO)	+= spacemit_gpio.o
 obj-$(CONFIG_MT7620_GPIO)	+= mt7620_gpio.o
 obj-$(CONFIG_MT7621_GPIO)	+= mt7621_gpio.o
 obj-$(CONFIG_MSCC_SGPIO)	+= mscc_sgpio.o
diff --git a/drivers/gpio/spacemit_gpio.c b/drivers/gpio/spacemit_gpio.c
new file mode 100644
index 00000000000..02a13bd8bce
--- /dev/null
+++ b/drivers/gpio/spacemit_gpio.c
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025-2026 RISCstar Ltd.
+ */
+
+#include <asm/gpio.h>
+#include <clk.h>
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <dm/pinctrl.h>
+#include <dm/read.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <log.h>
+
+#define GPIO_BANK_SIZE		32
+#define GPIO_TO_BANK(pin)	((pin) / GPIO_BANK_SIZE)
+#define GPIO_TO_BIT(pin)	((pin) % GPIO_BANK_SIZE)
+
+static inline int gpio_to_reg_offset(unsigned int pin)
+{
+	unsigned int bank = GPIO_TO_BANK(pin);
+
+	if (bank == 0)
+		return 0;
+	else if (bank == 1)
+		return 4;
+	else if (bank == 2)
+		return 8;
+	else if (bank == 3)
+		return 0x100;
+	log_warning("Use default GPIO bank for an invalid GPIO[%d].\n", pin);
+	return 0;
+}
+
+#define REG_PLR(pin)		(0x00 + gpio_to_reg_offset(pin))
+#define REG_PDR(pin)		(0x0c + gpio_to_reg_offset(pin))
+#define REG_PSR(pin)		(0x18 + gpio_to_reg_offset(pin))
+#define REG_PCR(pin)		(0x24 + gpio_to_reg_offset(pin))
+#define REG_SDR(pin)		(0x54 + gpio_to_reg_offset(pin))
+#define REG_CDR(pin)		(0x60 + gpio_to_reg_offset(pin))
+
+struct spacemit_gpio_data {
+	u16	gpio_base;
+	u16	gpio_count;
+	u8	num_banks;
+};
+
+struct spacemit_gpio_priv {
+	void __iomem *regs;
+};
+
+static int spacemit_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+			       struct ofnode_phandle_args *args)
+{
+	struct spacemit_gpio_data *data;
+	u32 bank, offset, flags;
+
+	data = (struct spacemit_gpio_data *)dev_get_driver_data(dev);
+	if (args->args_count < 3) {
+		dev_err(dev, "Invalid args count: %d, expected 3\n",
+			args->args_count);
+		return -EINVAL;
+	}
+	bank = args->args[0];
+	offset = args->args[1];
+	flags = args->args[2];
+
+	if (bank >= data->num_banks) {
+		dev_err(dev, "Invalid gpio bank: %u (max %u)\n",
+			bank, data->num_banks - 1);
+		return -EINVAL;
+	}
+	if (offset >= GPIO_BANK_SIZE) {
+		dev_err(dev, "Invalid offset: %u (max 31)\n", offset);
+		return -EINVAL;
+	}
+	desc->offset = bank * GPIO_BANK_SIZE + offset;
+	desc->flags = flags;
+	return 0;
+}
+
+static int spacemit_gpio_get_value(struct udevice *dev, unsigned int offset)
+{
+	struct spacemit_gpio_priv *priv = dev_get_priv(dev);
+	void __iomem *addr;
+	u32 value, mask;
+
+	addr = priv->regs + REG_PLR(offset);
+	value = readl(addr);
+	mask = 1 << GPIO_TO_BIT(offset);
+	return !!(value & mask);
+}
+
+static int spacemit_gpio_get_function(struct udevice *dev, unsigned int offset)
+{
+	struct spacemit_gpio_priv *priv = dev_get_priv(dev);
+	void __iomem *addr;
+	u32 value, mask;
+
+	addr = priv->regs + REG_PDR(offset);
+	value = readl(addr);
+	mask = 1 << GPIO_TO_BIT(offset);
+	if (value & mask)
+		return GPIOF_OUTPUT;
+	return GPIOF_INPUT;
+}
+
+static int spacemit_gpio_get_flags(struct udevice *dev, unsigned int offset,
+				   ulong *flagsp)
+{
+	ulong flags = 0;
+	u32 dir;
+
+	dir = spacemit_gpio_get_function(dev, offset);
+	if (dir) {
+		flags |= GPIOD_IS_OUT;
+		if (spacemit_gpio_get_value(dev, offset))
+			flags |= GPIOD_IS_OUT_ACTIVE;
+	} else {
+		flags |= GPIOD_IS_IN;
+	}
+	*flagsp = flags;
+	return 0;
+}
+
+static int spacemit_gpio_set_flags(struct udevice *dev, unsigned int offset,
+				   ulong flags)
+{
+	struct spacemit_gpio_priv *priv = dev_get_priv(dev);
+	void __iomem *addr;
+	int value;
+
+	value = (flags & GPIOD_IS_OUT_ACTIVE) ? 1 : 0;
+	if (flags & GPIOD_IS_IN) {
+		addr = priv->regs + REG_CDR(offset);
+		writel(1 << GPIO_TO_BIT(offset), addr);
+	}
+	if (flags & GPIOD_IS_OUT) {
+		if (value) {
+			addr = priv->regs + REG_PSR(offset);
+			writel(1 << GPIO_TO_BIT(offset), addr);
+		} else {
+			addr = priv->regs + REG_PCR(offset);
+			writel(1 << GPIO_TO_BIT(offset), addr);
+		}
+		addr = priv->regs + REG_SDR(offset);
+		writel(1 << GPIO_TO_BIT(offset), addr);
+	}
+	return 0;
+}
+
+static const struct dm_gpio_ops spacemit_gpio_ops = {
+	.request	= pinctrl_gpio_request,
+	.rfree		= pinctrl_gpio_free,
+	.xlate		= spacemit_gpio_xlate,
+	.get_value	= spacemit_gpio_get_value,
+	.get_function	= spacemit_gpio_get_function,
+	.get_flags	= spacemit_gpio_get_flags,
+	.set_flags	= spacemit_gpio_set_flags,
+};
+
+static int spacemit_gpio_probe(struct udevice *dev)
+{
+	struct spacemit_gpio_priv *priv;
+	struct spacemit_gpio_data *data;
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct clk_bulk clks;
+	int ret;
+
+	data = (struct spacemit_gpio_data *)dev_get_driver_data(dev);
+	priv = dev_get_priv(dev);
+	priv->regs = dev_read_addr_ptr(dev);
+	if (!priv->regs) {
+		dev_err(dev, "Fail to get base address\n");
+		return -EINVAL;
+	}
+	uc_priv->bank_name = "GPIO";
+	uc_priv->gpio_count = data->gpio_count;
+	uc_priv->gpio_base = data->gpio_base;
+
+	ret = clk_get_bulk(dev, &clks);
+	if (ret) {
+		dev_err(dev, "Fail to get bulk clks\n");
+		return ret;
+	}
+	ret = clk_enable_bulk(&clks);
+	if (ret) {
+		dev_err(dev, "Fail to enable bulk clks\n");
+		goto out;
+	}
+	return 0;
+out:
+	clk_release_bulk(&clks);
+	return ret;
+}
+
+static const struct spacemit_gpio_data k1_gpio_data = {
+	.num_banks	= 4,
+	.gpio_count	= 128,
+	.gpio_base	= 0,
+};
+
+static const struct udevice_id spacemit_gpio_ids[] = {
+	{ .compatible = "spacemit,k1-gpio", .data = (uintptr_t)&k1_gpio_data, },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(k1_gpio) = {
+	.name		= "spacemit_k1_gpio",
+	.id		= UCLASS_GPIO,
+	.of_match	= spacemit_gpio_ids,
+	.ops		= &spacemit_gpio_ops,
+	.priv_auto	= sizeof(struct spacemit_gpio_priv),
+	.probe		= spacemit_gpio_probe,
+};
-- 
2.25.1

[PATCH 02/16] pinctrl: add pinctrl driver for Spacemit K1 SoC

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

Add pinctrl driver for Spacemit K1 SoC.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 drivers/pinctrl/Kconfig               |   1 +
 drivers/pinctrl/Makefile              |   1 +
 drivers/pinctrl/spacemit/Kconfig      |   9 +
 drivers/pinctrl/spacemit/Makefile     |   2 +
 drivers/pinctrl/spacemit/pinctrl-k1.c | 550 ++++++++++++++++++++++++++
 5 files changed, 563 insertions(+)
 create mode 100644 drivers/pinctrl/spacemit/Kconfig
 create mode 100644 drivers/pinctrl/spacemit/Makefile
 create mode 100644 drivers/pinctrl/spacemit/pinctrl-k1.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 578edbf8168..a3abe0ea04d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -419,6 +419,7 @@ source "drivers/pinctrl/nxp/Kconfig"
 source "drivers/pinctrl/qcom/Kconfig"
 source "drivers/pinctrl/renesas/Kconfig"
 source "drivers/pinctrl/rockchip/Kconfig"
+source "drivers/pinctrl/spacemit/Kconfig"
 source "drivers/pinctrl/sunxi/Kconfig"
 source "drivers/pinctrl/tegra/Kconfig"
 source "drivers/pinctrl/uniphier/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 29fb9b484d0..ece7a57767c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_PINCTRL_SCMI)	+= pinctrl-scmi.o
 obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o
 obj-$(CONFIG_PINCTRL_STI)	+= pinctrl-sti.o
 obj-$(CONFIG_PINCTRL_STM32)	+= pinctrl_stm32.o
+obj-$(CONFIG_$(PHASE_)PINCTRL_SPACEMIT_K1) += spacemit/
 obj-$(CONFIG_$(PHASE_)PINCTRL_SX150X) += pinctrl-sx150x.o
 obj-$(CONFIG_$(PHASE_)PINCTRL_STMFX)	+= pinctrl-stmfx.o
 obj-$(CONFIG_PINCTRL_TH1520)	+= pinctrl-th1520.o
diff --git a/drivers/pinctrl/spacemit/Kconfig b/drivers/pinctrl/spacemit/Kconfig
new file mode 100644
index 00000000000..6aab89e160c
--- /dev/null
+++ b/drivers/pinctrl/spacemit/Kconfig
@@ -0,0 +1,9 @@
+config PINCTRL_SPACEMIT_K1
+	bool "Spacemit K1 SoC pinctrl driver"
+	depends on PINCTRL_GENERIC && DM
+	help
+	  Supports pin multiplexing control on Spacemit K1 SoCs.
+
+	  The driver is controlled by a device tree node which contains both
+	  the GPIO definitions and pin control functions for each available
+	  multiplex function.
diff --git a/drivers/pinctrl/spacemit/Makefile b/drivers/pinctrl/spacemit/Makefile
new file mode 100644
index 00000000000..0dc43c72cb1
--- /dev/null
+++ b/drivers/pinctrl/spacemit/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-y += pinctrl-k1.o
diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c
new file mode 100644
index 00000000000..a6a22eacac7
--- /dev/null
+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c
@@ -0,0 +1,550 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 Yixun Lan <dlan@gentoo.org>
+ * Copyright (c) 2025-2026 RISCstar Ltd.
+ */
+
+#include <clk.h>
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <dm/pinctrl.h>
+#include <dm/read.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+/*
+ * +---------+----------+-----------+--------+--------+----------+--------+
+ * |   pull  |   drive  | schmitter |  slew  |  edge  |  strong  |   mux  |
+ * | up/down | strength |  trigger  |  rate  | detect |   pull   |  mode  |
+ * +---------+----------+-----------+--------+--------+----------+--------+
+ *   3 bits     3 bits     2 bits     1 bit    3 bits     1 bit    3 bits
+ */
+
+#define PAD_MUX			GENMASK(2, 0)
+#define PAD_STRONG_PULL		BIT(3)
+#define PAD_EDGE_RISE		BIT(4)
+#define PAD_EDGE_FALL		BIT(5)
+#define PAD_EDGE_CLEAR		BIT(6)
+#define PAD_SLEW_RATE		GENMASK(12, 11)
+#define PAD_SLEW_RATE_EN	BIT(7)
+#define PAD_SCHMITT		GENMASK(9, 8)
+#define PAD_DRIVE		GENMASK(12, 10)
+#define PAD_PULLDOWN		BIT(13)
+#define PAD_PULLUP		BIT(14)
+#define PAD_PULL_EN		BIT(15)
+
+#define PIN_POWER_STATE_1V8		1800
+#define PIN_POWER_STATE_3V3		3300
+
+enum spacemit_pin_io_type {
+	IO_TYPE_NONE = 0,
+	IO_TYPE_1V8,
+	IO_TYPE_3V3,
+	IO_TYPE_EXTERNAL,
+};
+
+struct spacemit_pin_io {
+	unsigned int	pin : 12;	// 0~4095
+	unsigned int	io_type : 4;	// 0~15
+	unsigned int	ds : 8;		// 0~255
+	unsigned int	reserved : 8;
+};
+
+struct spacemit_pinctrl_data {
+	struct spacemit_pin_io *io_pins;
+	int nr_io_pins;
+
+	void __iomem * (*pin_to_reg)(struct udevice *dev, unsigned int pin);
+	int (*get_gpio_mux)(struct udevice *dev, unsigned int pin);
+	int (*get_pins)(struct udevice *dev);
+	int (*get_functions)(struct udevice *dev);
+	int (*get_io_type)(struct udevice *dev, unsigned int pin);
+};
+
+struct spacemit_pinctrl_priv {
+	void __iomem		*regs;
+	struct spacemit_pin_io	*io_pins;
+	int			nr_io_pins;
+};
+
+struct spacemit_pin_mux_config {
+	const struct spacemit_pin	*pin;
+	u32				config;
+};
+
+struct spacemit_pin_drv_strength {
+	unsigned int	val : 8;
+	unsigned int	ma : 16;
+	unsigned int	reserved : 8;
+};
+
+static char pin_name[PINNAME_SIZE];
+
+/* External: IO voltage via external source, can be 1.8V or 3.3V */
+static struct spacemit_pin_io k1_io_pins[] = {
+	{ 47, IO_TYPE_EXTERNAL, 0, },
+	{ 48, IO_TYPE_EXTERNAL, 0, },
+	{ 49, IO_TYPE_EXTERNAL, 0, },
+	{ 50, IO_TYPE_EXTERNAL, 0, },
+	{ 51, IO_TYPE_EXTERNAL, 0, },
+	{ 52, IO_TYPE_EXTERNAL, 0, },
+	{ 75, IO_TYPE_EXTERNAL, 0, },
+	{ 76, IO_TYPE_EXTERNAL, 0, },
+	{ 77, IO_TYPE_EXTERNAL, 0, },
+	{ 78, IO_TYPE_EXTERNAL, 0, },
+	{ 79, IO_TYPE_EXTERNAL, 0, },
+	{ 80, IO_TYPE_EXTERNAL, 0, },
+	{ 98, IO_TYPE_EXTERNAL, 0, },
+	{ 99, IO_TYPE_EXTERNAL, 0, },
+	{ 100, IO_TYPE_EXTERNAL, 0, },
+	{ 101, IO_TYPE_EXTERNAL, 0, },
+	{ 102, IO_TYPE_EXTERNAL, 0, },
+	{ 103, IO_TYPE_EXTERNAL, 0, },
+	{ 104, IO_TYPE_EXTERNAL, 0, },
+	{ 105, IO_TYPE_EXTERNAL, 0, },
+	{ 106, IO_TYPE_EXTERNAL, 0, },
+	{ 107, IO_TYPE_EXTERNAL, 0, },
+	{ 108, IO_TYPE_EXTERNAL, 0, },
+	{ 109, IO_TYPE_EXTERNAL, 0, },
+};
+
+static inline int k1_get_pins(struct udevice *dev)
+{
+	return 128;
+}
+
+static inline int k1_get_functions(struct udevice *dev)
+{
+	return 7;
+}
+
+// The pin number equals to the gpio number.
+static void __iomem *k1_pin_to_reg(struct udevice *dev, unsigned int pin)
+{
+	struct spacemit_pinctrl_priv *priv = dev_get_priv(dev);
+	unsigned int offset = 1;
+
+	if (pin < 86) {
+		offset += pin;
+	} else if (pin < 93) {
+		offset += pin + 36;
+	} else if (pin < 98) {
+		offset += pin + 23;
+	} else if (pin == 98) {		// QSPI_DAT3
+		offset += 92;
+	} else if (pin == 99) {		// QSPI_DAT2
+		offset += 91;
+	} else if (pin == 100) {	// QSPI_DAT1
+		offset += 90;
+	} else if (pin == 101) {	// QSPI_DAT0
+		offset += 89;
+	} else if (pin == 102) {	// QSPI_CLK
+		offset += 94;
+	} else if (pin == 103) {	// QSPI_CS1
+		offset += 93;
+	} else if (pin < 111) {
+		offset += pin + 5;
+	} else if (pin < 128) {
+		offset += pin + 19;
+	} else {
+		dev_err(dev, "Invalid pin (%u)\n", pin);
+		return NULL;
+	}
+	return priv->regs + (offset << 2);
+}
+
+static int k1_get_gpio_mux(struct udevice *dev, unsigned int selector)
+{
+	u32 mux = 0;
+
+	if (selector < 70) {
+		mux = 0;
+	} else if (selector < 74) {
+		mux = 1;
+	} else if (selector < 93) {
+		mux = 0;
+	} else if (selector < 104) {
+		mux = 1;
+	} else if (selector < 110) {
+		mux = 4;
+	} else if (selector < 128) {
+		mux = 0;
+	} else {
+		dev_err(dev, "Invalid pin (%u)\n", selector);
+		return -EINVAL;
+	}
+	return mux;
+}
+
+static int k1_get_io_type(struct udevice *dev, unsigned int selector)
+{
+	if (selector < 47)
+		return IO_TYPE_1V8;
+	else if (selector < 53)
+		return IO_TYPE_EXTERNAL;
+	else if (selector < 75)
+		return IO_TYPE_1V8;
+	else if (selector < 81)
+		return IO_TYPE_EXTERNAL;
+	else if (selector < 98)
+		return IO_TYPE_1V8;
+	else if (selector < 110)
+		return IO_TYPE_EXTERNAL;
+	else if (selector < 128)
+		return IO_TYPE_1V8;
+	return -EINVAL;
+}
+
+/* use IO high level output current as the table */
+static struct spacemit_pin_drv_strength spacemit_ds_1v8_tbl[4] = {
+	{ 0, 11 },
+	{ 2, 21 },
+	{ 4, 32 },
+	{ 6, 42 },
+};
+
+static struct spacemit_pin_drv_strength spacemit_ds_3v3_tbl[8] = {
+	{ 0,  7 },
+	{ 2, 10 },
+	{ 4, 13 },
+	{ 6, 16 },
+	{ 1, 19 },
+	{ 3, 23 },
+	{ 5, 26 },
+	{ 7, 29 },
+};
+
+static inline u8 spacemit_get_ds_value(struct spacemit_pin_drv_strength *tbl,
+				       u32 num, u32 ma)
+{
+	int i;
+
+	for (i = 0; i < num; i++)
+		if (ma <= tbl[i].ma)
+			return tbl[i].val;
+
+	return tbl[num - 1].val;
+}
+
+static inline u32 spacemit_get_ds_ma(struct spacemit_pin_drv_strength *tbl,
+				     u32 num, u32 val)
+{
+	int i;
+
+	for (i = 0; i < num; i++)
+		if (val == tbl[i].val)
+			return tbl[i].ma;
+
+	return 0;
+}
+
+static inline u8 spacemit_get_drive_strength(enum spacemit_pin_io_type type,
+					     u32 ma)
+{
+	switch (type) {
+	case IO_TYPE_1V8:
+		return spacemit_get_ds_value(spacemit_ds_1v8_tbl,
+					     ARRAY_SIZE(spacemit_ds_1v8_tbl),
+					     ma);
+	case IO_TYPE_3V3:
+		return spacemit_get_ds_value(spacemit_ds_3v3_tbl,
+					     ARRAY_SIZE(spacemit_ds_3v3_tbl),
+					     ma);
+	default:
+		return 0;
+	}
+}
+
+static inline u32 spacemit_get_drive_strength_ma(enum spacemit_pin_io_type type,
+						 u32 value)
+{
+	switch (type) {
+	case IO_TYPE_1V8:
+		return spacemit_get_ds_ma(spacemit_ds_1v8_tbl,
+					  ARRAY_SIZE(spacemit_ds_1v8_tbl),
+					  value & 0x6);
+	case IO_TYPE_3V3:
+		return spacemit_get_ds_ma(spacemit_ds_3v3_tbl,
+					  ARRAY_SIZE(spacemit_ds_3v3_tbl),
+					  value);
+	default:
+		return 0;
+	}
+}
+
+static inline u16 spacemit_dt_get_pin(u32 value)
+{
+	return value >> 16;
+}
+
+static inline u16 spacemit_dt_get_pin_mux(u32 value)
+{
+	return value & GENMASK(15, 0);
+}
+
+static int spacemit_get_pins_count(struct udevice *dev)
+{
+	struct spacemit_pinctrl_data *data;
+
+	data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+	if (!data || !data->get_pins)
+		return -EINVAL;
+	return data->get_pins(dev);
+}
+
+static const char *spacemit_get_pin_name(struct udevice *dev,
+					 unsigned int selector)
+{
+	struct spacemit_pinctrl_data *data;
+	unsigned int npins;
+
+	data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+	if (!data || !data->get_pins)
+		return NULL;
+	npins = data->get_pins(dev);
+
+	if (selector >= npins)
+		snprintf(pin_name, PINNAME_SIZE, "Error");
+	else
+		snprintf(pin_name, PINNAME_SIZE, "PIN%u", selector);
+
+	return pin_name;
+}
+
+static int spacemit_get_functions_count(struct udevice *dev)
+{
+	struct spacemit_pinctrl_data *data;
+
+	data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+	if (!data || !data->get_functions)
+		return -EINVAL;
+	return data->get_functions(dev);
+}
+
+static int spacemit_get_pin_muxing(struct udevice *dev, unsigned int pin,
+				   char *buf, int size)
+{
+	struct spacemit_pinctrl_data *data;
+	void __iomem *addr;
+	u32 mux, val;
+
+	data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+	if (!data || !data->pin_to_reg)
+		return -EINVAL;
+
+	addr = data->pin_to_reg(dev, pin);
+	if (!addr)
+		return -EINVAL;
+
+	val = readl(addr);
+	mux = val & PAD_MUX;
+	snprintf(buf, size, "[%p] 0x%08x MUX%d", addr, val, mux);
+	return 0;
+}
+
+static int spacemit_pinctrl_request_gpio(struct udevice *dev,
+					 unsigned int selector)
+{
+	struct spacemit_pinctrl_data *data;
+	void __iomem *addr;
+	int mux;
+
+	data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+	if (!data || !data->pin_to_reg || !data->get_gpio_mux)
+		return -EINVAL;
+	addr = data->pin_to_reg(dev, selector);
+	mux = data->get_gpio_mux(dev, selector);
+	if (mux < 0) {
+		dev_err(dev, "Invalid pin (%d)\n", selector);
+		return -EINVAL;
+	}
+	clrsetbits_le32(addr, PAD_MUX, mux & PAD_MUX);
+	return 0;
+}
+
+static int spacemit_pinctrl_free_gpio(struct udevice *dev,
+				      unsigned int selector)
+{
+	return 0;
+}
+
+static int spacemit_pinmux_set(struct udevice *dev, unsigned int pin,
+			       unsigned int mux)
+{
+	struct spacemit_pinctrl_data *data;
+	void __iomem *addr;
+
+	data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+	if (!data || !data->pin_to_reg)
+		return -EINVAL;
+	addr = data->pin_to_reg(dev, pin);
+	clrsetbits_le32(addr, PAD_MUX, mux & PAD_MUX);
+	return 0;
+}
+
+static int spacemit_pinmux_property_set(struct udevice *dev, u32 pinmux_group)
+{
+	u32 pin, mux;
+
+	pin = spacemit_dt_get_pin(pinmux_group);
+	mux = spacemit_dt_get_pin_mux(pinmux_group);
+	return spacemit_pinmux_set(dev, pin, mux);
+}
+
+static const struct pinconf_param spacemit_pinconf_params[] = {
+	{ "bias-disable",	PIN_CONFIG_BIAS_DISABLE,	0 },
+	{ "bias-pull-down",	PIN_CONFIG_BIAS_PULL_DOWN,	1 },
+	{ "bias-pull-up",	PIN_CONFIG_BIAS_PULL_UP,	1 },
+	{ "drive-strength",	PIN_CONFIG_DRIVE_STRENGTH,	U32_MAX },
+	{ "power-source",	PIN_CONFIG_POWER_SOURCE,	U32_MAX },
+};
+
+static int spacemit_pinconf_set(struct udevice *dev, unsigned int pin_selector,
+				unsigned int param, unsigned int argument)
+{
+	struct spacemit_pinctrl_data *data;
+	struct spacemit_pinctrl_priv *priv = dev_get_priv(dev);
+	void __iomem *addr;
+	u32 mask = 0;
+	unsigned int io_type;
+	u8 ds;
+	bool found;
+	int i;
+
+	data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+	if (!data || !data->pin_to_reg)
+		return -EINVAL;
+	addr = data->pin_to_reg(dev, pin_selector);
+	switch (param) {
+	case PIN_CONFIG_BIAS_DISABLE:
+		clrbits_le32(addr, PAD_PULLUP | PAD_PULLDOWN | PAD_PULL_EN);
+		break;
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+		mask = PAD_PULLDOWN | PAD_PULLUP | PAD_PULL_EN;
+		clrsetbits_le32(addr, mask, PAD_PULLDOWN | PAD_PULL_EN);
+		break;
+	case PIN_CONFIG_BIAS_PULL_UP:
+		mask = PAD_PULLDOWN | PAD_PULLUP | PAD_PULL_EN;
+		clrsetbits_le32(addr, mask, PAD_PULLUP | PAD_PULL_EN);
+		break;
+	case PIN_CONFIG_DRIVE_STRENGTH:
+		io_type = IO_TYPE_1V8;
+		for (i = 0; i < priv->nr_io_pins; i++) {
+			if (priv->io_pins[i].pin != pin_selector)
+				continue;
+			io_type = priv->io_pins[i].io_type;
+			break;
+		}
+		if (io_type != IO_TYPE_3V3 && io_type != IO_TYPE_1V8) {
+			dev_err(dev, "Invalid IO type (%d)\n", io_type);
+			return -EINVAL;
+		}
+		ds = spacemit_get_drive_strength(io_type, argument);
+		clrsetbits_le32(addr, PAD_DRIVE, ds);
+		break;
+	case PIN_CONFIG_POWER_SOURCE:
+		for (i = 0, found = false; i < priv->nr_io_pins; i++) {
+			if (priv->io_pins[i].pin != pin_selector)
+				continue;
+			if (argument == PIN_POWER_STATE_3V3) {
+				priv->io_pins[i].io_type = IO_TYPE_3V3;
+				found = true;
+			} else if (argument == PIN_POWER_STATE_1V8) {
+				priv->io_pins[i].io_type = IO_TYPE_1V8;
+				found = true;
+			}
+			break;
+		}
+		if (!found && argument != PIN_POWER_STATE_1V8) {
+			dev_err(dev, "Invalid power source (%d)\n", argument);
+			return -EINVAL;
+		}
+		break;
+	default:
+		return -EOPNOTSUPP;
+	}
+	return 0;
+}
+
+static int spacemit_pinctrl_probe(struct udevice *dev)
+{
+	struct spacemit_pinctrl_data *data;
+	struct spacemit_pinctrl_priv *priv;
+	struct clk_bulk clks;
+	size_t size;
+	int ret;
+
+	data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+	priv = dev_get_priv(dev);
+	priv->regs = dev_read_addr_ptr(dev);
+	if (!priv->regs) {
+		dev_err(dev, "Fail to get base address\n");
+		return -EINVAL;
+	}
+	priv->nr_io_pins = data->nr_io_pins;
+	size = priv->nr_io_pins * sizeof(struct spacemit_pin_io);
+	priv->io_pins = (struct spacemit_pin_io *)memdup(data->io_pins, size);
+	if (!priv->io_pins) {
+		dev_err(dev, "Fail to allocate memory\n");
+		return -ENOMEM;
+	}
+
+	ret = clk_get_bulk(dev, &clks);
+	if (ret) {
+		dev_err(dev, "Fail to get bulk clks\n");
+		goto out_get_clk;
+	}
+	ret = clk_enable_bulk(&clks);
+	if (ret) {
+		dev_err(dev, "Fail to enable bulk clks\n");
+		goto out_clks;
+	}
+	return 0;
+out_clks:
+	clk_release_bulk(&clks);
+out_get_clk:
+	free(priv->io_pins);
+	return ret;
+}
+
+static const struct spacemit_pinctrl_data k1_pinctrl_data = {
+	.io_pins	= k1_io_pins,
+	.nr_io_pins	= ARRAY_SIZE(k1_io_pins),
+	.pin_to_reg	= k1_pin_to_reg,
+	.get_gpio_mux	= k1_get_gpio_mux,
+	.get_pins	= k1_get_pins,
+	.get_functions	= k1_get_functions,
+	.get_io_type	= k1_get_io_type,
+};
+
+static const struct udevice_id spacemit_pinctrl_ids[] = {
+	{
+		.compatible = "spacemit,k1-pinctrl",
+		.data = (uintptr_t)&k1_pinctrl_data,
+	}, { /* sentinel */ }
+};
+
+static const struct pinctrl_ops spacemit_pinctrl_ops = {
+	.get_pins_count		= spacemit_get_pins_count,
+	.get_pin_name		= spacemit_get_pin_name,
+	.get_functions_count	= spacemit_get_functions_count,
+	.get_pin_muxing		= spacemit_get_pin_muxing,
+	.set_state		= pinctrl_generic_set_state,
+	.gpio_request_enable	= spacemit_pinctrl_request_gpio,
+	.gpio_disable_free	= spacemit_pinctrl_free_gpio,
+	.pinmux_set		= spacemit_pinmux_set,
+	.pinmux_property_set	= spacemit_pinmux_property_set,
+	.pinconf_num_params	= ARRAY_SIZE(spacemit_pinconf_params),
+	.pinconf_params		= spacemit_pinconf_params,
+	.pinconf_set		= spacemit_pinconf_set,
+};
+
+U_BOOT_DRIVER(spacemit_pinctrl) = {
+	.name		= "spacemit_pinctrl",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= spacemit_pinctrl_ids,
+	.ops		= &spacemit_pinctrl_ops,
+	.priv_auto	= sizeof(struct spacemit_pinctrl_priv),
+	.probe		= spacemit_pinctrl_probe,
+};
-- 
2.25.1

[PATCH 03/16] dts: k1: fix gpio ranges

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

The numbers of cells in gpio-ranges should only be 3.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 arch/riscv/dts/k1.dtsi | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi
index 682d2fb88e2..fc3a693a10e 100644
--- a/arch/riscv/dts/k1.dtsi
+++ b/arch/riscv/dts/k1.dtsi
@@ -383,10 +383,7 @@
 			interrupt-parent = <&plic>;
 			interrupt-controller;
 			#interrupt-cells = <3>;
-			gpio-ranges = <&pinctrl 0 0 0 32>,
-				      <&pinctrl 1 0 32 32>,
-				      <&pinctrl 2 0 64 32>,
-				      <&pinctrl 3 0 96 32>;
+			gpio-ranges = <&pinctrl 0 0 128>;
 		};
 
 		pwm0: pwm@d401a000 {
-- 
2.25.1

[PATCH 04/16] dts: k1: import pinctrl dts file from upstream folder

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

Import k1-pinctrl.dtsi from upstream folder.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 arch/riscv/dts/k1-pinctrl.dtsi | 66 ++++++++++++++++++++++++++++++++--
 1 file changed, 63 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/dts/k1-pinctrl.dtsi b/arch/riscv/dts/k1-pinctrl.dtsi
index 14e7096fbcf..aff19c86d5f 100644
--- a/arch/riscv/dts/k1-pinctrl.dtsi
+++ b/arch/riscv/dts/k1-pinctrl.dtsi
@@ -1,12 +1,64 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0 OR MIT
 /*
- * Copyright (C) 2022 Spacemit Inc.
- * Copyright (C) 2025 Yixun Lan <dlan@gentoo.org>
+ * Copyright (c) 2024 Yixun Lan <dlan@gentoo.org>
  */
 
+#include <dt-bindings/gpio/gpio.h>
+
 #define K1_PADCONF(pin, func) (((pin) << 16) | (func))
 
+/* Map GPIO pin to each bank's <index, offset> */
+#define K1_GPIO(x)	(x / 32) (x % 32)
+
 &pinctrl {
+	gmac0_cfg: gmac0-cfg {
+		gmac0-pins {
+			pinmux = <K1_PADCONF(0, 1)>,	/* gmac0_rxdv */
+				 <K1_PADCONF(1, 1)>,	/* gmac0_rx_d0 */
+				 <K1_PADCONF(2, 1)>,	/* gmac0_rx_d1 */
+				 <K1_PADCONF(3, 1)>,	/* gmac0_rx_clk */
+				 <K1_PADCONF(4, 1)>,	/* gmac0_rx_d2 */
+				 <K1_PADCONF(5, 1)>,	/* gmac0_rx_d3 */
+				 <K1_PADCONF(6, 1)>,	/* gmac0_tx_d0 */
+				 <K1_PADCONF(7, 1)>,	/* gmac0_tx_d1 */
+				 <K1_PADCONF(8, 1)>,	/* gmac0_tx */
+				 <K1_PADCONF(9, 1)>,	/* gmac0_tx_d2 */
+				 <K1_PADCONF(10, 1)>,	/* gmac0_tx_d3 */
+				 <K1_PADCONF(11, 1)>,	/* gmac0_tx_en */
+				 <K1_PADCONF(12, 1)>,	/* gmac0_mdc */
+				 <K1_PADCONF(13, 1)>,	/* gmac0_mdio */
+				 <K1_PADCONF(14, 1)>,	/* gmac0_int_n */
+				 <K1_PADCONF(45, 1)>;	/* gmac0_clk_ref */
+
+			bias-pull-up = <0>;
+			drive-strength = <21>;
+		};
+	};
+
+	gmac1_cfg: gmac1-cfg {
+		gmac1-pins {
+			pinmux = <K1_PADCONF(29, 1)>,	/* gmac1_rxdv */
+				 <K1_PADCONF(30, 1)>,	/* gmac1_rx_d0 */
+				 <K1_PADCONF(31, 1)>,	/* gmac1_rx_d1 */
+				 <K1_PADCONF(32, 1)>,	/* gmac1_rx_clk */
+				 <K1_PADCONF(33, 1)>,	/* gmac1_rx_d2 */
+				 <K1_PADCONF(34, 1)>,	/* gmac1_rx_d3 */
+				 <K1_PADCONF(35, 1)>,	/* gmac1_tx_d0 */
+				 <K1_PADCONF(36, 1)>,	/* gmac1_tx_d1 */
+				 <K1_PADCONF(37, 1)>,	/* gmac1_tx */
+				 <K1_PADCONF(38, 1)>,	/* gmac1_tx_d2 */
+				 <K1_PADCONF(39, 1)>,	/* gmac1_tx_d3 */
+				 <K1_PADCONF(40, 1)>,	/* gmac1_tx_en */
+				 <K1_PADCONF(41, 1)>,	/* gmac1_mdc */
+				 <K1_PADCONF(42, 1)>,	/* gmac1_mdio */
+				 <K1_PADCONF(43, 1)>,	/* gmac1_int_n */
+				 <K1_PADCONF(46, 1)>;	/* gmac1_clk_ref */
+
+			bias-pull-up = <0>;
+			drive-strength = <21>;
+		};
+	};
+
 	uart0_2_cfg: uart0-2-cfg {
 		uart0-2-pins {
 			pinmux = <K1_PADCONF(68, 2)>,
@@ -16,4 +68,12 @@
 			drive-strength = <32>;
 		};
 	};
+
+	pwm14_1_cfg: pwm14-1-cfg {
+		pwm14-1-pins {
+			pinmux = <K1_PADCONF(44, 4)>;
+			bias-pull-up = <0>;
+			drive-strength = <32>;
+		};
+	};
 };
-- 
2.25.1

[PATCH 05/16] dts: k1: remove embedded subnode in pin configs

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

Fix the embedded subnode that is defined in pin configs.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 arch/riscv/dts/k1-pinctrl.dtsi | 102 ++++++++++++++++-----------------
 1 file changed, 51 insertions(+), 51 deletions(-)

diff --git a/arch/riscv/dts/k1-pinctrl.dtsi b/arch/riscv/dts/k1-pinctrl.dtsi
index aff19c86d5f..2e4216f94d0 100644
--- a/arch/riscv/dts/k1-pinctrl.dtsi
+++ b/arch/riscv/dts/k1-pinctrl.dtsi
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0 OR MIT
 /*
  * Copyright (c) 2024 Yixun Lan <dlan@gentoo.org>
+ * Copyright (c) 2025-2026 RISCstar Ltd.
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -12,68 +13,67 @@
 
 &pinctrl {
 	gmac0_cfg: gmac0-cfg {
-		gmac0-pins {
-			pinmux = <K1_PADCONF(0, 1)>,	/* gmac0_rxdv */
-				 <K1_PADCONF(1, 1)>,	/* gmac0_rx_d0 */
-				 <K1_PADCONF(2, 1)>,	/* gmac0_rx_d1 */
-				 <K1_PADCONF(3, 1)>,	/* gmac0_rx_clk */
-				 <K1_PADCONF(4, 1)>,	/* gmac0_rx_d2 */
-				 <K1_PADCONF(5, 1)>,	/* gmac0_rx_d3 */
-				 <K1_PADCONF(6, 1)>,	/* gmac0_tx_d0 */
-				 <K1_PADCONF(7, 1)>,	/* gmac0_tx_d1 */
-				 <K1_PADCONF(8, 1)>,	/* gmac0_tx */
-				 <K1_PADCONF(9, 1)>,	/* gmac0_tx_d2 */
-				 <K1_PADCONF(10, 1)>,	/* gmac0_tx_d3 */
-				 <K1_PADCONF(11, 1)>,	/* gmac0_tx_en */
-				 <K1_PADCONF(12, 1)>,	/* gmac0_mdc */
-				 <K1_PADCONF(13, 1)>,	/* gmac0_mdio */
-				 <K1_PADCONF(14, 1)>,	/* gmac0_int_n */
-				 <K1_PADCONF(45, 1)>;	/* gmac0_clk_ref */
+		pinmux = <K1_PADCONF(0, 1)>,	/* gmac0_rxdv */
+			 <K1_PADCONF(1, 1)>,	/* gmac0_rx_d0 */
+			 <K1_PADCONF(2, 1)>,	/* gmac0_rx_d1 */
+			 <K1_PADCONF(3, 1)>,	/* gmac0_rx_clk */
+			 <K1_PADCONF(4, 1)>,	/* gmac0_rx_d2 */
+			 <K1_PADCONF(5, 1)>,	/* gmac0_rx_d3 */
+			 <K1_PADCONF(6, 1)>,	/* gmac0_tx_d0 */
+			 <K1_PADCONF(7, 1)>,	/* gmac0_tx_d1 */
+			 <K1_PADCONF(8, 1)>,	/* gmac0_tx */
+			 <K1_PADCONF(9, 1)>,	/* gmac0_tx_d2 */
+			 <K1_PADCONF(10, 1)>,	/* gmac0_tx_d3 */
+			 <K1_PADCONF(11, 1)>,	/* gmac0_tx_en */
+			 <K1_PADCONF(12, 1)>,	/* gmac0_mdc */
+			 <K1_PADCONF(13, 1)>,	/* gmac0_mdio */
+			 <K1_PADCONF(14, 1)>,	/* gmac0_int_n */
+			 <K1_PADCONF(45, 1)>;	/* gmac0_clk_ref */
 
-			bias-pull-up = <0>;
-			drive-strength = <21>;
-		};
+		bias-pull-up = <0>;
+		drive-strength = <21>;
 	};
 
 	gmac1_cfg: gmac1-cfg {
-		gmac1-pins {
-			pinmux = <K1_PADCONF(29, 1)>,	/* gmac1_rxdv */
-				 <K1_PADCONF(30, 1)>,	/* gmac1_rx_d0 */
-				 <K1_PADCONF(31, 1)>,	/* gmac1_rx_d1 */
-				 <K1_PADCONF(32, 1)>,	/* gmac1_rx_clk */
-				 <K1_PADCONF(33, 1)>,	/* gmac1_rx_d2 */
-				 <K1_PADCONF(34, 1)>,	/* gmac1_rx_d3 */
-				 <K1_PADCONF(35, 1)>,	/* gmac1_tx_d0 */
-				 <K1_PADCONF(36, 1)>,	/* gmac1_tx_d1 */
-				 <K1_PADCONF(37, 1)>,	/* gmac1_tx */
-				 <K1_PADCONF(38, 1)>,	/* gmac1_tx_d2 */
-				 <K1_PADCONF(39, 1)>,	/* gmac1_tx_d3 */
-				 <K1_PADCONF(40, 1)>,	/* gmac1_tx_en */
-				 <K1_PADCONF(41, 1)>,	/* gmac1_mdc */
-				 <K1_PADCONF(42, 1)>,	/* gmac1_mdio */
-				 <K1_PADCONF(43, 1)>,	/* gmac1_int_n */
-				 <K1_PADCONF(46, 1)>;	/* gmac1_clk_ref */
+		pinmux = <K1_PADCONF(29, 1)>,	/* gmac1_rxdv */
+			 <K1_PADCONF(30, 1)>,	/* gmac1_rx_d0 */
+			 <K1_PADCONF(31, 1)>,	/* gmac1_rx_d1 */
+			 <K1_PADCONF(32, 1)>,	/* gmac1_rx_clk */
+			 <K1_PADCONF(33, 1)>,	/* gmac1_rx_d2 */
+			 <K1_PADCONF(34, 1)>,	/* gmac1_rx_d3 */
+			 <K1_PADCONF(35, 1)>,	/* gmac1_tx_d0 */
+			 <K1_PADCONF(36, 1)>,	/* gmac1_tx_d1 */
+			 <K1_PADCONF(37, 1)>,	/* gmac1_tx */
+			 <K1_PADCONF(38, 1)>,	/* gmac1_tx_d2 */
+			 <K1_PADCONF(39, 1)>,	/* gmac1_tx_d3 */
+			 <K1_PADCONF(40, 1)>,	/* gmac1_tx_en */
+			 <K1_PADCONF(41, 1)>,	/* gmac1_mdc */
+			 <K1_PADCONF(42, 1)>,	/* gmac1_mdio */
+			 <K1_PADCONF(43, 1)>,	/* gmac1_int_n */
+			 <K1_PADCONF(46, 1)>;	/* gmac1_clk_ref */
 
-			bias-pull-up = <0>;
-			drive-strength = <21>;
-		};
+		bias-pull-up = <0>;
+		drive-strength = <21>;
 	};
 
 	uart0_2_cfg: uart0-2-cfg {
-		uart0-2-pins {
-			pinmux = <K1_PADCONF(68, 2)>,
-				 <K1_PADCONF(69, 2)>;
+		pinmux = <K1_PADCONF(68, 2)>,
+			 <K1_PADCONF(69, 2)>;
 
-			bias-pull-up = <0>;
-			drive-strength = <32>;
-		};
+		bias-pull-up = <0>;
+		drive-strength = <32>;
+		bootph-pre-ram;
+	};
+
+	i2c2_0_cfg: i2c2-0-cfg {
+		pinmux = <K1_PADCONF(84, 4)>,	/* I2C2_SCL */
+			 <K1_PADCONF(85, 4)>;	/* I2C2_SDA */
+		bootph-pre-ram;
 	};
 
 	pwm14_1_cfg: pwm14-1-cfg {
-		pwm14-1-pins {
-			pinmux = <K1_PADCONF(44, 4)>;
-			bias-pull-up = <0>;
-			drive-strength = <32>;
-		};
+		pinmux = <K1_PADCONF(44, 4)>;
+		bias-pull-up = <0>;
+		drive-strength = <32>;
 	};
 };
-- 
2.25.1

[PATCH 06/16] configs: k1: enable pinctrl and gpio

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

Enable pinctrl and gpio configurations for Spacemit K1 SoC.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 board/spacemit/k1/MAINTAINERS | 2 ++
 configs/spacemit_k1_defconfig | 6 +++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/board/spacemit/k1/MAINTAINERS b/board/spacemit/k1/MAINTAINERS
index 408621ab819..6a2c4c23f9f 100644
--- a/board/spacemit/k1/MAINTAINERS
+++ b/board/spacemit/k1/MAINTAINERS
@@ -6,6 +6,8 @@ S:	Maintained
 F:	board/spacemit/k1/
 F:	configs/spacemit_k1_defconfig
 F:	doc/board/spacemit/bananapi-f3.rst
+F:	drivers/gpio/spacemit_gpio.c
 F:	drivers/i2c/k1_i2c.c
+F:	drivers/pinctrl/spacemit/pinctrl-k1.c
 F:	drivers/power/pmic/pmic_spacemit_p1.c
 F:	drivers/power/regulator/spacemit_p1_regulator.c
diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig
index 16754ea98d3..29a3c71f19e 100644
--- a/configs/spacemit_k1_defconfig
+++ b/configs/spacemit_k1_defconfig
@@ -31,7 +31,11 @@ CONFIG_SYS_PBSIZE=276
 CONFIG_HUSH_PARSER=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_PINCTRL=y
-CONFIG_PINCTRL_SINGLE=y
+CONFIG_PINCTRL_SPACEMIT_K1=y
+CONFIG_GPIO=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_SPACEMIT_GPIO=y
 CONFIG_RESET_SPACEMIT_K1=y
 CONFIG_SPL_RESET_SPACEMIT_K1=y
 CONFIG_SYS_NS16550=y
-- 
2.25.1

[PATCH 07/16] mtd: spi: select SPL_SPI_FLASH_TINY in SPL stage

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

Fix to select CONFIG_SPL_SPI_FLASH_TINY in SPL_BUILD stage.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 drivers/mtd/spi/Makefile | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 44e67cd913a..9a96be11e6d 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -8,14 +8,13 @@ spi-nor-y := sf_probe.o spi-nor-ids.o
 
 ifdef CONFIG_XPL_BUILD
 obj-$(CONFIG_SPL_SPI_BOOT)	+= fsl_espi_spl.o
+endif
+
 ifeq ($(CONFIG_$(PHASE_)SPI_FLASH_TINY),y)
 spi-nor-y += spi-nor-tiny.o
 else
 spi-nor-y += spi-nor-core.o
 endif
-else
-spi-nor-y += spi-nor-core.o
-endif
 
 obj-$(CONFIG_SPI_FLASH) += spi-nor.o
 obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
-- 
2.25.1

[PATCH 08/16] mtd: spi: enable spi_nor_remove() in soft reset config

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

spi_nor_remove() is only implemented in spi-nor-core.o, not spi-nor-tiny.o.

So make spi_nor_remove() only valid for CONFIG_SPI_FLASH_SOFT_RESET.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 drivers/mtd/spi/sf_probe.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 7100b64bf22..dee03662d45 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -229,9 +229,11 @@ static int spi_flash_std_remove(struct udevice *dev)
 		spi_mem_dirmap_destroy(flash->dirmap.rdesc);
 	}
 
-	ret = spi_nor_remove(flash);
-	if (ret)
-		return ret;
+	if (CONFIG_IS_ENABLED(SPI_FLASH_SOFT_RESET)) {
+		ret = spi_nor_remove(flash);
+		if (ret)
+			return ret;
+	}
 
 	if (CONFIG_IS_ENABLED(SPI_FLASH_MTD))
 		spi_flash_mtd_unregister(flash);
-- 
2.25.1

[PATCH 09/16] spi: fsl: add support for Spacemit K1 SoC

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

Make FSL QSPI driver supporting Spacemit K1 SoC.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 drivers/spi/fsl_qspi.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 65ab3e306d7..5692510a558 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -267,6 +267,14 @@ static const struct fsl_qspi_devtype_data ls2080a_data = {
 	.little_endian = true,
 };
 
+static const struct fsl_qspi_devtype_data spacemit_k1_data = {
+	.rxfifo = SZ_128,
+	.txfifo = SZ_256,
+	.ahb_buf_size = SZ_128,
+	.quirks = QUADSPI_QUIRK_TKT253890,
+	.little_endian = true,
+};
+
 struct fsl_qspi {
 	struct udevice *dev;
 	void __iomem *iobase;
@@ -870,6 +878,7 @@ static const struct udevice_id fsl_qspi_ids[] = {
 	{ .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, },
 	{ .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls2080a_data, },
 	{ .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, },
+	{ .compatible = "spacemit,k1-qspi", .data = (ulong)&spacemit_k1_data, },
 	{ }
 };
 
-- 
2.25.1

[PATCH 10/16] dts: k1: add QSPI controller support

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

Add QSPI controller support in DTS for Spacemit K1 SoC.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 arch/riscv/dts/k1-spl.dts | 15 +++++++++++++++
 arch/riscv/dts/k1.dtsi    | 16 ++++++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/arch/riscv/dts/k1-spl.dts b/arch/riscv/dts/k1-spl.dts
index 6f9407aada6..e3311af76e6 100644
--- a/arch/riscv/dts/k1-spl.dts
+++ b/arch/riscv/dts/k1-spl.dts
@@ -226,3 +226,18 @@
 		};
 	};
 };
+
+&qspi {
+	status = "okay";
+	bootph-pre-ram;
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <26500000>;
+		m25p,fast-read;
+		broken-flash-reset;
+		status = "okay";
+		bootph-pre-ram;
+	};
+};
diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi
index fc3a693a10e..96f604b0561 100644
--- a/arch/riscv/dts/k1.dtsi
+++ b/arch/riscv/dts/k1.dtsi
@@ -879,6 +879,22 @@
 				status = "disabled";
 			};
 
+			qspi: spi@d420c000 {
+				compatible = "spacemit,k1-qspi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x0 0xd420c000 0x0 0x1000>,
+				      <0x0 0xb8000000 0x0 0xc00000>;
+				reg-names = "QuadSPI", "QuadSPI-memory";
+				clocks = <&syscon_apmu CLK_QSPI_BUS>,
+					 <&syscon_apmu CLK_QSPI>;
+				clock-names = "qspi_en", "qspi";
+				resets = <&syscon_apmu RESET_QSPI>,
+					 <&syscon_apmu RESET_QSPI_BUS>;
+				interrupts = <117>;
+				status = "disabled";
+			};
+
 			sec_uart1: serial@f0612000 {
 				compatible = "spacemit,k1-uart",
 					     "intel,xscale-uart";
-- 
2.25.1

[PATCH 11/16] board: k1: enable SPI NOR flash in SPL

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

Enable SPI NOR flash in SPL stage.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 board/spacemit/k1/spl.c       | 24 +++++++++++++++++++++++-
 configs/spacemit_k1_defconfig | 22 ++++++++++++++++++++++
 2 files changed, 45 insertions(+), 1 deletion(-)

diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c
index 5af804f0409..77b6df1371b 100644
--- a/board/spacemit/k1/spl.c
+++ b/board/spacemit/k1/spl.c
@@ -20,6 +20,7 @@
 #include <spl.h>
 #include <tlv_eeprom.h>
 #include "tlv_codes.h"
+#include <spi_flash.h>
 
 #define MUX_MODE4		4
 #define EDGE_NONE		BIT(6)
@@ -309,6 +310,21 @@ void ddr_early_init(void)
 		log_info("DDR isn't invalid\n");
 }
 
+void nor_early_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device(UCLASS_SPI, 0, &dev);
+	if (ret)
+		panic("Fail to detect spi controller.\n");
+	udelay(10);
+	ret = uclass_get_device(UCLASS_SPI_FLASH, 0, &dev);
+	if (ret)
+		panic("Fail to detect spi nor flash.\n");
+	udelay(10);
+}
+
 void board_init_f(ulong dummy)
 {
 	u8 i2c_buf[I2C_BUF_SIZE];
@@ -335,13 +351,19 @@ void board_init_f(ulong dummy)
 	pmic_init();
 
 	ddr_early_init();
+	nor_early_init();
 }
 
 u32 spl_boot_device(void)
 {
-	return BOOT_DEVICE_NOR;
+	return BOOT_DEVICE_SPI;
 }
 
 void spl_board_init(void)
 {
 }
+
+void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
+{
+	return (void *)CONFIG_SPL_LOAD_FIT_ADDRESS;
+}
diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig
index 29a3c71f19e..97b6c8cbbb0 100644
--- a/configs/spacemit_k1_defconfig
+++ b/configs/spacemit_k1_defconfig
@@ -14,6 +14,7 @@ CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xc0840000
 CONFIG_SPL_SIZE_LIMIT=0x31000
 CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_HAS_LOAD_FIT_ADDRESS=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x08000000
 CONFIG_STACK_SIZE=0x100000
 CONFIG_SYS_BOOTM_LEN=0xa000000
@@ -29,7 +30,10 @@ CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
 # CONFIG_BOARD_INIT is not set
 CONFIG_HUSH_PARSER=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_OFFSET=0x60000
+CONFIG_ENV_SIZE=0x4000
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_SPACEMIT_K1=y
 CONFIG_GPIO=y
@@ -65,6 +69,18 @@ CONFIG_DM_PMIC=y
 CONFIG_PMIC_SPACEMIT_P1=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_SPACEMIT_P1=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_FSL_QSPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_MEM=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x000a0000
+CONFIG_CMD_SPI=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MULTI_DTB_FIT=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SPL_LIB_RATIONAL=y
 CONFIG_SPL_DM_RESET=y
@@ -78,3 +94,9 @@ CONFIG_SPL_CMD_TLV_EEPROM=y
 CONFIG_SPL_POWER=y
 CONFIG_SPL_DM_PMIC=y
 CONFIG_SPL_DM_REGULATOR=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_SPI_FLASH_TINY=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
-- 
2.25.1

[PATCH 12/16] riscv: binman: Always set default configuration in FIT image

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

When CONFIG_MULTI_DTB_FIT is enabled, the FIT image contains multiple
device tree configurations for different boards. The default
configuration must be explicitly set to ensure the FIT framework
traverses all available configurations instead of falling back to
CONFIG_DEFAULT_DEVICE_TREE.

Without this default property, fit_find_config_node() will use
CONFIG_DEFAULT_DEVICE_TREE as the configuration name to match.
This prevents the SPL from correctly selecting the appropriate
DTB based on runtime board detection (e.g., from EEPROM).

Remove the conditional guard so that "default = conf-1" is always
present in the FIT image, regardless of CONFIG_MULTI_DTB_FIT.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 arch/riscv/dts/binman.dtsi | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index b518560bb94..84c261c6849 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -93,9 +93,7 @@
 
 			configurations {
 
-#ifndef CONFIG_MULTI_DTB_FIT
 				default = "conf-1";
-#endif
 
 #if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
 				@conf-SEQ {
-- 
2.25.1

[PATCH 13/16] spacemit: k1: append RISCV_MMODE_TIMERBASE

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

Append the definition of RISCV_MMODE_TIMER_BASE & RISCV_MMODE_TIMEROFF.
Since they're required by riscv aclint timer.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 include/configs/k1.h | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/include/configs/k1.h b/include/configs/k1.h
index 8e148803dea..33cbbeb6fd6 100644
--- a/include/configs/k1.h
+++ b/include/configs/k1.h
@@ -8,12 +8,14 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CFG_SYS_SDRAM_BASE	    0x0
+#define CFG_SYS_SDRAM_BASE		0x0
 
-#define CFG_SYS_NS16550_CLK	    14700000
-#define CFG_SYS_NS16550_IER	    0x40 /* UART Unit Enable */
+#define CFG_SYS_NS16550_CLK		14700000
+#define CFG_SYS_NS16550_IER		0x40 /* UART Unit Enable */
 
-#define RISCV_MMODE_TIMER_FREQ	    24000000
-#define RISCV_SMODE_TIMER_FREQ	    24000000
+#define RISCV_MMODE_TIMERBASE		0xe4000000
+#define RISCV_MMODE_TIMEROFF		0xbff8
+#define RISCV_MMODE_TIMER_FREQ		24000000
+#define RISCV_SMODE_TIMER_FREQ		24000000
 
 #endif /* __CONFIG_H */
-- 
2.25.1

[PATCH 14/16] spacemit: k1: Add multiple device tree support

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

Enable multiple DTB support in the FIT image for the Spacemit K1 SoC,
allowing a single U-Boot binary to support different board variants.

The SPL reads the board type from EEPROM and selects the corresponding
device tree at runtime via board_fit_config_name_match(), ensuring the
correct hardware description is passed to U-Boot proper.

Enlarge CONFIG_SYS_MALLOC_F_LEN to enable multiple device tree support.

Switch to MMODE since opensbi firmware is included at the same tim.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 arch/riscv/dts/Makefile           |   2 +-
 arch/riscv/dts/k1-bananapi-f3.dts | 161 ++++++++++++++++++++++++
 arch/riscv/dts/k1-muse-pi-pro.dts | 199 ++++++++++++++++++++++++++++++
 arch/riscv/dts/k1-spl.dts         |  47 +++----
 board/spacemit/k1/spl.c           |  29 ++++-
 configs/spacemit_k1_defconfig     |   7 +-
 6 files changed, 415 insertions(+), 30 deletions(-)
 create mode 100644 arch/riscv/dts/k1-muse-pi-pro.dts

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 61a7acabd27..22b62e25d4d 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -9,7 +9,7 @@ dtb-$(CONFIG_TARGET_LICHEERV_NANO) += sg2002-licheerv-nano-b.dtb
 dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
 dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-dtb-$(CONFIG_TARGET_SPACEMIT_K1) += k1-bananapi-f3.dtb k1-spl.dtb
+dtb-$(CONFIG_TARGET_SPACEMIT_K1) += k1-bananapi-f3.dtb k1-muse-pi-pro.dtb k1-spl.dtb
 dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
 dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb
 dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb
diff --git a/arch/riscv/dts/k1-bananapi-f3.dts b/arch/riscv/dts/k1-bananapi-f3.dts
index 6b5b83bcdb9..ea11029c182 100644
--- a/arch/riscv/dts/k1-bananapi-f3.dts
+++ b/arch/riscv/dts/k1-bananapi-f3.dts
@@ -21,8 +21,169 @@
 	};
 };
 
+&vctcxo_1m {
+	status = "okay";
+};
+
+&vctcxo_24m {
+	status = "okay";
+};
+
+&vctcxo_3m {
+	status = "okay";
+};
+
+&osc_32k {
+	status = "okay";
+};
+
+&soc {
+	system-controller@d4050000 {
+		status = "okay";
+	};
+	clock-controller@d4090000 {
+		status = "okay";
+	};
+	system-controller@d4282800 {
+		status = "okay";
+	};
+	system-controller@d4015000 {
+		clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
+			 <&vctcxo_24m>, <&syscon_mpmu CLK_PLL1_31P5>,
+			 <&pll CLK_PLL1_D4>;
+		clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
+			      "vctcxo_24m", "pll1_d78_31p5", "pll1_d4";
+		status = "okay";
+	};
+
+	i2c@d4012000 {		/* i2c2 */
+		status = "okay";
+		eeprom: eeprom {
+			compatible = "atmel,24c02";
+			reg = <0x50>;
+			status = "okay";
+		};
+	};
+
+	reset-controller@d4050000 {
+		status = "okay";
+	};
+};
+
 &uart0 {
+	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_2_cfg>;
+};
+
+&i2c8 {
 	status = "okay";
+	pmic@41 {
+		compatible = "spacemit,p1";
+		reg = <0x41>;
+		status = "okay";
+
+		regulators {
+			buck1 {
+				regulator-name = "vdd_core";
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3450000>;
+				regulator-ramp-delay = <5000>;
+				regulator-always-on;
+			};
+
+			buck2 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3450000>;
+				regulator-ramp-delay = <5000>;
+				regulator-always-on;
+			};
+
+			buck3_1v8: buck3 {
+				regulator-name = "vdd_1v8";
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-ramp-delay = <5000>;
+				regulator-always-on;
+			};
+
+			buck4 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <5000>;
+				regulator-always-on;
+			};
+
+			buck5 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3450000>;
+				regulator-ramp-delay = <5000>;
+				regulator-always-on;
+			};
+
+			buck6 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3450000>;
+				regulator-ramp-delay = <5000>;
+				regulator-always-on;
+			};
+
+			aldo1 {
+				regulator-name = "vdd_1v8_mmc";
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+			};
+
+			aldo2 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			aldo3 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			aldo4 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			dldo1 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			dldo2 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			dldo3 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			dldo4 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			dldo5 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			dldo6 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			dldo7 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+		};
+	};
 };
diff --git a/arch/riscv/dts/k1-muse-pi-pro.dts b/arch/riscv/dts/k1-muse-pi-pro.dts
new file mode 100644
index 00000000000..43f08317e31
--- /dev/null
+++ b/arch/riscv/dts/k1-muse-pi-pro.dts
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2026 RISCstar Ltd.
+ */
+
+#include "k1.dtsi"
+#include "binman.dtsi"
+
+/ {
+	model = "spacemit k1-x MUSE-Pi-Pro board";
+	compatible = "spacemit,muse-pi-pro", "spacemit,k1";
+
+	aliases {
+		console = &uart0;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&vctcxo_1m {
+	status = "okay";
+};
+
+&vctcxo_24m {
+	status = "okay";
+};
+
+&vctcxo_3m {
+	status = "okay";
+};
+
+&osc_32k {
+	status = "okay";
+};
+
+&soc {
+	system-controller@d4050000 {
+		status = "okay";
+	};
+	clock-controller@d4090000 {
+		status = "okay";
+	};
+	system-controller@d4282800 {
+		status = "okay";
+	};
+	system-controller@d4015000 {
+		clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
+			 <&vctcxo_24m>, <&syscon_mpmu CLK_PLL1_31P5>,
+			 <&pll CLK_PLL1_D4>;
+		clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
+			      "vctcxo_24m", "pll1_d78_31p5", "pll1_d4";
+		status = "okay";
+	};
+
+	i2c@d4012000 {		/* i2c2 */
+		status = "okay";
+		eeprom: eeprom {
+			compatible = "atmel,24c02";
+			reg = <0x50>;
+			status = "okay";
+		};
+	};
+
+	reset-controller@d4050000 {
+		status = "okay";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&i2c8 {
+	status = "okay";
+	pmic@41 {
+		compatible = "spacemit,p1";
+		reg = <0x41>;
+		status = "okay";
+
+		regulators {
+			buck1 {
+				regulator-name = "vdd_core";
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3450000>;
+				regulator-ramp-delay = <5000>;
+				regulator-always-on;
+			};
+
+			buck2 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3450000>;
+				regulator-ramp-delay = <5000>;
+				regulator-always-on;
+			};
+
+			buck3_1v8: buck3 {
+				regulator-name = "vdd_1v8";
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-ramp-delay = <5000>;
+				regulator-always-on;
+			};
+
+			buck4 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <5000>;
+				regulator-always-on;
+			};
+
+			buck5 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3450000>;
+				regulator-ramp-delay = <5000>;
+				regulator-always-on;
+			};
+
+			buck6 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3450000>;
+				regulator-ramp-delay = <5000>;
+				regulator-always-on;
+			};
+
+			aldo1 {
+				regulator-name = "vdd_1v8_mmc";
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+			};
+
+			aldo2 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			aldo3 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			aldo4 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			dldo1 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			dldo2 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			dldo3 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			dldo4 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			dldo5 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			dldo6 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+
+			dldo7 {
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <3400000>;
+			};
+		};
+	};
+};
+
+&qspi {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <26500000>;
+		m25p,fast-read;
+		broken-flash-reset;
+		status = "okay";
+	};
+};
diff --git a/arch/riscv/dts/k1-spl.dts b/arch/riscv/dts/k1-spl.dts
index e3311af76e6..b8b600b792e 100644
--- a/arch/riscv/dts/k1-spl.dts
+++ b/arch/riscv/dts/k1-spl.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include "k1.dtsi"
+#include "binman.dtsi"
 
 / {
 	model = "spacemit k1 spl";
@@ -19,29 +20,6 @@
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
-
-	binman {
-		u-boot-spl-ddr {
-			type = "section";
-			filename = "u-boot-spl-ddr.bin";
-			pad-byte = <0xff>;
-
-			u-boot-spl {
-			};
-
-			ddr-fw {
-				type = "blob";
-				filename = "ddr_fw.bin";
-				align = <64>;
-			};
-
-			u-boot-any {
-				type = "section";
-				size = <0>;
-				offset = <0>;
-			};
-		};
-	};
 };
 
 &vctcxo_1m {
@@ -54,6 +32,29 @@
 	bootph-pre-ram;
 };
 
+&binman {
+	u-boot-spl-ddr {
+		type = "section";
+		filename = "u-boot-spl-ddr.bin";
+		pad-byte = <0xff>;
+
+		u-boot-spl {
+		};
+
+		ddr-fw {
+			type = "blob";
+			filename = "ddr_fw.bin";
+			align = <64>;
+		};
+
+		u-boot-any {
+			type = "section";
+			size = <0>;
+			offset = <0>;
+		};
+	};
+};
+
 &vctcxo_3m {
 	status = "okay";
 	bootph-pre-ram;
diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c
index 77b6df1371b..9b30bc9ea7e 100644
--- a/board/spacemit/k1/spl.c
+++ b/board/spacemit/k1/spl.c
@@ -8,12 +8,12 @@
 #include <binman_sym.h>
 #include <clk.h>
 #include <clk-uclass.h>
-#include <cpu_func.h>
 #include <configs/k1.h>
 #include <cpu_func.h>
 #include <dm/device.h>
 #include <dm/uclass.h>
 #include <i2c.h>
+#include <linux/ctype.h>
 #include <linux/delay.h>
 #include <log.h>
 #include <power/regulator.h>
@@ -56,6 +56,8 @@ struct ddr_cfg {
 binman_sym_declare(ulong, ddr_fw, image_pos);
 binman_sym_declare(ulong, ddr_fw, size);
 
+char product_name[I2C_BUF_SIZE] = "k1";
+
 static void reset_early_init(void)
 {
 	struct udevice *dev;
@@ -327,7 +329,6 @@ void nor_early_init(void)
 
 void board_init_f(ulong dummy)
 {
-	u8 i2c_buf[I2C_BUF_SIZE];
 	int ret;
 
 	ret = spl_early_init();
@@ -343,11 +344,11 @@ void board_init_f(ulong dummy)
 	preloader_console_init();
 
 	i2c_early_init();
-	ret = read_product_name(i2c_buf, I2C_BUF_SIZE);
+	ret = read_product_name(product_name, I2C_BUF_SIZE);
 	if (ret)
 		log_info("Fail to detect board:%d\n", ret);
 	else
-		log_info("Get board name:%s\n", (char *)i2c_buf);
+		log_info("Get board name:%s\n", product_name);
 	pmic_init();
 
 	ddr_early_init();
@@ -363,6 +364,26 @@ void spl_board_init(void)
 {
 }
 
+int board_fit_config_name_match(const char *name)
+{
+	char fdt_name[I2C_BUF_SIZE];
+	int i;
+
+	memset(fdt_name, 0, I2C_BUF_SIZE);
+	if (!strncmp(product_name, "k1-x_", 5)) {
+		snprintf(fdt_name, I2C_BUF_SIZE, "%s-%s", "k1",
+			 &product_name[5]);
+	}
+	for (i = 0; i < I2C_BUF_SIZE; i++) {
+		if (fdt_name[i] == '\0')
+			break;
+		fdt_name[i] = tolower(fdt_name[i]);
+	}
+	if (!strcmp(name, fdt_name))
+		return 0;
+	return -ENOENT;
+}
+
 void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
 {
 	return (void *)CONFIG_SPL_LOAD_FIT_ADDRESS;
diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig
index 97b6c8cbbb0..13f055cdf53 100644
--- a/configs/spacemit_k1_defconfig
+++ b/configs/spacemit_k1_defconfig
@@ -4,6 +4,7 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000
 CONFIG_DEFAULT_DEVICE_TREE="k1-spl"
+CONFIG_OF_LIST="k1-bananapi-f3 k1-muse-pi-pro"
 CONFIG_SPL=y
 CONFIG_SPL_TEXT_BASE=0xc0801000
 CONFIG_SPL_MAX_SIZE=0x33000
@@ -22,7 +23,8 @@ CONFIG_SYS_LOAD_ADDR=0x200000
 CONFIG_ARCH_RV64I=y
 CONFIG_RISCV_SMODE=y
 CONFIG_TARGET_SPACEMIT_K1=y
-CONFIG_SPL_RISCV_SMODE=y
+CONFIG_SPL_RISCV_MMODE=y
+# CONFIG_SPL_SMP is not set
 CONFIG_FIT=y
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_OF_BOARD_SETUP=y
@@ -58,7 +60,7 @@ CONFIG_CLK=y
 CONFIG_CLK_CCF=y
 CONFIG_CLK_SPACEMIT=y
 CONFIG_CLK_SPACEMIT_K1=y
-CONFIG_SYS_MALLOC_F_LEN=0x5000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_SPACEMIT_K1=y
 CONFIG_MISC=y
@@ -100,3 +102,4 @@ CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SPL_SPI_FLASH_TINY=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x5300
-- 
2.25.1

[PATCH 15/16] spacemit: k1: Add support for mmc regulator initialization

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

Initialize the 1.8V supply for the MMC I/O domain to ensure proper
voltage configuration for MMC interfaces. This is required for
reliable operation of the MMC controller.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 board/spacemit/k1/spl.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c
index 9b30bc9ea7e..2556dfe047a 100644
--- a/board/spacemit/k1/spl.c
+++ b/board/spacemit/k1/spl.c
@@ -196,6 +196,9 @@ static void set_vdd_mmc(void)
 	ret = regulator_get_by_platname("vdd_1v8_mmc", &dev);
 	if (ret)
 		panic("Fail to detect vdd_1v8_mmc (%d)\n", ret);
+	ret = regulator_set_value(dev, 1800000);
+	if (ret)
+		log_warning("Fail to set vdd_1v8_mmc as 1800000 (%d)\n", ret);
 	ret = regulator_set_enable(dev, true);
 	if (ret)
 		log_warning("Fail to enable vdd_1v8_mmc (%d)\n", ret);
-- 
2.25.1

[PATCH 16/16] spacemit: k1: rename device tree prefix from "k1-" to "k1_"

[Raymond Mao]

From: Raymond Mao <raymond.mao@riscstar.com>

This change replaces the hyphen ("-") in the DTS prefix with an
underscore ("_") for consistency with other prefixes in the
Spacemit K1 SoC platform.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 arch/riscv/dts/Makefile                                   | 2 +-
 arch/riscv/dts/{k1-bananapi-f3.dts => k1_bananapi-f3.dts} | 2 +-
 arch/riscv/dts/{k1-muse-pi-pro.dts => k1_muse-pi-pro.dts} | 0
 arch/riscv/dts/{k1-pinctrl.dtsi => k1_pinctrl.dtsi}       | 0
 arch/riscv/dts/{k1-spl.dts => k1_spl.dts}                 | 0
 board/spacemit/k1/spl.c                                   | 2 +-
 configs/spacemit_k1_defconfig                             | 4 ++--
 7 files changed, 5 insertions(+), 5 deletions(-)
 rename arch/riscv/dts/{k1-bananapi-f3.dts => k1_bananapi-f3.dts} (99%)
 rename arch/riscv/dts/{k1-muse-pi-pro.dts => k1_muse-pi-pro.dts} (100%)
 rename arch/riscv/dts/{k1-pinctrl.dtsi => k1_pinctrl.dtsi} (100%)
 rename arch/riscv/dts/{k1-spl.dts => k1_spl.dts} (100%)

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 22b62e25d4d..3827ff72215 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -9,7 +9,7 @@ dtb-$(CONFIG_TARGET_LICHEERV_NANO) += sg2002-licheerv-nano-b.dtb
 dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
 dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-dtb-$(CONFIG_TARGET_SPACEMIT_K1) += k1-bananapi-f3.dtb k1-muse-pi-pro.dtb k1-spl.dtb
+dtb-$(CONFIG_TARGET_SPACEMIT_K1) += k1_bananapi-f3.dtb k1_muse-pi-pro.dtb k1_spl.dtb
 dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
 dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb
 dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb
diff --git a/arch/riscv/dts/k1-bananapi-f3.dts b/arch/riscv/dts/k1_bananapi-f3.dts
similarity index 99%
rename from arch/riscv/dts/k1-bananapi-f3.dts
rename to arch/riscv/dts/k1_bananapi-f3.dts
index ea11029c182..bcb5be5f1bc 100644
--- a/arch/riscv/dts/k1-bananapi-f3.dts
+++ b/arch/riscv/dts/k1_bananapi-f3.dts
@@ -5,7 +5,7 @@
 
 #include "k1.dtsi"
 #include "binman.dtsi"
-#include "k1-pinctrl.dtsi"
+#include "k1_pinctrl.dtsi"
 
 / {
 	model = "Banana Pi BPI-F3";
diff --git a/arch/riscv/dts/k1-muse-pi-pro.dts b/arch/riscv/dts/k1_muse-pi-pro.dts
similarity index 100%
rename from arch/riscv/dts/k1-muse-pi-pro.dts
rename to arch/riscv/dts/k1_muse-pi-pro.dts
diff --git a/arch/riscv/dts/k1-pinctrl.dtsi b/arch/riscv/dts/k1_pinctrl.dtsi
similarity index 100%
rename from arch/riscv/dts/k1-pinctrl.dtsi
rename to arch/riscv/dts/k1_pinctrl.dtsi
diff --git a/arch/riscv/dts/k1-spl.dts b/arch/riscv/dts/k1_spl.dts
similarity index 100%
rename from arch/riscv/dts/k1-spl.dts
rename to arch/riscv/dts/k1_spl.dts
diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c
index 2556dfe047a..b8e1327dc57 100644
--- a/board/spacemit/k1/spl.c
+++ b/board/spacemit/k1/spl.c
@@ -374,7 +374,7 @@ int board_fit_config_name_match(const char *name)
 
 	memset(fdt_name, 0, I2C_BUF_SIZE);
 	if (!strncmp(product_name, "k1-x_", 5)) {
-		snprintf(fdt_name, I2C_BUF_SIZE, "%s-%s", "k1",
+		snprintf(fdt_name, I2C_BUF_SIZE, "%s_%s", "k1",
 			 &product_name[5]);
 	}
 	for (i = 0; i < I2C_BUF_SIZE; i++) {
diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig
index 13f055cdf53..ddd0c959c12 100644
--- a/configs/spacemit_k1_defconfig
+++ b/configs/spacemit_k1_defconfig
@@ -3,8 +3,8 @@ CONFIG_SYS_MALLOC_LEN=0x1000000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000
-CONFIG_DEFAULT_DEVICE_TREE="k1-spl"
-CONFIG_OF_LIST="k1-bananapi-f3 k1-muse-pi-pro"
+CONFIG_DEFAULT_DEVICE_TREE="k1_spl"
+CONFIG_OF_LIST="k1_bananapi-f3 k1_muse-pi-pro"
 CONFIG_SPL=y
 CONFIG_SPL_TEXT_BASE=0xc0801000
 CONFIG_SPL_MAX_SIZE=0x33000
-- 
2.25.1

Re: [PATCH 16/16] spacemit: k1: rename device tree prefix from "k1-" to "k1_"

[Conor Dooley]

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On Wed, Apr 22, 2026 at 10:31:12AM -0400, Raymond Mao wrote:
> From: Raymond Mao <raymond.mao@riscstar.com>
> 
> This change replaces the hyphen ("-") in the DTS prefix with an
> underscore ("_") for consistency with other prefixes in the
> Spacemit K1 SoC platform.

Doesn't this inconsistency only exist because you added files that made
it inconsistent? Using hyphens is the norm anyway, right?

> 
> Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
> ---
>  arch/riscv/dts/Makefile                                   | 2 +-
>  arch/riscv/dts/{k1-bananapi-f3.dts => k1_bananapi-f3.dts} | 2 +-
>  arch/riscv/dts/{k1-muse-pi-pro.dts => k1_muse-pi-pro.dts} | 0
>  arch/riscv/dts/{k1-pinctrl.dtsi => k1_pinctrl.dtsi}       | 0
>  arch/riscv/dts/{k1-spl.dts => k1_spl.dts}                 | 0
>  board/spacemit/k1/spl.c                                   | 2 +-
>  configs/spacemit_k1_defconfig                             | 4 ++--
>  7 files changed, 5 insertions(+), 5 deletions(-)
>  rename arch/riscv/dts/{k1-bananapi-f3.dts => k1_bananapi-f3.dts} (99%)
>  rename arch/riscv/dts/{k1-muse-pi-pro.dts => k1_muse-pi-pro.dts} (100%)
>  rename arch/riscv/dts/{k1-pinctrl.dtsi => k1_pinctrl.dtsi} (100%)
>  rename arch/riscv/dts/{k1-spl.dts => k1_spl.dts} (100%)
> 
> diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> index 22b62e25d4d..3827ff72215 100644
> --- a/arch/riscv/dts/Makefile
> +++ b/arch/riscv/dts/Makefile
> @@ -9,7 +9,7 @@ dtb-$(CONFIG_TARGET_LICHEERV_NANO) += sg2002-licheerv-nano-b.dtb
>  dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
>  dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
>  dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> -dtb-$(CONFIG_TARGET_SPACEMIT_K1) += k1-bananapi-f3.dtb k1-muse-pi-pro.dtb k1-spl.dtb
> +dtb-$(CONFIG_TARGET_SPACEMIT_K1) += k1_bananapi-f3.dtb k1_muse-pi-pro.dtb k1_spl.dtb
>  dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
>  dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb
>  dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb
> diff --git a/arch/riscv/dts/k1-bananapi-f3.dts b/arch/riscv/dts/k1_bananapi-f3.dts
> similarity index 99%
> rename from arch/riscv/dts/k1-bananapi-f3.dts
> rename to arch/riscv/dts/k1_bananapi-f3.dts
> index ea11029c182..bcb5be5f1bc 100644
> --- a/arch/riscv/dts/k1-bananapi-f3.dts
> +++ b/arch/riscv/dts/k1_bananapi-f3.dts
> @@ -5,7 +5,7 @@
>  
>  #include "k1.dtsi"
>  #include "binman.dtsi"
> -#include "k1-pinctrl.dtsi"
> +#include "k1_pinctrl.dtsi"
>  
>  / {
>  	model = "Banana Pi BPI-F3";
> diff --git a/arch/riscv/dts/k1-muse-pi-pro.dts b/arch/riscv/dts/k1_muse-pi-pro.dts
> similarity index 100%
> rename from arch/riscv/dts/k1-muse-pi-pro.dts
> rename to arch/riscv/dts/k1_muse-pi-pro.dts
> diff --git a/arch/riscv/dts/k1-pinctrl.dtsi b/arch/riscv/dts/k1_pinctrl.dtsi
> similarity index 100%
> rename from arch/riscv/dts/k1-pinctrl.dtsi
> rename to arch/riscv/dts/k1_pinctrl.dtsi
> diff --git a/arch/riscv/dts/k1-spl.dts b/arch/riscv/dts/k1_spl.dts
> similarity index 100%
> rename from arch/riscv/dts/k1-spl.dts
> rename to arch/riscv/dts/k1_spl.dts
> diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c
> index 2556dfe047a..b8e1327dc57 100644
> --- a/board/spacemit/k1/spl.c
> +++ b/board/spacemit/k1/spl.c
> @@ -374,7 +374,7 @@ int board_fit_config_name_match(const char *name)
>  
>  	memset(fdt_name, 0, I2C_BUF_SIZE);
>  	if (!strncmp(product_name, "k1-x_", 5)) {
> -		snprintf(fdt_name, I2C_BUF_SIZE, "%s-%s", "k1",
> +		snprintf(fdt_name, I2C_BUF_SIZE, "%s_%s", "k1",
>  			 &product_name[5]);
>  	}
>  	for (i = 0; i < I2C_BUF_SIZE; i++) {
> diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig
> index 13f055cdf53..ddd0c959c12 100644
> --- a/configs/spacemit_k1_defconfig
> +++ b/configs/spacemit_k1_defconfig
> @@ -3,8 +3,8 @@ CONFIG_SYS_MALLOC_LEN=0x1000000
>  CONFIG_NR_DRAM_BANKS=2
>  CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000
> -CONFIG_DEFAULT_DEVICE_TREE="k1-spl"
> -CONFIG_OF_LIST="k1-bananapi-f3 k1-muse-pi-pro"
> +CONFIG_DEFAULT_DEVICE_TREE="k1_spl"
> +CONFIG_OF_LIST="k1_bananapi-f3 k1_muse-pi-pro"
>  CONFIG_SPL=y
>  CONFIG_SPL_TEXT_BASE=0xc0801000
>  CONFIG_SPL_MAX_SIZE=0x33000
> -- 
> 2.25.1
> 

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Re: [PATCH 04/16] dts: k1: import pinctrl dts file from upstream folder

[Conor Dooley]

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On Wed, Apr 22, 2026 at 10:31:00AM -0400, Raymond Mao wrote:
> From: Raymond Mao <raymond.mao@riscstar.com>
> 
> Import k1-pinctrl.dtsi from upstream folder.

Why doesn't the platform just use the upstream dts directly?

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Re: [PATCH 16/16] spacemit: k1: rename device tree prefix from "k1-" to "k1_"

[Heinrich Schuchardt]

Am 29. April 2026 21:42:04 MESZ schrieb Conor Dooley <conor@kernel.org>:
>On Wed, Apr 22, 2026 at 10:31:12AM -0400, Raymond Mao wrote:
>> From: Raymond Mao <raymond.mao@riscstar.com>
>> 
>> This change replaces the hyphen ("-") in the DTS prefix with an
>> underscore ("_") for consistency with other prefixes in the
>> Spacemit K1 SoC platform.
>
>Doesn't this inconsistency only exist because you added files that made
>it inconsistent? Using hyphens is the norm anyway, right?

The kernel uses hyphens. We should not deviate from Linux. In the long term we want to use the upstream Linux device-trees in U-Boot.

Renaming in Linux should also be avoided.

Best regards

Heinrich

>
>> 
>> Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
>> ---
>>  arch/riscv/dts/Makefile                                   | 2 +-
>>  arch/riscv/dts/{k1-bananapi-f3.dts => k1_bananapi-f3.dts} | 2 +-
>>  arch/riscv/dts/{k1-muse-pi-pro.dts => k1_muse-pi-pro.dts} | 0
>>  arch/riscv/dts/{k1-pinctrl.dtsi => k1_pinctrl.dtsi}       | 0
>>  arch/riscv/dts/{k1-spl.dts => k1_spl.dts}                 | 0
>>  board/spacemit/k1/spl.c                                   | 2 +-
>>  configs/spacemit_k1_defconfig                             | 4 ++--
>>  7 files changed, 5 insertions(+), 5 deletions(-)
>>  rename arch/riscv/dts/{k1-bananapi-f3.dts => k1_bananapi-f3.dts} (99%)
>>  rename arch/riscv/dts/{k1-muse-pi-pro.dts => k1_muse-pi-pro.dts} (100%)
>>  rename arch/riscv/dts/{k1-pinctrl.dtsi => k1_pinctrl.dtsi} (100%)
>>  rename arch/riscv/dts/{k1-spl.dts => k1_spl.dts} (100%)
>> 
>> diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
>> index 22b62e25d4d..3827ff72215 100644
>> --- a/arch/riscv/dts/Makefile
>> +++ b/arch/riscv/dts/Makefile
>> @@ -9,7 +9,7 @@ dtb-$(CONFIG_TARGET_LICHEERV_NANO) += sg2002-licheerv-nano-b.dtb
>>  dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
>>  dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
>>  dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
>> -dtb-$(CONFIG_TARGET_SPACEMIT_K1) += k1-bananapi-f3.dtb k1-muse-pi-pro.dtb k1-spl.dtb
>> +dtb-$(CONFIG_TARGET_SPACEMIT_K1) += k1_bananapi-f3.dtb k1_muse-pi-pro.dtb k1_spl.dtb
>>  dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
>>  dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb
>>  dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb
>> diff --git a/arch/riscv/dts/k1-bananapi-f3.dts b/arch/riscv/dts/k1_bananapi-f3.dts
>> similarity index 99%
>> rename from arch/riscv/dts/k1-bananapi-f3.dts
>> rename to arch/riscv/dts/k1_bananapi-f3.dts
>> index ea11029c182..bcb5be5f1bc 100644
>> --- a/arch/riscv/dts/k1-bananapi-f3.dts
>> +++ b/arch/riscv/dts/k1_bananapi-f3.dts
>> @@ -5,7 +5,7 @@
>>  
>>  #include "k1.dtsi"
>>  #include "binman.dtsi"
>> -#include "k1-pinctrl.dtsi"
>> +#include "k1_pinctrl.dtsi"
>>  
>>  / {
>>  	model = "Banana Pi BPI-F3";
>> diff --git a/arch/riscv/dts/k1-muse-pi-pro.dts b/arch/riscv/dts/k1_muse-pi-pro.dts
>> similarity index 100%
>> rename from arch/riscv/dts/k1-muse-pi-pro.dts
>> rename to arch/riscv/dts/k1_muse-pi-pro.dts
>> diff --git a/arch/riscv/dts/k1-pinctrl.dtsi b/arch/riscv/dts/k1_pinctrl.dtsi
>> similarity index 100%
>> rename from arch/riscv/dts/k1-pinctrl.dtsi
>> rename to arch/riscv/dts/k1_pinctrl.dtsi
>> diff --git a/arch/riscv/dts/k1-spl.dts b/arch/riscv/dts/k1_spl.dts
>> similarity index 100%
>> rename from arch/riscv/dts/k1-spl.dts
>> rename to arch/riscv/dts/k1_spl.dts
>> diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c
>> index 2556dfe047a..b8e1327dc57 100644
>> --- a/board/spacemit/k1/spl.c
>> +++ b/board/spacemit/k1/spl.c
>> @@ -374,7 +374,7 @@ int board_fit_config_name_match(const char *name)
>>  
>>  	memset(fdt_name, 0, I2C_BUF_SIZE);
>>  	if (!strncmp(product_name, "k1-x_", 5)) {
>> -		snprintf(fdt_name, I2C_BUF_SIZE, "%s-%s", "k1",
>> +		snprintf(fdt_name, I2C_BUF_SIZE, "%s_%s", "k1",
>>  			 &product_name[5]);
>>  	}
>>  	for (i = 0; i < I2C_BUF_SIZE; i++) {
>> diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig
>> index 13f055cdf53..ddd0c959c12 100644
>> --- a/configs/spacemit_k1_defconfig
>> +++ b/configs/spacemit_k1_defconfig
>> @@ -3,8 +3,8 @@ CONFIG_SYS_MALLOC_LEN=0x1000000
>>  CONFIG_NR_DRAM_BANKS=2
>>  CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>>  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000
>> -CONFIG_DEFAULT_DEVICE_TREE="k1-spl"
>> -CONFIG_OF_LIST="k1-bananapi-f3 k1-muse-pi-pro"
>> +CONFIG_DEFAULT_DEVICE_TREE="k1_spl"
>> +CONFIG_OF_LIST="k1_bananapi-f3 k1_muse-pi-pro"
>>  CONFIG_SPL=y
>>  CONFIG_SPL_TEXT_BASE=0xc0801000
>>  CONFIG_SPL_MAX_SIZE=0x33000
>> -- 
>> 2.25.1
>> 

Re: [PATCH 04/16] dts: k1: import pinctrl dts file from upstream folder

[Yao Zi]

On Wed, Apr 29, 2026 at 08:48:39PM +0100, Conor Dooley wrote:
> On Wed, Apr 22, 2026 at 10:31:00AM -0400, Raymond Mao wrote:
> > From: Raymond Mao <raymond.mao@riscstar.com>
> > 
> > Import k1-pinctrl.dtsi from upstream folder.
> 
> Why doesn't the platform just use the upstream dts directly?

AFAIK, U-Boot's reset driver for SpacemiT K1 predates land of the
kernel side driver, and follows a complete different (and to me,
broken since it combines completely unrelated MMIO regions) ABI.

U-Boot's version,

	reset: reset-controller@d4050000 {
		compatible = "spacemit,k1-reset";
		reg = <0x0 0xd4050000 0x0 0x209c>,
		      <0x0 0xd4282800 0x0 0x400>,
		      <0x0 0xd4015000 0x0 0x1000>,
		      <0x0 0xd4090000 0x0 0x1000>,
		      <0x0 0xd4282c00 0x0 0x400>,
		      <0x0 0xd8440000 0x0 0x98>,
		      <0x0 0xc0000000 0x0 0x4280>,
		      <0x0 0xf0610000 0x0 0x20>;
		      reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc", "apbc2";
		      #reset-cells = <1>;
		      status = "disabled";
	};

Kernel's version,

	syscon_apmu: system-controller@d4282800 {
		compatible = "spacemit,k1-syscon-apmu";
		reg = <0x0 0xd4282800 0x0 0x400>;
		clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
			 <&vctcxo_24m>;
		clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
			 "vctcxo_24m";
		#clock-cells = <1>;
		#power-domain-cells = <1>;
		#reset-cells = <1>;
	};

	(and many other independent system-controller nodes, each for a
	 distinct MMIO region)

I suspect we have to deal with the difference before switching to
upstream devicetree, since I2C controllers introduced in this series
do depend on resets.

Regards,
Yao Zi

Re: [PATCH 04/16] dts: k1: import pinctrl dts file from upstream folder

[Heinrich Schuchardt]

Am 30. April 2026 03:26:38 MESZ schrieb Yao Zi <me@ziyao.cc>:
>On Wed, Apr 29, 2026 at 08:48:39PM +0100, Conor Dooley wrote:
>> On Wed, Apr 22, 2026 at 10:31:00AM -0400, Raymond Mao wrote:
>> > From: Raymond Mao <raymond.mao@riscstar.com>
>> > 
>> > Import k1-pinctrl.dtsi from upstream folder.
>> 
>> Why doesn't the platform just use the upstream dts directly?
>
>AFAIK, U-Boot's reset driver for SpacemiT K1 predates land of the
>kernel side driver, and follows a complete different (and to me,
>broken since it combines completely unrelated MMIO regions) ABI.

Shouldn't we first correct the reset drivers and switch to the upstream kernel device-tree before adding anything new? - This would reduce future rework.

Best regards

Heinrich




>
>U-Boot's version,
>
>	reset: reset-controller@d4050000 {
>		compatible = "spacemit,k1-reset";
>		reg = <0x0 0xd4050000 0x0 0x209c>,
>		      <0x0 0xd4282800 0x0 0x400>,
>		      <0x0 0xd4015000 0x0 0x1000>,
>		      <0x0 0xd4090000 0x0 0x1000>,
>		      <0x0 0xd4282c00 0x0 0x400>,
>		      <0x0 0xd8440000 0x0 0x98>,
>		      <0x0 0xc0000000 0x0 0x4280>,
>		      <0x0 0xf0610000 0x0 0x20>;
>		      reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc", "apbc2";
>		      #reset-cells = <1>;
>		      status = "disabled";
>	};
>
>Kernel's version,
>
>	syscon_apmu: system-controller@d4282800 {
>		compatible = "spacemit,k1-syscon-apmu";
>		reg = <0x0 0xd4282800 0x0 0x400>;
>		clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
>			 <&vctcxo_24m>;
>		clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
>			 "vctcxo_24m";
>		#clock-cells = <1>;
>		#power-domain-cells = <1>;
>		#reset-cells = <1>;
>	};
>
>	(and many other independent system-controller nodes, each for a
>	 distinct MMIO region)
>
>I suspect we have to deal with the difference before switching to
>upstream devicetree, since I2C controllers introduced in this series
>do depend on resets.
>
>Regards,
>Yao Zi

Re: [PATCH 04/16] dts: k1: import pinctrl dts file from upstream folder

[Tom Rini]

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On Thu, Apr 30, 2026 at 07:21:58AM +0200, Heinrich Schuchardt wrote:
> Am 30. April 2026 03:26:38 MESZ schrieb Yao Zi <me@ziyao.cc>:
> >On Wed, Apr 29, 2026 at 08:48:39PM +0100, Conor Dooley wrote:
> >> On Wed, Apr 22, 2026 at 10:31:00AM -0400, Raymond Mao wrote:
> >> > From: Raymond Mao <raymond.mao@riscstar.com>
> >> > 
> >> > Import k1-pinctrl.dtsi from upstream folder.
> >> 
> >> Why doesn't the platform just use the upstream dts directly?
> >
> >AFAIK, U-Boot's reset driver for SpacemiT K1 predates land of the
> >kernel side driver, and follows a complete different (and to me,
> >broken since it combines completely unrelated MMIO regions) ABI.
> 
> Shouldn't we first correct the reset drivers and switch to the upstream kernel device-tree before adding anything new? - This would reduce future rework.

Exactly. That's a condition of bringing stuff in to U-Boot before it's
accepted to the kernel. It *must* be updated once the kernel folks have
provided feedback, we do not diverge.

-- 
Tom

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Re: [PATCH 04/16] dts: k1: import pinctrl dts file from upstream folder

[Guodong Xu]

Hi Tom, Conor, Heinrich, Yao Zi,


On Thu, Apr 30, 2026 at 10:33 PM Tom Rini <trini@konsulko.com> wrote:
>
> On Thu, Apr 30, 2026 at 07:21:58AM +0200, Heinrich Schuchardt wrote:
> > Am 30. April 2026 03:26:38 MESZ schrieb Yao Zi <me@ziyao.cc>:
> > >On Wed, Apr 29, 2026 at 08:48:39PM +0100, Conor Dooley wrote:
> > >> On Wed, Apr 22, 2026 at 10:31:00AM -0400, Raymond Mao wrote:
> > >> > From: Raymond Mao <raymond.mao@riscstar.com>
> > >> >
> > >> > Import k1-pinctrl.dtsi from upstream folder.
> > >>
> > >> Why doesn't the platform just use the upstream dts directly?
> > >
> > >AFAIK, U-Boot's reset driver for SpacemiT K1 predates land of the
> > >kernel side driver, and follows a complete different (and to me,
> > >broken since it combines completely unrelated MMIO regions) ABI.
> >
> > Shouldn't we first correct the reset drivers and switch to the upstream kernel device-tree before adding anything new? - This would reduce future rework.
>
> Exactly. That's a condition of bringing stuff in to U-Boot before it's
> accepted to the kernel. It *must* be updated once the kernel folks have
> provided feedback, we do not diverge.
>

Chiming in as one of the K1 platform contributors.

Yao Zi is right about the reset driver. U-Boot's spacemit,k1-reset driver
predates the current kernel binding. The kernel K1 reset driver was reworked
to use the auxiliary-device mechanism during upstream review. At that
point the kernel DTS (arch/riscv/boot/dts/spacemit/k1.dtsi) dropped its
reset-controller node. And it is from there, the K1 uboot and kernel dts/dtsi
files starting to diverge with each other.

To pull them back together, with the goal to reuse the kernel dts,
we plan to:

1. Refactor U-Boot's K1 reset driver to be spawned from each per-syscon
clock driver via device_bind_driver_to_node(), called from the .bind
hook in drivers/clk/spacemit/clk-k1.c. More study is requried but for
now we think this is the correct way. After the refactor, the K1
build should be able to switch dts/upstream/src/riscv/spacemit/, with
a simple U-Boot specifics layered as <board>-u-boot.dtsi overlays.

2. After the refactor, we'll rebase the still in-flight K1 SPL bring-up
work [1] and the PIN/SPI series [2] (this one) on top, dropping
the patches that imported the forked DT, and resend.

Could you confirm this matches your direction? If so, we'll send the
K1 reset driver refactor as a standalone series first.

Link: https://lore.kernel.org/u-boot/20260325223232.1553212-1-raymondmaoca@gmail.com/
[1]
[PATCH v3 00/16] Add board support for Spacemit K1 SoC in SPL

Link: https://lore.kernel.org/u-boot/20260422143112.1329478-1-raymondmaoca@gmail.com/
[2]
[PATCH 00/16] Add PIN and SPI support for Spacemit K1

Thanks,
Guodong

> --
> Tom

Re: [PATCH 04/16] dts: k1: import pinctrl dts file from upstream folder

[Tom Rini]

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On Thu, May 07, 2026 at 07:59:41PM +0800, Guodong Xu wrote:
> Hi Tom, Conor, Heinrich, Yao Zi,
> 
> 
> On Thu, Apr 30, 2026 at 10:33 PM Tom Rini <trini@konsulko.com> wrote:
> >
> > On Thu, Apr 30, 2026 at 07:21:58AM +0200, Heinrich Schuchardt wrote:
> > > Am 30. April 2026 03:26:38 MESZ schrieb Yao Zi <me@ziyao.cc>:
> > > >On Wed, Apr 29, 2026 at 08:48:39PM +0100, Conor Dooley wrote:
> > > >> On Wed, Apr 22, 2026 at 10:31:00AM -0400, Raymond Mao wrote:
> > > >> > From: Raymond Mao <raymond.mao@riscstar.com>
> > > >> >
> > > >> > Import k1-pinctrl.dtsi from upstream folder.
> > > >>
> > > >> Why doesn't the platform just use the upstream dts directly?
> > > >
> > > >AFAIK, U-Boot's reset driver for SpacemiT K1 predates land of the
> > > >kernel side driver, and follows a complete different (and to me,
> > > >broken since it combines completely unrelated MMIO regions) ABI.
> > >
> > > Shouldn't we first correct the reset drivers and switch to the upstream kernel device-tree before adding anything new? - This would reduce future rework.
> >
> > Exactly. That's a condition of bringing stuff in to U-Boot before it's
> > accepted to the kernel. It *must* be updated once the kernel folks have
> > provided feedback, we do not diverge.
> >
> 
> Chiming in as one of the K1 platform contributors.
> 
> Yao Zi is right about the reset driver. U-Boot's spacemit,k1-reset driver
> predates the current kernel binding. The kernel K1 reset driver was reworked
> to use the auxiliary-device mechanism during upstream review. At that
> point the kernel DTS (arch/riscv/boot/dts/spacemit/k1.dtsi) dropped its
> reset-controller node. And it is from there, the K1 uboot and kernel dts/dtsi
> files starting to diverge with each other.
> 
> To pull them back together, with the goal to reuse the kernel dts,
> we plan to:
> 
> 1. Refactor U-Boot's K1 reset driver to be spawned from each per-syscon
> clock driver via device_bind_driver_to_node(), called from the .bind
> hook in drivers/clk/spacemit/clk-k1.c. More study is requried but for
> now we think this is the correct way. After the refactor, the K1
> build should be able to switch dts/upstream/src/riscv/spacemit/, with
> a simple U-Boot specifics layered as <board>-u-boot.dtsi overlays.
> 
> 2. After the refactor, we'll rebase the still in-flight K1 SPL bring-up
> work [1] and the PIN/SPI series [2] (this one) on top, dropping
> the patches that imported the forked DT, and resend.
> 
> Could you confirm this matches your direction? If so, we'll send the
> K1 reset driver refactor as a standalone series first.
> 
> Link: https://lore.kernel.org/u-boot/20260325223232.1553212-1-raymondmaoca@gmail.com/
> [1]
> [PATCH v3 00/16] Add board support for Spacemit K1 SoC in SPL
> 
> Link: https://lore.kernel.org/u-boot/20260422143112.1329478-1-raymondmaoca@gmail.com/
> [2]
> [PATCH 00/16] Add PIN and SPI support for Spacemit K1

From my point of view, yes, whatever is needed such that we can use the
upstream bindings again makes sense and I'll defer to you about how is
best given the SoC design. Thanks!

-- 
Tom

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