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From: Vinod Koul <vkoul@kernel.org>
To: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Cc: Neil Armstrong <neil.armstrong@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Algea Cao <algea.cao@rock-chips.com>,
	Dmitry Baryshkov <lumag@kernel.org>,
	kernel@collabora.com, linux-phy@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups
Date: Mon, 11 May 2026 21:48:51 +0530	[thread overview]
Message-ID: <agIBa7qxIGgqCYZ1@vaman> (raw)
In-Reply-To: <c76d7020-2b3b-4f30-ab40-a8442c953966@collabora.com>

On 10-05-26, 11:55, Cristian Ciocaltea wrote:
> Hi Vinod,
> 
> On 5/10/26 10:36 AM, Vinod Koul wrote:
> > On 27-02-26, 22:48, Cristian Ciocaltea wrote:
> >> This series provides a set of bug fixes and cleanups for the Rockchip
> >> Samsung HDPTX PHY driver.
> >>
> >> The first part of the series (i.e. PATCH 1 & 2) addresses clock rate
> >> calculation and synchronization issues.  Specifically, it fixes edge
> >> cases where the PHY PLL is pre-programmed by an external component (like
> >> a bootloader) or when changing the color depth (bpc) while keeping the
> >> modeline constant.  Because the Common Clock Framework .set_rate()
> >> callback might not be invoked if the pixel clock remains unchanged, this
> >> previously led to out-of-sync states between CCF and the actual HDMI PHY
> >> configuration.
> >>
> >> The second part focuses on code cleanups and modernizing the register
> >> access.  Now that dw_hdmi_qp driver has fully switched to using
> >> phy_configure(), we can drop the deprecated TMDS rate setup workarounds
> >> and the restrict_rate_change flag logic.  Finally, it refactors the
> >> driver to consistently use standard bitfield macros.
> > 
> > Sorry looks like I have missed to review this one.
> > Can you please rebase on phy/fixes and send...
> 
> I've just verified and it applies cleanly on top of phy/fixes.
> Do you still need a resend?

Yes please, it didnt apply for me

-- 
~Vinod

WARNING: multiple messages have this Message-ID (diff)
From: Vinod Koul <vkoul@kernel.org>
To: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Cc: Neil Armstrong <neil.armstrong@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Algea Cao <algea.cao@rock-chips.com>,
	Dmitry Baryshkov <lumag@kernel.org>,
	kernel@collabora.com, linux-phy@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups
Date: Mon, 11 May 2026 21:48:51 +0530	[thread overview]
Message-ID: <agIBa7qxIGgqCYZ1@vaman> (raw)
In-Reply-To: <c76d7020-2b3b-4f30-ab40-a8442c953966@collabora.com>

On 10-05-26, 11:55, Cristian Ciocaltea wrote:
> Hi Vinod,
> 
> On 5/10/26 10:36 AM, Vinod Koul wrote:
> > On 27-02-26, 22:48, Cristian Ciocaltea wrote:
> >> This series provides a set of bug fixes and cleanups for the Rockchip
> >> Samsung HDPTX PHY driver.
> >>
> >> The first part of the series (i.e. PATCH 1 & 2) addresses clock rate
> >> calculation and synchronization issues.  Specifically, it fixes edge
> >> cases where the PHY PLL is pre-programmed by an external component (like
> >> a bootloader) or when changing the color depth (bpc) while keeping the
> >> modeline constant.  Because the Common Clock Framework .set_rate()
> >> callback might not be invoked if the pixel clock remains unchanged, this
> >> previously led to out-of-sync states between CCF and the actual HDMI PHY
> >> configuration.
> >>
> >> The second part focuses on code cleanups and modernizing the register
> >> access.  Now that dw_hdmi_qp driver has fully switched to using
> >> phy_configure(), we can drop the deprecated TMDS rate setup workarounds
> >> and the restrict_rate_change flag logic.  Finally, it refactors the
> >> driver to consistently use standard bitfield macros.
> > 
> > Sorry looks like I have missed to review this one.
> > Can you please rebase on phy/fixes and send...
> 
> I've just verified and it applies cleanly on top of phy/fixes.
> Do you still need a resend?

Yes please, it didnt apply for me

-- 
~Vinod

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: Vinod Koul <vkoul@kernel.org>
To: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Cc: Neil Armstrong <neil.armstrong@linaro.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Algea Cao <algea.cao@rock-chips.com>,
	Dmitry Baryshkov <lumag@kernel.org>,
	kernel@collabora.com, linux-phy@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups
Date: Mon, 11 May 2026 21:48:51 +0530	[thread overview]
Message-ID: <agIBa7qxIGgqCYZ1@vaman> (raw)
In-Reply-To: <c76d7020-2b3b-4f30-ab40-a8442c953966@collabora.com>

On 10-05-26, 11:55, Cristian Ciocaltea wrote:
> Hi Vinod,
> 
> On 5/10/26 10:36 AM, Vinod Koul wrote:
> > On 27-02-26, 22:48, Cristian Ciocaltea wrote:
> >> This series provides a set of bug fixes and cleanups for the Rockchip
> >> Samsung HDPTX PHY driver.
> >>
> >> The first part of the series (i.e. PATCH 1 & 2) addresses clock rate
> >> calculation and synchronization issues.  Specifically, it fixes edge
> >> cases where the PHY PLL is pre-programmed by an external component (like
> >> a bootloader) or when changing the color depth (bpc) while keeping the
> >> modeline constant.  Because the Common Clock Framework .set_rate()
> >> callback might not be invoked if the pixel clock remains unchanged, this
> >> previously led to out-of-sync states between CCF and the actual HDMI PHY
> >> configuration.
> >>
> >> The second part focuses on code cleanups and modernizing the register
> >> access.  Now that dw_hdmi_qp driver has fully switched to using
> >> phy_configure(), we can drop the deprecated TMDS rate setup workarounds
> >> and the restrict_rate_change flag logic.  Finally, it refactors the
> >> driver to consistently use standard bitfield macros.
> > 
> > Sorry looks like I have missed to review this one.
> > Can you please rebase on phy/fixes and send...
> 
> I've just verified and it applies cleanly on top of phy/fixes.
> Do you still need a resend?

Yes please, it didnt apply for me

-- 
~Vinod

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

  reply	other threads:[~2026-05-11 16:18 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-27 20:48 [PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups Cristian Ciocaltea
2026-02-27 20:48 ` Cristian Ciocaltea
2026-02-27 20:48 ` Cristian Ciocaltea
2026-02-27 20:48 ` [PATCH 1/6] phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc Cristian Ciocaltea
2026-02-27 20:48   ` Cristian Ciocaltea
2026-02-27 20:48   ` Cristian Ciocaltea
2026-02-27 20:48 ` [PATCH 2/6] phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes Cristian Ciocaltea
2026-02-27 20:48   ` Cristian Ciocaltea
2026-02-27 20:48   ` Cristian Ciocaltea
2026-02-27 20:48 ` [PATCH 3/6] phy: rockchip: samsung-hdptx: Drop TMDS rate setup workaround Cristian Ciocaltea
2026-02-27 20:48   ` Cristian Ciocaltea
2026-02-27 20:48   ` Cristian Ciocaltea
2026-02-27 20:48 ` [PATCH 4/6] phy: rockchip: samsung-hdptx: Drop restrict_rate_change handling Cristian Ciocaltea
2026-02-27 20:48   ` Cristian Ciocaltea
2026-02-27 20:48   ` Cristian Ciocaltea
2026-02-27 20:48 ` [PATCH 5/6] phy: rockchip: samsung-hdptx: Simplify GRF access with FIELD_PREP_WM16() Cristian Ciocaltea
2026-02-27 20:48   ` Cristian Ciocaltea
2026-02-27 20:48   ` Cristian Ciocaltea
2026-02-27 20:48 ` [PATCH 6/6] phy: rockchip: samsung-hdptx: Consistently use bitfield macros Cristian Ciocaltea
2026-02-27 20:48   ` Cristian Ciocaltea
2026-02-27 20:48   ` Cristian Ciocaltea
2026-03-02 19:46 ` [PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups 1und1
2026-03-02 19:46   ` 1und1
2026-03-02 19:46   ` 1und1
2026-03-02 20:25   ` Cristian Ciocaltea
2026-03-02 20:25     ` Cristian Ciocaltea
2026-03-02 20:25     ` Cristian Ciocaltea
2026-05-08  9:03 ` Simon Wright
2026-05-08  9:03   ` Simon Wright
2026-05-08  9:03   ` Simon Wright
2026-05-10  7:36 ` Vinod Koul
2026-05-10  7:36   ` Vinod Koul
2026-05-10  7:36   ` Vinod Koul
2026-05-10  8:55   ` Cristian Ciocaltea
2026-05-10  8:55     ` Cristian Ciocaltea
2026-05-10  8:55     ` Cristian Ciocaltea
2026-05-11 16:18     ` Vinod Koul [this message]
2026-05-11 16:18       ` Vinod Koul
2026-05-11 16:18       ` Vinod Koul
2026-05-11 18:31       ` Cristian Ciocaltea
2026-05-11 18:31         ` Cristian Ciocaltea
2026-05-11 18:31         ` Cristian Ciocaltea

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