From: Kuan-Wei Chiu <visitorckw@gmail.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: pbonzini@redhat.com, marcandre.lureau@redhat.com,
palmer@dabbelt.com, alistair.francis@wdc.com,
christoph.muellner@vrull.eu, liwei1518@gmail.com,
daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com,
chao.liu.zevorn@gmail.com, jserv@ccns.ncku.edu.tw,
eleanor15x@gmail.com, qemu-devel@nongnu.org,
qemu-riscv@nongnu.org
Subject: Re: [PATCH RFC 1/5] target/riscv: Add stubs for T-Head PMU CSRs
Date: Wed, 13 May 2026 22:49:55 +0800 [thread overview]
Message-ID: <agSPk3idcDVPg8kH@google.com> (raw)
In-Reply-To: <CAKmqyKPpKPOgpKuY9wcyShzXw1y5vVgyT6Lx2f7Jhs8cqzZD0Q@mail.gmail.com>
On Wed, May 13, 2026 at 12:13:25PM +1000, Alistair Francis wrote:
> On Tue, May 12, 2026 at 7:47 PM Kuan-Wei Chiu <visitorckw@gmail.com> wrote:
> >
> > T-Head CPUs use custom CSRs for performance monitoring, specifically
> > mcounterinten (0x7ca) and mcounterof (0x7cb).
> >
> > Since we don't implement these custom PMU registers yet, the system
> > crashes with an illegal instruction trap when OpenSBI like this:
> >
> > system_opcode_insn: Failed to access CSR 0x7ca from M-mode
> > sbi_trap_error: hart0: trap1: illegal instruction handler failed (error -1)
> >
> > Add simple read/write stubs for these two CSRs. By silently ignoring
> > writes and returning 0 on reads, we prevent the fatal exceptions and
> > allow to continue normally.
>
> Can you include a link to the documentation for the CSRs
>
Sure.
I'll add the link in v2.
Regards,
Kuan-Wei
next prev parent reply other threads:[~2026-05-13 14:50 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-12 9:46 [PATCH RFC 0/5] hw/riscv: Add support for Milk-V Duo board Kuan-Wei Chiu
2026-05-12 9:46 ` [PATCH RFC 1/5] target/riscv: Add stubs for T-Head PMU CSRs Kuan-Wei Chiu
2026-05-13 2:13 ` Alistair Francis
2026-05-13 14:49 ` Kuan-Wei Chiu [this message]
2026-05-12 9:46 ` [PATCH RFC 2/5] hw/char: Add dw8250 UART Kuan-Wei Chiu
2026-05-12 9:46 ` [PATCH RFC 3/5] hw/misc: Add Sophgo CV1800B clock controller Kuan-Wei Chiu
2026-05-12 9:46 ` [PATCH RFC 4/5] hw/riscv: Add Sophgo CV1800B SoC support Kuan-Wei Chiu
2026-05-12 9:46 ` [PATCH RFC 5/5] hw/riscv: Add Milk-V Duo board support Kuan-Wei Chiu
2026-05-13 2:27 ` [PATCH RFC 0/5] hw/riscv: Add support for Milk-V Duo board Alistair Francis
2026-05-13 14:56 ` Kuan-Wei Chiu
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