* [PATCH v4 01/15] accel/mshv: move msr.c to target/i386
2026-05-27 5:00 [PATCH v4 00/15] Add ARM64 support for MSHV accelerator Aastha Rawat
@ 2026-05-27 5:00 ` Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 02/15] accel/mshv: extract common CPU register helpers Aastha Rawat
` (13 subsequent siblings)
14 siblings, 0 replies; 17+ messages in thread
From: Aastha Rawat @ 2026-05-27 5:00 UTC (permalink / raw)
To: qemu-devel
Cc: Magnus Kulke, Wei Liu, Paolo Bonzini, Marc-André Lureau,
Daniel P. Berrangé, Philippe Mathieu-Daudé,
Peter Maydell, Anirudh Rayabharam, Aastha Rawat, qemu-arm,
Alexander Graf, Pedro Barbuda, Mohamed Mediouni,
Doru Blânzeanu, Pierrick Bouvier, Magnus Kulke
This file has x86 specific implementations. Move this file to i386
folder in preparation for ARM64 MSHV support.
Signed-off-by: Aastha Rawat <aastharawat@linux.microsoft.com>
Acked-by: Wei Liu <wei.liu@kernel.org>
Reviewed-by: Mohamed Mediouni <mohamed@unpredictable.fr>
---
accel/mshv/meson.build | 1 -
target/i386/mshv/meson.build | 1 +
{accel => target/i386}/mshv/msr.c | 0
3 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/mshv/meson.build b/accel/mshv/meson.build
index c1b1787c5e..e433187cde 100644
--- a/accel/mshv/meson.build
+++ b/accel/mshv/meson.build
@@ -1,6 +1,5 @@
system_ss.add(when: 'CONFIG_MSHV', if_true: files(
'irq.c',
'mem.c',
- 'msr.c',
'mshv-all.c'
))
diff --git a/target/i386/mshv/meson.build b/target/i386/mshv/meson.build
index 49f28d4a5b..6091c21887 100644
--- a/target/i386/mshv/meson.build
+++ b/target/i386/mshv/meson.build
@@ -2,6 +2,7 @@ i386_mshv_ss = ss.source_set()
i386_mshv_ss.add(files(
'mshv-cpu.c',
+ 'msr.c',
))
i386_system_ss.add_all(when: 'CONFIG_MSHV', if_true: i386_mshv_ss)
diff --git a/accel/mshv/msr.c b/target/i386/mshv/msr.c
similarity index 100%
rename from accel/mshv/msr.c
rename to target/i386/mshv/msr.c
--
2.45.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 02/15] accel/mshv: extract common CPU register helpers
2026-05-27 5:00 [PATCH v4 00/15] Add ARM64 support for MSHV accelerator Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 01/15] accel/mshv: move msr.c to target/i386 Aastha Rawat
@ 2026-05-27 5:00 ` Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 03/15] accel/mshv: add arch-specific accelerator init hook Aastha Rawat
` (12 subsequent siblings)
14 siblings, 0 replies; 17+ messages in thread
From: Aastha Rawat @ 2026-05-27 5:00 UTC (permalink / raw)
To: qemu-devel
Cc: Magnus Kulke, Wei Liu, Paolo Bonzini, Marc-André Lureau,
Daniel P. Berrangé, Philippe Mathieu-Daudé,
Peter Maydell, Anirudh Rayabharam, Aastha Rawat, qemu-arm,
Alexander Graf, Pedro Barbuda, Mohamed Mediouni,
Doru Blânzeanu, Pierrick Bouvier, Magnus Kulke
Move arch-independent MSHV CPU register handling functions into
accel/mshv/mshv-cpu-common.c. Update x86 MSHV backends to use these
shared helpers.
Prefix get_generic_regs() with mshv_ for proper namespacing since it
is now public.
Signed-off-by: Aastha Rawat <aastharawat@linux.microsoft.com>
---
accel/mshv/meson.build | 3 +-
accel/mshv/mshv-cpu-common.c | 151 +++++++++++++++++++++++++++++++++++++++++++
include/system/mshv_int.h | 3 +
target/i386/mshv/mshv-cpu.c | 130 +------------------------------------
4 files changed, 159 insertions(+), 128 deletions(-)
diff --git a/accel/mshv/meson.build b/accel/mshv/meson.build
index e433187cde..ebe32921b3 100644
--- a/accel/mshv/meson.build
+++ b/accel/mshv/meson.build
@@ -1,5 +1,6 @@
system_ss.add(when: 'CONFIG_MSHV', if_true: files(
'irq.c',
'mem.c',
- 'mshv-all.c'
+ 'mshv-all.c',
+ 'mshv-cpu-common.c'
))
diff --git a/accel/mshv/mshv-cpu-common.c b/accel/mshv/mshv-cpu-common.c
new file mode 100644
index 0000000000..b104720161
--- /dev/null
+++ b/accel/mshv/mshv-cpu-common.c
@@ -0,0 +1,151 @@
+/*
+ * QEMU MSHV common CPU register helpers
+ *
+ * Copyright Microsoft, Corp. 2026
+ *
+ * Authors: Ziqiao Zhou <ziqiaozhou@microsoft.com>
+ * Magnus Kulke <magnuskulke@microsoft.com>
+ * Jinank Jain <jinankjain@microsoft.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/memalign.h"
+
+#include "system/mshv.h"
+#include "system/mshv_int.h"
+
+#include "hw/core/cpu.h"
+#include "linux/mshv.h"
+
+#include <sys/ioctl.h>
+
+int mshv_set_generic_regs(const CPUState *cpu, const hv_register_assoc *assocs,
+ size_t n_regs)
+{
+ int cpu_fd = mshv_vcpufd(cpu);
+ int vp_index = cpu->cpu_index;
+ size_t in_sz, assocs_sz;
+ hv_input_set_vp_registers *in = cpu->accel->hvcall_args.input_page;
+ struct mshv_root_hvcall args = {0};
+ int ret;
+
+ /* find out the size of the struct w/ a flexible array at the tail */
+ assocs_sz = n_regs * sizeof(hv_register_assoc);
+ in_sz = sizeof(hv_input_set_vp_registers) + assocs_sz;
+
+ /* fill the input struct */
+ memset(in, 0, sizeof(hv_input_set_vp_registers));
+ in->vp_index = vp_index;
+ memcpy(in->elements, assocs, assocs_sz);
+
+ /* create the hvcall envelope */
+ args.code = HVCALL_SET_VP_REGISTERS;
+ args.in_sz = in_sz;
+ args.in_ptr = (uint64_t) in;
+ args.reps = (uint16_t) n_regs;
+
+ /* perform the call */
+ ret = mshv_hvcall(cpu_fd, &args);
+ if (ret < 0) {
+ error_report("Failed to set registers");
+ return -1;
+ }
+
+ /* assert we set all registers */
+ if (args.reps != n_regs) {
+ error_report("Failed to set registers: expected %zu elements"
+ ", got %u", n_regs, args.reps);
+ return -1;
+ }
+
+ return 0;
+}
+
+int mshv_get_generic_regs(CPUState *cpu, hv_register_assoc *assocs,
+ size_t n_regs)
+{
+ int cpu_fd = mshv_vcpufd(cpu);
+ int vp_index = cpu->cpu_index;
+ hv_input_get_vp_registers *in = cpu->accel->hvcall_args.input_page;
+ hv_register_value *values = cpu->accel->hvcall_args.output_page;
+ size_t in_sz, names_sz, values_sz;
+ int i, ret;
+ struct mshv_root_hvcall args = {0};
+
+ /* find out the size of the struct w/ a flexible array at the tail */
+ names_sz = n_regs * sizeof(hv_register_name);
+ in_sz = sizeof(hv_input_get_vp_registers) + names_sz;
+
+ /* fill the input struct */
+ memset(in, 0, sizeof(hv_input_get_vp_registers));
+ in->vp_index = vp_index;
+ for (i = 0; i < n_regs; i++) {
+ in->names[i] = assocs[i].name;
+ }
+
+ /* determine size of value output buffer */
+ values_sz = n_regs * sizeof(union hv_register_value);
+
+ /* create the hvcall envelope */
+ args.code = HVCALL_GET_VP_REGISTERS;
+ args.in_sz = in_sz;
+ args.in_ptr = (uint64_t) in;
+ args.out_sz = values_sz;
+ args.out_ptr = (uint64_t) values;
+ args.reps = (uint16_t) n_regs;
+
+ /* perform the call */
+ ret = mshv_hvcall(cpu_fd, &args);
+ if (ret < 0) {
+ error_report("Failed to retrieve registers");
+ return -1;
+ }
+
+ /* assert we got all registers */
+ if (args.reps != n_regs) {
+ error_report("Failed to retrieve registers: expected %zu elements"
+ ", got %u", n_regs, args.reps);
+ return -1;
+ }
+
+ /* copy values into assoc */
+ for (i = 0; i < n_regs; i++) {
+ assocs[i].value = values[i];
+ }
+
+ return 0;
+}
+
+int mshv_create_vcpu(int vm_fd, uint8_t vp_index, int *cpu_fd)
+{
+ int ret;
+ struct mshv_create_vp vp_arg = {
+ .vp_index = vp_index,
+ };
+
+ ret = ioctl(vm_fd, MSHV_CREATE_VP, &vp_arg);
+ if (ret < 0) {
+ error_report("failed to create mshv vcpu: %s", strerror(errno));
+ return -1;
+ }
+
+ *cpu_fd = ret;
+
+ return 0;
+}
+
+void mshv_remove_vcpu(int vm_fd, int cpu_fd)
+{
+ close(cpu_fd);
+}
+
+void mshv_setup_hvcall_args(AccelCPUState *state)
+{
+ void *mem = qemu_memalign(HV_HYP_PAGE_SIZE, 2 * HV_HYP_PAGE_SIZE);
+
+ state->hvcall_args.base = mem;
+ state->hvcall_args.input_page = mem;
+ state->hvcall_args.output_page = (uint8_t *)mem + HV_HYP_PAGE_SIZE;
+}
diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h
index 35386c422f..ff3ab957b5 100644
--- a/include/system/mshv_int.h
+++ b/include/system/mshv_int.h
@@ -89,12 +89,15 @@ int mshv_load_regs(CPUState *cpu);
int mshv_store_regs(CPUState *cpu);
int mshv_set_generic_regs(const CPUState *cpu, const hv_register_assoc *assocs,
size_t n_regs);
+int mshv_get_generic_regs(CPUState *cpu, hv_register_assoc *assocs,
+ size_t n_regs);
int mshv_arch_put_registers(const CPUState *cpu);
void mshv_arch_init_vcpu(CPUState *cpu);
void mshv_arch_destroy_vcpu(CPUState *cpu);
void mshv_arch_amend_proc_features(
union hv_partition_synthetic_processor_features *features);
int mshv_arch_post_init_vm(int vm_fd);
+void mshv_setup_hvcall_args(AccelCPUState *state);
typedef struct mshv_root_hvcall mshv_root_hvcall;
int mshv_hvcall(int fd, const mshv_root_hvcall *args);
diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c
index 4ed6e7548f..e1df5e8a17 100644
--- a/target/i386/mshv/mshv-cpu.c
+++ b/target/i386/mshv/mshv-cpu.c
@@ -148,103 +148,6 @@ static int translate_gva(const CPUState *cpu, uint64_t gva, uint64_t *gpa,
return 0;
}
-int mshv_set_generic_regs(const CPUState *cpu, const hv_register_assoc *assocs,
- size_t n_regs)
-{
- int cpu_fd = mshv_vcpufd(cpu);
- int vp_index = cpu->cpu_index;
- size_t in_sz, assocs_sz;
- hv_input_set_vp_registers *in = cpu->accel->hvcall_args.input_page;
- struct mshv_root_hvcall args = {0};
- int ret;
-
- /* find out the size of the struct w/ a flexible array at the tail */
- assocs_sz = n_regs * sizeof(hv_register_assoc);
- in_sz = sizeof(hv_input_set_vp_registers) + assocs_sz;
-
- /* fill the input struct */
- memset(in, 0, sizeof(hv_input_set_vp_registers));
- in->vp_index = vp_index;
- memcpy(in->elements, assocs, assocs_sz);
-
- /* create the hvcall envelope */
- args.code = HVCALL_SET_VP_REGISTERS;
- args.in_sz = in_sz;
- args.in_ptr = (uint64_t) in;
- args.reps = (uint16_t) n_regs;
-
- /* perform the call */
- ret = mshv_hvcall(cpu_fd, &args);
- if (ret < 0) {
- error_report("Failed to set registers");
- return -1;
- }
-
- /* assert we set all registers */
- if (args.reps != n_regs) {
- error_report("Failed to set registers: expected %zu elements"
- ", got %u", n_regs, args.reps);
- return -1;
- }
-
- return 0;
-}
-
-static int get_generic_regs(CPUState *cpu, hv_register_assoc *assocs,
- size_t n_regs)
-{
- int cpu_fd = mshv_vcpufd(cpu);
- int vp_index = cpu->cpu_index;
- hv_input_get_vp_registers *in = cpu->accel->hvcall_args.input_page;
- hv_register_value *values = cpu->accel->hvcall_args.output_page;
- size_t in_sz, names_sz, values_sz;
- int i, ret;
- struct mshv_root_hvcall args = {0};
-
- /* find out the size of the struct w/ a flexible array at the tail */
- names_sz = n_regs * sizeof(hv_register_name);
- in_sz = sizeof(hv_input_get_vp_registers) + names_sz;
-
- /* fill the input struct */
- memset(in, 0, sizeof(hv_input_get_vp_registers));
- in->vp_index = vp_index;
- for (i = 0; i < n_regs; i++) {
- in->names[i] = assocs[i].name;
- }
-
- /* determine size of value output buffer */
- values_sz = n_regs * sizeof(union hv_register_value);
-
- /* create the hvcall envelope */
- args.code = HVCALL_GET_VP_REGISTERS;
- args.in_sz = in_sz;
- args.in_ptr = (uint64_t) in;
- args.out_sz = values_sz;
- args.out_ptr = (uint64_t) values;
- args.reps = (uint16_t) n_regs;
-
- /* perform the call */
- ret = mshv_hvcall(cpu_fd, &args);
- if (ret < 0) {
- error_report("Failed to retrieve registers");
- return -1;
- }
-
- /* assert we got all registers */
- if (args.reps != n_regs) {
- error_report("Failed to retrieve registers: expected %zu elements"
- ", got %u", n_regs, args.reps);
- return -1;
- }
-
- /* copy values into assoc */
- for (i = 0; i < n_regs; i++) {
- assocs[i].value = values[i];
- }
-
- return 0;
-}
-
static int set_standard_regs(const CPUState *cpu)
{
X86CPU *x86cpu = X86_CPU(cpu);
@@ -334,7 +237,7 @@ int mshv_get_standard_regs(CPUState *cpu)
for (size_t i = 0; i < n_regs; i++) {
assocs[i].name = STANDARD_REGISTER_NAMES[i];
}
- ret = get_generic_regs(cpu, assocs, n_regs);
+ ret = mshv_get_generic_regs(cpu, assocs, n_regs);
if (ret < 0) {
error_report("failed to get standard registers");
return -1;
@@ -412,7 +315,7 @@ int mshv_get_special_regs(CPUState *cpu)
for (size_t i = 0; i < n_regs; i++) {
assocs[i].name = SPECIAL_REGISTER_NAMES[i];
}
- ret = get_generic_regs(cpu, assocs, n_regs);
+ ret = mshv_get_generic_regs(cpu, assocs, n_regs);
if (ret < 0) {
error_report("failed to get special registers");
return -errno;
@@ -1525,29 +1428,6 @@ int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *exit)
return 0;
}
-void mshv_remove_vcpu(int vm_fd, int cpu_fd)
-{
- close(cpu_fd);
-}
-
-
-int mshv_create_vcpu(int vm_fd, uint8_t vp_index, int *cpu_fd)
-{
- int ret;
- struct mshv_create_vp vp_arg = {
- .vp_index = vp_index,
- };
- ret = ioctl(vm_fd, MSHV_CREATE_VP, &vp_arg);
- if (ret < 0) {
- error_report("failed to create mshv vcpu: %s", strerror(errno));
- return -1;
- }
-
- *cpu_fd = ret;
-
- return 0;
-}
-
static void read_segment_descriptor(CPUState *cpu,
struct x86_segment_descriptor *desc,
enum X86Seg seg_idx)
@@ -1605,8 +1485,6 @@ void mshv_arch_init_vcpu(CPUState *cpu)
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
AccelCPUState *state = cpu->accel;
- size_t page = HV_HYP_PAGE_SIZE;
- void *mem = qemu_memalign(page, 2 * page);
/* sanity check, to make sure we don't overflow the page */
QEMU_BUILD_BUG_ON((MAX_REGISTER_COUNT
@@ -1614,9 +1492,7 @@ void mshv_arch_init_vcpu(CPUState *cpu)
+ sizeof(hv_input_get_vp_registers)
> HV_HYP_PAGE_SIZE));
- state->hvcall_args.base = mem;
- state->hvcall_args.input_page = mem;
- state->hvcall_args.output_page = (uint8_t *)mem + page;
+ mshv_setup_hvcall_args(state);
env->emu_mmio_buf = g_new(char, 4096);
}
--
2.45.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 03/15] accel/mshv: add arch-specific accelerator init hook
2026-05-27 5:00 [PATCH v4 00/15] Add ARM64 support for MSHV accelerator Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 01/15] accel/mshv: move msr.c to target/i386 Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 02/15] accel/mshv: extract common CPU register helpers Aastha Rawat
@ 2026-05-27 5:00 ` Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 04/15] meson, target/arm/mshv: Enable arm64 build & add initial MSHV support Aastha Rawat
` (11 subsequent siblings)
14 siblings, 0 replies; 17+ messages in thread
From: Aastha Rawat @ 2026-05-27 5:00 UTC (permalink / raw)
To: qemu-devel
Cc: Magnus Kulke, Wei Liu, Paolo Bonzini, Marc-André Lureau,
Daniel P. Berrangé, Philippe Mathieu-Daudé,
Peter Maydell, Anirudh Rayabharam, Aastha Rawat, qemu-arm,
Alexander Graf, Pedro Barbuda, Mohamed Mediouni,
Doru Blânzeanu, Pierrick Bouvier, Magnus Kulke
From: "Anirudh Rayabharam (Microsoft)" <anirudh@anirudhrb.com>
Introduce mshv_arch_accel_init() as an arch-specific hook called early
in mshv_init(), before VM creation. This allows each architecture to
perform platform-specific initialization at accelerator init time.
For x86, the hook calls mshv_init_mmio_emu() which was previously called
directly from the common init path. Also move set_unimplemented_msr_action()
and mshv_arch_post_init_vm() from mshv-cpu.c to the new mshv-all.c, as
they are not vCPU-specific.
Signed-off-by: Anirudh Rayabharam (Microsoft) <anirudh@anirudhrb.com>
---
accel/mshv/mshv-all.c | 5 ++-
include/system/mshv_int.h | 1 +
target/i386/mshv/meson.build | 1 +
target/i386/mshv/mshv-all.c | 80 ++++++++++++++++++++++++++++++++++++++++++++
target/i386/mshv/mshv-cpu.c | 40 ----------------------
5 files changed, 86 insertions(+), 41 deletions(-)
diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c
index 58af674bd9..65095798e2 100644
--- a/accel/mshv/mshv-all.c
+++ b/accel/mshv/mshv-all.c
@@ -448,7 +448,10 @@ static int mshv_init(AccelState *as, MachineState *ms)
return -1;
}
- mshv_init_mmio_emu();
+ ret = mshv_arch_accel_init(as, ms, mshv_fd);
+ if (ret < 0) {
+ return -1;
+ }
mshv_init_msicontrol();
diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h
index ff3ab957b5..c72c91cd23 100644
--- a/include/system/mshv_int.h
+++ b/include/system/mshv_int.h
@@ -96,6 +96,7 @@ void mshv_arch_init_vcpu(CPUState *cpu);
void mshv_arch_destroy_vcpu(CPUState *cpu);
void mshv_arch_amend_proc_features(
union hv_partition_synthetic_processor_features *features);
+int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd);
int mshv_arch_post_init_vm(int vm_fd);
void mshv_setup_hvcall_args(AccelCPUState *state);
diff --git a/target/i386/mshv/meson.build b/target/i386/mshv/meson.build
index 6091c21887..ce54e134cb 100644
--- a/target/i386/mshv/meson.build
+++ b/target/i386/mshv/meson.build
@@ -1,6 +1,7 @@
i386_mshv_ss = ss.source_set()
i386_mshv_ss.add(files(
+ 'mshv-all.c',
'mshv-cpu.c',
'msr.c',
))
diff --git a/target/i386/mshv/mshv-all.c b/target/i386/mshv/mshv-all.c
new file mode 100644
index 0000000000..f0b43aa86f
--- /dev/null
+++ b/target/i386/mshv/mshv-all.c
@@ -0,0 +1,80 @@
+/*
+ * QEMU MSHV support
+ *
+ * Copyright Microsoft, Corp. 2026
+ *
+ * Authors: Ziqiao Zhou <ziqiaozhou@microsoft.com>
+ * Magnus Kulke <magnuskulke@microsoft.com>
+ * Jinank Jain <jinankjain@microsoft.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/memalign.h"
+
+#include "system/mshv.h"
+#include "system/mshv_int.h"
+#include "system/address-spaces.h"
+#include "linux/mshv.h"
+#include "hw/hyperv/hvgdk.h"
+#include "hw/hyperv/hvgdk_mini.h"
+#include "hw/hyperv/hvhdk_mini.h"
+#include "hw/i386/apic_internal.h"
+
+#include "cpu.h"
+#include "emulate/x86_decode.h"
+#include "emulate/x86_emu.h"
+#include "emulate/x86_flags.h"
+
+#include "trace-accel_mshv.h"
+#include "trace.h"
+
+#include <sys/ioctl.h>
+
+int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd)
+{
+ mshv_init_mmio_emu();
+ return 0;
+}
+
+/*
+ * Default Microsoft Hypervisor behavior for unimplemented MSR is to send a
+ * fault to the guest if it tries to access it. It is possible to override
+ * this behavior with a more suitable option i.e., ignore writes from the guest
+ * and return zero in attempt to read unimplemented.
+ */
+static int set_unimplemented_msr_action(int vm_fd)
+{
+ struct hv_input_set_partition_property in = {0};
+ struct mshv_root_hvcall args = {0};
+
+ in.property_code = HV_PARTITION_PROPERTY_UNIMPLEMENTED_MSR_ACTION;
+ in.property_value = HV_UNIMPLEMENTED_MSR_ACTION_IGNORE_WRITE_READ_ZERO;
+
+ args.code = HVCALL_SET_PARTITION_PROPERTY;
+ args.in_sz = sizeof(in);
+ args.in_ptr = (uint64_t)∈
+
+ trace_mshv_hvcall_args("unimplemented_msr_action", args.code, args.in_sz);
+
+ int ret = mshv_hvcall(vm_fd, &args);
+ if (ret < 0) {
+ error_report("Failed to set unimplemented MSR action");
+ return -1;
+ }
+ return 0;
+}
+
+int mshv_arch_post_init_vm(int vm_fd)
+{
+ int ret;
+
+ ret = set_unimplemented_msr_action(vm_fd);
+ if (ret < 0) {
+ error_report("Failed to set unimplemented MSR action");
+ }
+
+ return ret;
+}
diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c
index e1df5e8a17..18e5b5206f 100644
--- a/target/i386/mshv/mshv-cpu.c
+++ b/target/i386/mshv/mshv-cpu.c
@@ -1507,43 +1507,3 @@ void mshv_arch_destroy_vcpu(CPUState *cpu)
state->hvcall_args = (MshvHvCallArgs){0};
g_clear_pointer(&env->emu_mmio_buf, g_free);
}
-
-/*
- * Default Microsoft Hypervisor behavior for unimplemented MSR is to send a
- * fault to the guest if it tries to access it. It is possible to override
- * this behavior with a more suitable option i.e., ignore writes from the guest
- * and return zero in attempt to read unimplemented.
- */
-static int set_unimplemented_msr_action(int vm_fd)
-{
- struct hv_input_set_partition_property in = {0};
- struct mshv_root_hvcall args = {0};
-
- in.property_code = HV_PARTITION_PROPERTY_UNIMPLEMENTED_MSR_ACTION;
- in.property_value = HV_UNIMPLEMENTED_MSR_ACTION_IGNORE_WRITE_READ_ZERO;
-
- args.code = HVCALL_SET_PARTITION_PROPERTY;
- args.in_sz = sizeof(in);
- args.in_ptr = (uint64_t)∈
-
- trace_mshv_hvcall_args("unimplemented_msr_action", args.code, args.in_sz);
-
- int ret = mshv_hvcall(vm_fd, &args);
- if (ret < 0) {
- error_report("Failed to set unimplemented MSR action");
- return -1;
- }
- return 0;
-}
-
-int mshv_arch_post_init_vm(int vm_fd)
-{
- int ret;
-
- ret = set_unimplemented_msr_action(vm_fd);
- if (ret < 0) {
- error_report("Failed to set unimplemented MSR action");
- }
-
- return ret;
-}
--
2.45.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 04/15] meson, target/arm/mshv: Enable arm64 build & add initial MSHV support
2026-05-27 5:00 [PATCH v4 00/15] Add ARM64 support for MSHV accelerator Aastha Rawat
` (2 preceding siblings ...)
2026-05-27 5:00 ` [PATCH v4 03/15] accel/mshv: add arch-specific accelerator init hook Aastha Rawat
@ 2026-05-27 5:00 ` Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 05/15] target/arm/mshv: implement vcpu state operations for ARM64 Aastha Rawat
` (10 subsequent siblings)
14 siblings, 0 replies; 17+ messages in thread
From: Aastha Rawat @ 2026-05-27 5:00 UTC (permalink / raw)
To: qemu-devel
Cc: Magnus Kulke, Wei Liu, Paolo Bonzini, Marc-André Lureau,
Daniel P. Berrangé, Philippe Mathieu-Daudé,
Peter Maydell, Anirudh Rayabharam, Aastha Rawat, qemu-arm,
Alexander Graf, Pedro Barbuda, Mohamed Mediouni,
Doru Blânzeanu, Pierrick Bouvier, Magnus Kulke
Enable the build of the MSHV accelerator for arm64 in the Meson build
system. Introduce initial files and stub implementations to support MSHV
for the ARM target.
Signed-off-by: Aastha Rawat <aastharawat@linux.microsoft.com>
---
meson.build | 8 +++----
target/arm/meson.build | 1 +
target/arm/mshv/meson.build | 7 ++++++
target/arm/mshv/mshv-all.c | 56 +++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 68 insertions(+), 4 deletions(-)
diff --git a/meson.build b/meson.build
index eb07491819..ff54d48e6e 100644
--- a/meson.build
+++ b/meson.build
@@ -305,7 +305,8 @@ if cpu == 'aarch64'
accelerator_targets += {
'CONFIG_HVF': ['aarch64-softmmu'],
'CONFIG_NITRO': ['aarch64-softmmu'],
- 'CONFIG_WHPX': ['aarch64-softmmu']
+ 'CONFIG_WHPX': ['aarch64-softmmu'],
+ 'CONFIG_MSHV': ['aarch64-softmmu'],
}
elif cpu == 'x86_64'
accelerator_targets += {
@@ -871,10 +872,9 @@ if get_option('kvm').allowed() and host_os == 'linux'
endif
if get_option('mshv').allowed() and host_os == 'linux'
- if get_option('mshv').enabled() and host_machine.cpu() != 'x86_64'
- error('mshv accelerator requires x64_64 host')
+ if host_machine.cpu() in [ 'x86_64', 'aarch64' ]
+ accelerators += 'CONFIG_MSHV'
endif
- accelerators += 'CONFIG_MSHV'
endif
if get_option('whpx').allowed() and host_os == 'windows'
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 4723f9f170..74d21544b9 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -58,6 +58,7 @@ arm_common_system_ss.add(files(
subdir('hvf')
subdir('whpx')
+subdir('mshv')
if 'CONFIG_TCG' in config_all_accel
subdir('tcg')
diff --git a/target/arm/mshv/meson.build b/target/arm/mshv/meson.build
new file mode 100644
index 0000000000..169643691e
--- /dev/null
+++ b/target/arm/mshv/meson.build
@@ -0,0 +1,7 @@
+arm_mshv_ss = ss.source_set()
+
+arm_mshv_ss.add(files(
+ 'mshv-all.c',
+))
+
+arm_system_ss.add_all(when: 'CONFIG_MSHV', if_true: arm_mshv_ss)
diff --git a/target/arm/mshv/mshv-all.c b/target/arm/mshv/mshv-all.c
new file mode 100644
index 0000000000..32adf26838
--- /dev/null
+++ b/target/arm/mshv/mshv-all.c
@@ -0,0 +1,56 @@
+/*
+ * QEMU MSHV support
+ *
+ * Copyright Microsoft, Corp. 2026
+ *
+ * Authors: Aastha Rawat <aastharawat@linux.microsoft.com>
+ * Anirudh Rayabharam <anirudh@anirudhrb.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/arm/virt.h"
+#include "system/mshv.h"
+#include "system/mshv_int.h"
+
+int mshv_load_regs(CPUState *cpu)
+{
+ return 0;
+}
+
+int mshv_arch_put_registers(const CPUState *cpu)
+{
+ return 0;
+}
+
+int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *exit)
+{
+ return 0;
+}
+
+void mshv_arch_init_vcpu(CPUState *cpu)
+{
+
+}
+
+void mshv_arch_destroy_vcpu(CPUState *cpu)
+{
+
+}
+
+int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd)
+{
+ return 0;
+}
+
+void mshv_arch_amend_proc_features(
+ union hv_partition_synthetic_processor_features *features)
+{
+
+}
+
+int mshv_arch_post_init_vm(int vm_fd)
+{
+ return 0;
+}
--
2.45.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 05/15] target/arm/mshv: implement vcpu state operations for ARM64
2026-05-27 5:00 [PATCH v4 00/15] Add ARM64 support for MSHV accelerator Aastha Rawat
` (3 preceding siblings ...)
2026-05-27 5:00 ` [PATCH v4 04/15] meson, target/arm/mshv: Enable arm64 build & add initial MSHV support Aastha Rawat
@ 2026-05-27 5:00 ` Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 06/15] target/arm: convert host CPU feature ifdef ladder to runtime checks Aastha Rawat
` (9 subsequent siblings)
14 siblings, 0 replies; 17+ messages in thread
From: Aastha Rawat @ 2026-05-27 5:00 UTC (permalink / raw)
To: qemu-devel
Cc: Magnus Kulke, Wei Liu, Paolo Bonzini, Marc-André Lureau,
Daniel P. Berrangé, Philippe Mathieu-Daudé,
Peter Maydell, Anirudh Rayabharam, Aastha Rawat, qemu-arm,
Alexander Graf, Pedro Barbuda, Mohamed Mediouni,
Doru Blânzeanu, Pierrick Bouvier, Magnus Kulke
Add support for reading and writing ARM64 CPU registers in the MSHV
accelerator. This includes functions to set and get registers,
initialize and destroy VCPU state, and manage register state
synchronization between QEMU and hypervisor.
Signed-off-by: Aastha Rawat <aastharawat@linux.microsoft.com>
---
include/hw/hyperv/hvgdk_mini.h | 42 +++++++++++++++
include/system/mshv_int.h | 1 -
target/arm/mshv/mshv-all.c | 118 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 160 insertions(+), 1 deletion(-)
diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h
index c3a8f33280..0933b9d6ec 100644
--- a/include/hw/hyperv/hvgdk_mini.h
+++ b/include/hw/hyperv/hvgdk_mini.h
@@ -13,6 +13,46 @@ typedef enum hv_register_name {
/* Pending Interruption Register */
HV_REGISTER_PENDING_INTERRUPTION = 0x00010002,
+#if defined(__aarch64__)
+ HV_ARM64_REGISTER_XZR = 0x0002FFFE,
+ HV_ARM64_REGISTER_X0 = 0x00020000,
+ HV_ARM64_REGISTER_X1 = 0x00020001,
+ HV_ARM64_REGISTER_X2 = 0x00020002,
+ HV_ARM64_REGISTER_X3 = 0x00020003,
+ HV_ARM64_REGISTER_X4 = 0x00020004,
+ HV_ARM64_REGISTER_X5 = 0x00020005,
+ HV_ARM64_REGISTER_X6 = 0x00020006,
+ HV_ARM64_REGISTER_X7 = 0x00020007,
+ HV_ARM64_REGISTER_X8 = 0x00020008,
+ HV_ARM64_REGISTER_X9 = 0x00020009,
+ HV_ARM64_REGISTER_X10 = 0x0002000A,
+ HV_ARM64_REGISTER_X11 = 0x0002000B,
+ HV_ARM64_REGISTER_X12 = 0x0002000C,
+ HV_ARM64_REGISTER_X13 = 0x0002000D,
+ HV_ARM64_REGISTER_X14 = 0x0002000E,
+ HV_ARM64_REGISTER_X15 = 0x0002000F,
+ HV_ARM64_REGISTER_X16 = 0x00020010,
+ HV_ARM64_REGISTER_X17 = 0x00020011,
+ HV_ARM64_REGISTER_X18 = 0x00020012,
+ HV_ARM64_REGISTER_X19 = 0x00020013,
+ HV_ARM64_REGISTER_X20 = 0x00020014,
+ HV_ARM64_REGISTER_X21 = 0x00020015,
+ HV_ARM64_REGISTER_X22 = 0x00020016,
+ HV_ARM64_REGISTER_X23 = 0x00020017,
+ HV_ARM64_REGISTER_X24 = 0x00020018,
+ HV_ARM64_REGISTER_X25 = 0x00020019,
+ HV_ARM64_REGISTER_X26 = 0x0002001A,
+ HV_ARM64_REGISTER_X27 = 0x0002001B,
+ HV_ARM64_REGISTER_X28 = 0x0002001C,
+ HV_ARM64_REGISTER_FP = 0x0002001D,
+ HV_ARM64_REGISTER_LR = 0x0002001E,
+ HV_ARM64_REGISTER_PC = 0x00020022,
+
+ /* AArch64 System Register Descriptions: General system control registers */
+ HV_ARM64_REGISTER_MIDR_EL1 = 0x00040051,
+ HV_ARM64_REGISTER_MPIDR_EL1 = 0x00040001,
+
+#elif defined(__x86_64__)
/* X64 User-Mode Registers */
HV_X64_REGISTER_RAX = 0x00020000,
HV_X64_REGISTER_RCX = 0x00020001,
@@ -157,6 +197,8 @@ typedef enum hv_register_name {
/* Other MSRs */
HV_X64_REGISTER_MSR_IA32_MISC_ENABLE = 0x000800A0,
+#endif
+
/* Misc */
HV_REGISTER_GUEST_OS_ID = 0x00090002,
HV_REGISTER_REFERENCE_TSC = 0x00090017,
diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h
index c72c91cd23..62fad48895 100644
--- a/include/system/mshv_int.h
+++ b/include/system/mshv_int.h
@@ -82,7 +82,6 @@ void mshv_init_mmio_emu(void);
int mshv_create_vcpu(int vm_fd, uint8_t vp_index, int *cpu_fd);
void mshv_remove_vcpu(int vm_fd, int cpu_fd);
int mshv_configure_vcpu(const CPUState *cpu, const MshvFPU *fpu, uint64_t xcr0);
-int mshv_get_standard_regs(CPUState *cpu);
int mshv_get_special_regs(CPUState *cpu);
int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *exit);
int mshv_load_regs(CPUState *cpu);
diff --git a/target/arm/mshv/mshv-all.c b/target/arm/mshv/mshv-all.c
index 32adf26838..3a0d14849a 100644
--- a/target/arm/mshv/mshv-all.c
+++ b/target/arm/mshv/mshv-all.c
@@ -10,17 +10,127 @@
*/
#include "qemu/osdep.h"
+#include <sys/ioctl.h>
+
+#include "qemu/error-report.h"
+#include "qemu/memalign.h"
#include "hw/arm/virt.h"
+
+#include "system/cpus.h"
+#include "target/arm/cpu.h"
+
#include "system/mshv.h"
#include "system/mshv_int.h"
+#include "hw/hyperv/hvgdk_mini.h"
+
+static const enum hv_register_name STANDARD_REGISTER_NAMES[32] = {
+ HV_ARM64_REGISTER_X0,
+ HV_ARM64_REGISTER_X1,
+ HV_ARM64_REGISTER_X2,
+ HV_ARM64_REGISTER_X3,
+ HV_ARM64_REGISTER_X4,
+ HV_ARM64_REGISTER_X5,
+ HV_ARM64_REGISTER_X6,
+ HV_ARM64_REGISTER_X7,
+ HV_ARM64_REGISTER_X8,
+ HV_ARM64_REGISTER_X9,
+ HV_ARM64_REGISTER_X10,
+ HV_ARM64_REGISTER_X11,
+ HV_ARM64_REGISTER_X12,
+ HV_ARM64_REGISTER_X13,
+ HV_ARM64_REGISTER_X14,
+ HV_ARM64_REGISTER_X15,
+ HV_ARM64_REGISTER_X16,
+ HV_ARM64_REGISTER_X17,
+ HV_ARM64_REGISTER_X18,
+ HV_ARM64_REGISTER_X19,
+ HV_ARM64_REGISTER_X20,
+ HV_ARM64_REGISTER_X21,
+ HV_ARM64_REGISTER_X22,
+ HV_ARM64_REGISTER_X23,
+ HV_ARM64_REGISTER_X24,
+ HV_ARM64_REGISTER_X25,
+ HV_ARM64_REGISTER_X26,
+ HV_ARM64_REGISTER_X27,
+ HV_ARM64_REGISTER_X28,
+ HV_ARM64_REGISTER_FP,
+ HV_ARM64_REGISTER_LR,
+ HV_ARM64_REGISTER_PC,
+};
+
+static int set_standard_regs(const CPUState *cpu)
+{
+ size_t n_regs = ARRAY_SIZE(STANDARD_REGISTER_NAMES);
+ struct hv_register_assoc assocs[ARRAY_SIZE(STANDARD_REGISTER_NAMES)] = {};
+ int ret;
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
+ CPUARMState *env = &arm_cpu->env;
+
+ for (size_t i = 0; i < n_regs - 1; i++) {
+ assocs[i].name = STANDARD_REGISTER_NAMES[i];
+ assocs[i].value.reg64 = env->xregs[i];
+ }
+
+ /* Last register is the program counter */
+ assocs[n_regs - 1].name = STANDARD_REGISTER_NAMES[n_regs - 1];
+ assocs[n_regs - 1].value.reg64 = env->pc;
+
+ ret = mshv_set_generic_regs(cpu, assocs, n_regs);
+ if (ret < 0) {
+ error_report("failed to set standard registers");
+ return -1;
+ }
+
+ return 0;
+}
+
+static int mshv_get_standard_regs(CPUState *cpu)
+{
+ size_t n_regs = ARRAY_SIZE(STANDARD_REGISTER_NAMES);
+ struct hv_register_assoc assocs[ARRAY_SIZE(STANDARD_REGISTER_NAMES)] = {};
+ int ret;
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
+ CPUARMState *env = &arm_cpu->env;
+
+ for (size_t i = 0; i < n_regs; i++) {
+ assocs[i].name = STANDARD_REGISTER_NAMES[i];
+ }
+ ret = mshv_get_generic_regs(cpu, assocs, n_regs);
+ if (ret < 0) {
+ error_report("failed to get standard registers");
+ return -1;
+ }
+
+ for (size_t i = 0; i < n_regs - 1; i++) {
+ env->xregs[i] = assocs[i].value.reg64;
+ }
+ env->pc = assocs[n_regs - 1].value.reg64;
+
+ return 0;
+}
int mshv_load_regs(CPUState *cpu)
{
+ int ret;
+
+ ret = mshv_get_standard_regs(cpu);
+ if (ret < 0) {
+ error_report("Failed to load standard registers");
+ return -1;
+ }
+
return 0;
}
int mshv_arch_put_registers(const CPUState *cpu)
{
+ int ret;
+
+ ret = set_standard_regs(cpu);
+ if (ret < 0) {
+ return ret;
+ }
+
return 0;
}
@@ -31,12 +141,20 @@ int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *exit)
void mshv_arch_init_vcpu(CPUState *cpu)
{
+ AccelCPUState *state = cpu->accel;
+ mshv_setup_hvcall_args(state);
}
void mshv_arch_destroy_vcpu(CPUState *cpu)
{
+ AccelCPUState *state = cpu->accel;
+
+ if (state->hvcall_args.base) {
+ qemu_vfree(state->hvcall_args.base);
+ }
+ state->hvcall_args = (MshvHvCallArgs){0};
}
int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd)
--
2.45.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 06/15] target/arm: convert host CPU feature ifdef ladder to runtime checks
2026-05-27 5:00 [PATCH v4 00/15] Add ARM64 support for MSHV accelerator Aastha Rawat
` (4 preceding siblings ...)
2026-05-27 5:00 ` [PATCH v4 05/15] target/arm/mshv: implement vcpu state operations for ARM64 Aastha Rawat
@ 2026-05-27 5:00 ` Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 07/15] target/arm/mshv: implement -cpu host for MSHV Aastha Rawat
` (8 subsequent siblings)
14 siblings, 0 replies; 17+ messages in thread
From: Aastha Rawat @ 2026-05-27 5:00 UTC (permalink / raw)
To: qemu-devel
Cc: Magnus Kulke, Wei Liu, Paolo Bonzini, Marc-André Lureau,
Daniel P. Berrangé, Philippe Mathieu-Daudé,
Peter Maydell, Anirudh Rayabharam, Aastha Rawat, qemu-arm,
Alexander Graf, Pedro Barbuda, Mohamed Mediouni,
Doru Blânzeanu, Pierrick Bouvier, Magnus Kulke
Replace the compile-time #if/#elif preprocessor ladder in
aarch64_host_initfn() with runtime calls and add mshv_enabled() to it.
This ensures the correct accelerator is selected at runtime when
multiple accelerators are compiled in.
Add CONFIG_MSHV to the aarch64_cpus[] guard so that mshv accelerator can
register the "host" CPU type.
Signed-off-by: Aastha Rawat <aastharawat@linux.microsoft.com>
---
target/arm/cpu64.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index b38a78aac3..aed84a3c0b 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -859,17 +859,21 @@ static void aarch64_host_initfn(Object *obj)
}
#endif
+ if (mshv_enabled()) {
+ mshv_arm_set_cpu_features_from_host(cpu);
+ } else if (kvm_enabled()) {
#if defined(CONFIG_KVM)
- kvm_arm_set_cpreg_mig_tolerances(cpu);
- kvm_arm_set_cpu_features_from_host(cpu);
- aarch64_add_sve_properties(obj);
-#elif defined(CONFIG_HVF)
- hvf_arm_set_cpu_features_from_host(cpu);
-#elif defined(CONFIG_WHPX)
- whpx_arm_set_cpu_features_from_host(cpu);
-#else
- g_assert_not_reached();
+ kvm_arm_set_cpreg_mig_tolerances(cpu);
#endif
+ kvm_arm_set_cpu_features_from_host(cpu);
+ aarch64_add_sve_properties(obj);
+ } else if (hvf_enabled()) {
+ hvf_arm_set_cpu_features_from_host(cpu);
+ } else if (whpx_enabled()) {
+ whpx_arm_set_cpu_features_from_host(cpu);
+ } else {
+ g_assert_not_reached();
+ }
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
aarch64_add_pauth_properties(obj);
}
@@ -897,7 +901,8 @@ static const ARMCPUInfo aarch64_cpus[] = {
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
{ .name = "max", .initfn = aarch64_max_initfn },
-#if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_WHPX)
+#if defined(CONFIG_KVM) || defined(CONFIG_HVF) || \
+ defined(CONFIG_WHPX) || defined(CONFIG_MSHV)
{ .name = "host", .initfn = aarch64_host_initfn },
#endif
};
--
2.45.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 07/15] target/arm/mshv: implement -cpu host for MSHV
2026-05-27 5:00 [PATCH v4 00/15] Add ARM64 support for MSHV accelerator Aastha Rawat
` (5 preceding siblings ...)
2026-05-27 5:00 ` [PATCH v4 06/15] target/arm: convert host CPU feature ifdef ladder to runtime checks Aastha Rawat
@ 2026-05-27 5:00 ` Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 08/15] accel/mshv: Add access_vp_regs synthetic proc features Aastha Rawat
` (7 subsequent siblings)
14 siblings, 0 replies; 17+ messages in thread
From: Aastha Rawat @ 2026-05-27 5:00 UTC (permalink / raw)
To: qemu-devel
Cc: Magnus Kulke, Wei Liu, Paolo Bonzini, Marc-André Lureau,
Daniel P. Berrangé, Philippe Mathieu-Daudé,
Peter Maydell, Anirudh Rayabharam, Aastha Rawat, qemu-arm,
Alexander Graf, Pedro Barbuda, Mohamed Mediouni,
Doru Blânzeanu, Pierrick Bouvier, Magnus Kulke
This commit enables support for the `-cpu host` option with MSHV
accelerator on ARM64. The implementation queries the partition's CPU's
ID registers and features via hypervisor interface, allowing to pass all
CPU capabilities for the host CPU to the guest.
Signed-off-by: Aastha Rawat <aastharawat@linux.microsoft.com>
---
accel/mshv/mshv-all.c | 3 +-
hw/arm/virt.c | 3 +-
include/hw/hyperv/hvgdk_mini.h | 17 ++++
include/hw/hyperv/hvhdk.h | 10 ++
include/system/hw_accel.h | 3 +-
target/arm/cpu.c | 6 +-
target/arm/cpu64.c | 2 +
target/arm/mshv/mshv-all.c | 217 +++++++++++++++++++++++++++++++++++++++++
target/arm/mshv_arm.h | 18 ++++
9 files changed, 274 insertions(+), 5 deletions(-)
diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c
index 65095798e2..294955788a 100644
--- a/accel/mshv/mshv-all.c
+++ b/accel/mshv/mshv-all.c
@@ -415,13 +415,14 @@ static int mshv_init_vcpu(CPUState *cpu)
int ret;
cpu->accel = g_new0(AccelCPUState, 1);
- mshv_arch_init_vcpu(cpu);
ret = mshv_create_vcpu(vm_fd, vp_index, &cpu->accel->cpufd);
if (ret < 0) {
return -1;
}
+ mshv_arch_init_vcpu(cpu);
+
cpu->accel->dirty = true;
return 0;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index b090233893..7803c73b0d 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -49,6 +49,7 @@
#include "system/kvm.h"
#include "system/hvf.h"
#include "system/whpx.h"
+#include "system/mshv.h"
#include "system/qtest.h"
#include "system/system.h"
#include "hw/core/loader.h"
@@ -4065,7 +4066,7 @@ static GPtrArray *virt_get_valid_cpu_types(const MachineState *ms)
if (target_aarch64()) {
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a53")));
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("cortex-a57")));
- if (kvm_enabled() || hvf_enabled() || whpx_enabled()) {
+ if (kvm_enabled() || hvf_enabled() || whpx_enabled() || mshv_enabled()) {
g_ptr_array_add(vct, g_strdup(ARM_CPU_TYPE_NAME("host")));
}
}
diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h
index 0933b9d6ec..7dc9511692 100644
--- a/include/hw/hyperv/hvgdk_mini.h
+++ b/include/hw/hyperv/hvgdk_mini.h
@@ -48,6 +48,20 @@ typedef enum hv_register_name {
HV_ARM64_REGISTER_LR = 0x0002001E,
HV_ARM64_REGISTER_PC = 0x00020022,
+ /* AArch64 System Register Descriptions: ID Registers */
+ HV_ARM64_REGISTER_ID_MIDR_EL1 = 0x00022000,
+ HV_ARM64_REGISTER_ID_MPIDR_EL1 = 0x00022005,
+ HV_ARM64_REGISTER_ID_AA64_PFR0_EL1 = 0x00022020,
+ HV_ARM64_REGISTER_ID_AA64_PFR1_EL1 = 0x00022021,
+ HV_ARM64_REGISTER_ID_AA64_ISAR0_EL1 = 0x00022030,
+ HV_ARM64_REGISTER_ID_AA64_ISAR1_EL1 = 0x00022031,
+ HV_ARM64_REGISTER_ID_AA64_ISAR2_EL1 = 0x00022032,
+ HV_ARM64_REGISTER_ID_AA64_MMFR0_EL1 = 0x00022038,
+ HV_ARM64_REGISTER_ID_AA64_MMFR1_EL1 = 0x00022039,
+ HV_ARM64_REGISTER_ID_AA64_MMFR2_EL1 = 0x0002203a,
+ HV_ARM64_REGISTER_ID_AA64_DFR0_EL1 = 0x00022028,
+ HV_ARM64_REGISTER_ID_AA64_DFR1_EL1 = 0x00022029,
+
/* AArch64 System Register Descriptions: General system control registers */
HV_ARM64_REGISTER_MIDR_EL1 = 0x00040051,
HV_ARM64_REGISTER_MPIDR_EL1 = 0x00040001,
@@ -850,6 +864,9 @@ struct hv_cpuid {
#define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT)
#define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1))
+#define HV_ANY_VP ((uint32_t)-1)
+#define HV_VTL_ALL 0xF
+
#define HVCALL_GET_PARTITION_PROPERTY 0x0044
#define HVCALL_SET_PARTITION_PROPERTY 0x0045
#define HVCALL_GET_VP_REGISTERS 0x0050
diff --git a/include/hw/hyperv/hvhdk.h b/include/hw/hyperv/hvhdk.h
index 41af743847..4695ceb92c 100644
--- a/include/hw/hyperv/hvhdk.h
+++ b/include/hw/hyperv/hvhdk.h
@@ -18,6 +18,16 @@ struct hv_input_set_partition_property {
uint64_t property_value;
} QEMU_PACKED;
+struct hv_input_get_partition_property {
+ uint64_t partition_id;
+ uint32_t property_code; /* enum hv_partition_property_code */
+ uint32_t padding;
+};
+
+struct hv_output_get_partition_property {
+ uint64_t property_value;
+};
+
union hv_partition_synthetic_processor_features {
uint64_t as_uint64[HV_PARTITION_SYNTHETIC_PROCESSOR_FEATURES_BANKS];
diff --git a/include/system/hw_accel.h b/include/system/hw_accel.h
index f0c10b6d80..614ea60be3 100644
--- a/include/system/hw_accel.h
+++ b/include/system/hw_accel.h
@@ -51,7 +51,8 @@ static inline bool hwaccel_enabled(void)
return hvf_enabled()
|| kvm_enabled()
|| nvmm_enabled()
- || whpx_enabled();
+ || whpx_enabled()
+ || mshv_enabled();
}
#endif /* QEMU_HW_ACCEL_H */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c47b70ac69..524ed3536a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -47,6 +47,7 @@
#include "system/tcg.h"
#include "system/qtest.h"
#include "system/hw_accel.h"
+#include "system/mshv.h"
#include "kvm_arm.h"
#include "disas/capstone.h"
#include "fpu/softfloat.h"
@@ -1781,8 +1782,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* this is the first point where we can report it.
*/
if (cpu->host_cpu_probe_failed) {
- if (!kvm_enabled() && !hvf_enabled() && !whpx_enabled()) {
- error_setg(errp, "The 'host' CPU type can only be used with KVM, HVF or WHPX");
+ if (!kvm_enabled() && !hvf_enabled() && !whpx_enabled() && !mshv_enabled()) {
+ error_setg(errp,
+ "The 'host' CPU type can only be used with KVM, HVF, WHPX, or MSHV");
} else {
error_setg(errp, "Failed to retrieve host CPU features");
}
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index aed84a3c0b..8fa7a4d102 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -26,12 +26,14 @@
#include "qemu/units.h"
#include "system/kvm.h"
#include "system/hvf.h"
+#include "system/mshv.h"
#include "system/whpx.h"
#include "system/hw_accel.h"
#include "system/qtest.h"
#include "system/tcg.h"
#include "kvm_arm.h"
#include "hvf_arm.h"
+#include "mshv_arm.h"
#include "whpx_arm.h"
#include "qapi/visitor.h"
#include "hw/core/qdev-properties.h"
diff --git a/target/arm/mshv/mshv-all.c b/target/arm/mshv/mshv-all.c
index 3a0d14849a..96a04df38a 100644
--- a/target/arm/mshv/mshv-all.c
+++ b/target/arm/mshv/mshv-all.c
@@ -18,10 +18,23 @@
#include "system/cpus.h"
#include "target/arm/cpu.h"
+#include "target/arm/internals.h"
+#include "target/arm/mshv_arm.h"
#include "system/mshv.h"
#include "system/mshv_int.h"
#include "hw/hyperv/hvgdk_mini.h"
+#include "hw/hyperv/hvhdk_mini.h"
+
+typedef struct ARMHostCPUFeatures {
+ ARMISARegisters isar;
+ uint64_t features;
+ uint64_t midr;
+ uint32_t reset_sctlr;
+ const char *dtb_compatible;
+} ARMHostCPUFeatures;
+
+static ARMHostCPUFeatures arm_host_cpu_features;
static const enum hv_register_name STANDARD_REGISTER_NAMES[32] = {
HV_ARM64_REGISTER_X0,
@@ -157,8 +170,46 @@ void mshv_arch_destroy_vcpu(CPUState *cpu)
state->hvcall_args = (MshvHvCallArgs){0};
}
+
+static uint32_t mshv_arm_get_ipa_bit_size(int mshv_fd)
+{
+ int ret;
+ struct hv_input_get_partition_property in = {0};
+ struct hv_output_get_partition_property out = {0};
+ struct mshv_root_hvcall args = {0};
+
+ in.property_code = HV_PARTITION_PROPERTY_PHYSICAL_ADDRESS_WIDTH;
+
+ args.code = HVCALL_GET_PARTITION_PROPERTY;
+ args.in_sz = sizeof(in);
+ args.in_ptr = (uint64_t)∈
+ args.out_sz = sizeof(out);
+ args.out_ptr = (uint64_t)&out;
+
+ ret = mshv_hvcall(mshv_fd, &args);
+
+ if (ret < 0) {
+ error_report("Failed to get IPA size");
+ exit(1);
+ }
+
+ return out.property_value;
+}
+
int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd)
{
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
+ int pa_range;
+ uint32_t ipa_size;
+
+ if (mc->get_physical_address_range) {
+ ipa_size = mshv_arm_get_ipa_bit_size(mshv_fd);
+ pa_range = mc->get_physical_address_range(ms, ipa_size, ipa_size);
+ if (pa_range < 0) {
+ return -EINVAL;
+ }
+ }
+
return 0;
}
@@ -172,3 +223,169 @@ int mshv_arch_post_init_vm(int vm_fd)
{
return 0;
}
+
+static void clamp_id_aa64mmfr0_parange_to_ipa_size(int mshv_fd,
+ ARMISARegisters *isar)
+{
+ uint32_t ipa_size = mshv_arm_get_ipa_bit_size(mshv_fd);
+ uint64_t id_aa64mmfr0;
+
+ /* Clamp down the PARange to the IPA size the kernel supports. */
+ uint8_t index = round_down_to_parange_index(ipa_size);
+ id_aa64mmfr0 = GET_IDREG(isar, ID_AA64MMFR0);
+ id_aa64mmfr0 = FIELD_DP64(id_aa64mmfr0, ID_AA64MMFR0, PARANGE, index);
+ SET_IDREG(isar, ID_AA64MMFR0, id_aa64mmfr0);
+}
+
+static int mshv_get_partition_regs(int vm_fd, hv_register_name *names,
+ hv_register_value *values, size_t n_regs)
+{
+ int ret = 0;
+ size_t in_sz, names_sz, values_sz;
+ void *in_buffer = qemu_memalign(HV_HYP_PAGE_SIZE, HV_HYP_PAGE_SIZE);
+ void *out_buffer = qemu_memalign(HV_HYP_PAGE_SIZE, HV_HYP_PAGE_SIZE);
+ hv_input_get_vp_registers *in = in_buffer;
+
+ struct mshv_root_hvcall args = {0};
+
+ names_sz = n_regs * sizeof(hv_register_name);
+ in_sz = sizeof(hv_input_get_vp_registers) + names_sz;
+
+ memset(in, 0, HV_HYP_PAGE_SIZE);
+
+ in->vp_index = HV_ANY_VP;
+ in->input_vtl.target_vtl = HV_VTL_ALL;
+ in->input_vtl.use_target_vtl = 1;
+
+ for (int i = 0; i < n_regs; i++) {
+ in->names[i] = names[i];
+ }
+
+ values_sz = n_regs * sizeof(hv_register_value);
+
+ args.code = HVCALL_GET_VP_REGISTERS;
+ args.in_sz = in_sz;
+ args.in_ptr = (uintptr_t)in_buffer;
+ args.out_sz = values_sz;
+ args.out_ptr = (uintptr_t)out_buffer;
+ args.reps = n_regs;
+
+ ret = mshv_hvcall(vm_fd, &args);
+
+ if (ret == 0) {
+ memcpy(values, out_buffer, values_sz);
+ }
+
+ qemu_vfree(in_buffer);
+ qemu_vfree(out_buffer);
+
+ return ret;
+}
+
+static bool mshv_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
+{
+ int mshv_fd = mshv_state->fd;
+ int vm_fd = mshv_state->vm;
+ int i, ret;
+ bool success = true;
+ uint64_t pfr0, pfr1;
+ gchar *contents = NULL;
+
+ static const struct {
+ hv_register_name name;
+ int isar_idx;
+ } regs[] = {
+ { HV_ARM64_REGISTER_ID_AA64_PFR0_EL1, ID_AA64PFR0_EL1_IDX },
+ { HV_ARM64_REGISTER_ID_AA64_PFR1_EL1, ID_AA64PFR1_EL1_IDX },
+ { HV_ARM64_REGISTER_ID_AA64_ISAR0_EL1, ID_AA64ISAR0_EL1_IDX },
+ { HV_ARM64_REGISTER_ID_AA64_ISAR1_EL1, ID_AA64ISAR1_EL1_IDX },
+ { HV_ARM64_REGISTER_ID_AA64_ISAR2_EL1, ID_AA64ISAR2_EL1_IDX },
+ { HV_ARM64_REGISTER_ID_AA64_MMFR0_EL1, ID_AA64MMFR0_EL1_IDX },
+ { HV_ARM64_REGISTER_ID_AA64_MMFR1_EL1, ID_AA64MMFR1_EL1_IDX },
+ { HV_ARM64_REGISTER_ID_AA64_MMFR2_EL1, ID_AA64MMFR2_EL1_IDX },
+ { HV_ARM64_REGISTER_ID_AA64_DFR0_EL1, ID_AA64DFR0_EL1_IDX },
+ { HV_ARM64_REGISTER_ID_AA64_DFR1_EL1, ID_AA64DFR1_EL1_IDX },
+ };
+
+ size_t n_regs = ARRAY_SIZE(regs);
+ hv_register_name *reg_names = g_new(hv_register_name, n_regs);
+ hv_register_value *reg_values = g_new(hv_register_value, n_regs);
+
+ for (i = 0; i < n_regs; i++) {
+ reg_names[i] = regs[i].name;
+ }
+
+ ret = mshv_get_partition_regs(vm_fd, reg_names, reg_values, n_regs);
+
+ if (ret < 0) {
+ error_report("Failed to get host ID registers");
+ success = false;
+ goto out;
+ }
+
+ for (i = 0; i < n_regs; i++) {
+ ahcf->isar.idregs[regs[i].isar_idx] = reg_values[i].reg64;
+ }
+
+ /* Read MIDR_EL1 from sysfs */
+ if (g_file_get_contents(
+ "/sys/devices/system/cpu/cpu0/regs/identification/midr_el1",
+ &contents, NULL, NULL)) {
+ ahcf->midr = g_ascii_strtoull(contents, NULL, 0);
+ } else {
+ error_report("Failed to read MIDR_EL1 from sysfs");
+ success = false;
+ goto out;
+ }
+
+ ahcf->dtb_compatible = "arm,armv8";
+ ahcf->features = (1ULL << ARM_FEATURE_V8) |
+ (1ULL << ARM_FEATURE_AARCH64) |
+ (1ULL << ARM_FEATURE_PMU) |
+ (1ULL << ARM_FEATURE_GENERIC_TIMER) |
+ (1ULL << ARM_FEATURE_NEON);
+
+ clamp_id_aa64mmfr0_parange_to_ipa_size(mshv_fd, &ahcf->isar);
+
+ /*
+ * SVE (Scalable Vector Extension) and SME (Scalable Matrix Extension)
+ * require specific context switch logic in the accelerator.
+ * Mask them out for now to ensure stability.
+ */
+ /* Mask SVE in PFR0 */
+ pfr0 = GET_IDREG(&ahcf->isar, ID_AA64PFR0);
+ pfr0 &= ~R_ID_AA64PFR0_SVE_MASK;
+ SET_IDREG(&ahcf->isar, ID_AA64PFR0, pfr0);
+
+ /* Mask SME in PFR1 */
+ pfr1 = GET_IDREG(&ahcf->isar, ID_AA64PFR1);
+ pfr1 &= ~R_ID_AA64PFR1_SME_MASK;
+ SET_IDREG(&ahcf->isar, ID_AA64PFR1, pfr1);
+
+out:
+ g_free(contents);
+ g_free(reg_names);
+ g_free(reg_values);
+ return success;
+}
+
+void mshv_arm_set_cpu_features_from_host(ARMCPU *cpu)
+{
+ if (!arm_host_cpu_features.dtb_compatible) {
+ if (!mshv_enabled() ||
+ !mshv_arm_get_host_cpu_features(&arm_host_cpu_features)) {
+ /*
+ * We can't report this error yet, so flag that we need to
+ * in arm_cpu_realizefn().
+ */
+ cpu->host_cpu_probe_failed = true;
+ return;
+ }
+ }
+
+ cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;
+ cpu->isar = arm_host_cpu_features.isar;
+ cpu->env.features = arm_host_cpu_features.features;
+ cpu->midr = arm_host_cpu_features.midr;
+ cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr;
+}
diff --git a/target/arm/mshv_arm.h b/target/arm/mshv_arm.h
new file mode 100644
index 0000000000..a03f9a4405
--- /dev/null
+++ b/target/arm/mshv_arm.h
@@ -0,0 +1,18 @@
+/*
+ * QEMU MSHV support
+ *
+ * Copyright Microsoft, Corp. 2026
+ *
+ * Authors: Aastha Rawat <aastharawat@linux.microsoft.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef QEMU_MSHV_ARM_H
+#define QEMU_MSHV_ARM_H
+
+#include "target/arm/cpu.h"
+
+void mshv_arm_set_cpu_features_from_host(ARMCPU *cpu);
+
+#endif
--
2.45.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 08/15] accel/mshv: Add access_vp_regs synthetic proc features
2026-05-27 5:00 [PATCH v4 00/15] Add ARM64 support for MSHV accelerator Aastha Rawat
` (6 preceding siblings ...)
2026-05-27 5:00 ` [PATCH v4 07/15] target/arm/mshv: implement -cpu host for MSHV Aastha Rawat
@ 2026-05-27 5:00 ` Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 09/15] target/arm: cpu: Mark MSHV supporting PSCI 1.3 Aastha Rawat
` (6 subsequent siblings)
14 siblings, 0 replies; 17+ messages in thread
From: Aastha Rawat @ 2026-05-27 5:00 UTC (permalink / raw)
To: qemu-devel
Cc: Magnus Kulke, Wei Liu, Paolo Bonzini, Marc-André Lureau,
Daniel P. Berrangé, Philippe Mathieu-Daudé,
Peter Maydell, Anirudh Rayabharam, Aastha Rawat, qemu-arm,
Alexander Graf, Pedro Barbuda, Mohamed Mediouni,
Doru Blânzeanu, Pierrick Bouvier, Magnus Kulke
Enable access_vp_regs feature for regs. In arm64, this feature bit
allows the guest to set VP registers using hypercall. This wasn't
required for x86 because such registers are set using wrmsr instead of
hypercall.
Signed-off-by: Aastha Rawat <aastharawat@linux.microsoft.com>
---
accel/mshv/mshv-all.c | 1 +
include/hw/hyperv/hvhdk.h | 91 ++++++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 91 insertions(+), 1 deletion(-)
diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c
index 294955788a..927e1b39bb 100644
--- a/accel/mshv/mshv-all.c
+++ b/accel/mshv/mshv-all.c
@@ -156,6 +156,7 @@ static int set_synthetic_proc_features(int vm_fd)
features.tb_flush_hypercalls = 1;
features.synthetic_cluster_ipi = 1;
features.direct_synthetic_timers = 1;
+ features.access_vp_regs = 1;
mshv_arch_amend_proc_features(&features);
diff --git a/include/hw/hyperv/hvhdk.h b/include/hw/hyperv/hvhdk.h
index 4695ceb92c..0261063908 100644
--- a/include/hw/hyperv/hvhdk.h
+++ b/include/hw/hyperv/hvhdk.h
@@ -94,11 +94,16 @@ union hv_partition_synthetic_processor_features {
*/
uint64_t access_partition_reference_tsc:1;
+#if defined(__x86_64__)
+
/*
* Partition has access to the guest idle reg. Corresponds to
* access_guest_idle_reg privilege.
*/
uint64_t access_guest_idle_reg:1;
+#else
+ uint64_t reserved_z10:1;
+#endif
/*
* Partition has access to frequency regs. corresponds to
@@ -110,11 +115,16 @@ union hv_partition_synthetic_processor_features {
uint64_t reserved_z13:1; /* Reserved for access_root_scheduler_reg */
uint64_t reserved_z14:1; /* Reserved for access_tsc_invariant_controls */
+#if defined(__x86_64__)
+
/*
* Extended GVA ranges for HvCallFlushVirtualAddressList hypercall.
* Corresponds to privilege.
*/
uint64_t enable_extended_gva_ranges_for_flush_virtual_address_list:1;
+#else
+ uint64_t reserved_z15:1;
+#endif
uint64_t reserved_z16:1; /* Reserved for access_vsm. */
uint64_t reserved_z17:1; /* Reserved for access_vp_registers. */
@@ -161,13 +171,92 @@ union hv_partition_synthetic_processor_features {
/* HvCallRetargetDeviceInterrupt is supported. */
uint64_t retarget_device_interrupt:1;
+#if defined(__x86_64__)
/* HvCallRestorePartitionTime is supported. */
uint64_t restore_time:1;
/* EnlightenedVmcs nested enlightenment is supported. */
uint64_t enlightened_vmcs:1;
- uint64_t reserved:30;
+ uint64_t nested_debug_ctl:1;
+ uint64_t synthetic_time_unhalted_timer:1;
+ uint64_t idle_spec_ctrl:1;
+
+#else
+ uint64_t reserved_z31:1;
+ uint64_t reserved_z32:1;
+ uint64_t reserved_z33:1;
+ uint64_t reserved_z34:1;
+ uint64_t reserved_z35:1;
+#endif
+
+#if defined(__aarch64__)
+ /*
+ * Register intercepts supported in V1. As more registers are supported
+ * in future releases, new bits will be added here to prevent migration
+ * between incompatible hosts.
+ *
+ * List of registers supported in V1:
+ * 1. TPIDRRO_EL0
+ * 2. TPIDR_EL1
+ * 3. SCTLR_EL1 - Supports write intercept mask.
+ * 4. VBAR_EL1
+ * 5. TCR_EL1 - Supports write intercept mask.
+ * 6. MAIR_EL1 - Supports write intercept mask.
+ * 7. CPACR_EL1 - Supports write intercept mask.
+ * 8. CONTEXTIDR_EL1
+ * 9. PAuth keys (total 10 registers)
+ * 10. HvArm64RegisterSyntheticException
+ */
+ uint64_t register_intercepts_v1:1;
+#else
+ uint64_t reserved_z36:1;
+#endif
+
+ /* HvCallWakeVps is supported */
+ uint64_t wake_vps:1;
+
+ /*
+ * HvCallGet/SetVpRegisters is supported.
+ * Corresponds to AccessVpRegisters privilege.
+ * This feature only affects exo partitions.
+ */
+ uint64_t access_vp_regs:1;
+
+#if defined(__aarch64__)
+ /* HvCallSyncContext/Ex is supported. */
+ uint64_t sync_context:1;
+#else
+ uint64_t reserved_z39:1;
+#endif /* __aarch64__ */
+
+ /*
+ * Management VTL synic support is allowed.
+ * Corresponds to the ManagementVtlSynicSupport privilege.
+ */
+ uint64_t management_vtl_synic_support:1;
+
+#if defined(__x86_64__)
+ /*
+ * Hypervisor supports guest mechanism to signal pending interrupts to
+ * paravisor.
+ */
+ uint64_t proxy_interrupt_doorbell_support:1;
+#else
+ uint64_t reserved_z41:1;
+#endif
+
+#if defined(__aarch64__)
+ /* InterceptSystemResetAvailable is exposed. */
+ uint64_t intercept_system_reset:1;
+#else
+ uint64_t reserved_z42:1;
+#endif
+
+ /* Hypercalls for host MMIO operations are available. */
+ uint64_t mmio_hypercalls:1;
+
+ uint64_t reserved:20;
};
};
--
2.45.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 09/15] target/arm: cpu: Mark MSHV supporting PSCI 1.3
2026-05-27 5:00 [PATCH v4 00/15] Add ARM64 support for MSHV accelerator Aastha Rawat
` (7 preceding siblings ...)
2026-05-27 5:00 ` [PATCH v4 08/15] accel/mshv: Add access_vp_regs synthetic proc features Aastha Rawat
@ 2026-05-27 5:00 ` Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 10/15] accel/mshv: implement cpu_thread_is_idle() hook Aastha Rawat
` (5 subsequent siblings)
14 siblings, 0 replies; 17+ messages in thread
From: Aastha Rawat @ 2026-05-27 5:00 UTC (permalink / raw)
To: qemu-devel
Cc: Magnus Kulke, Wei Liu, Paolo Bonzini, Marc-André Lureau,
Daniel P. Berrangé, Philippe Mathieu-Daudé,
Peter Maydell, Anirudh Rayabharam, Aastha Rawat, qemu-arm,
Alexander Graf, Pedro Barbuda, Mohamed Mediouni,
Doru Blânzeanu, Pierrick Bouvier, Magnus Kulke
MSHV supports PSCI 1.3. Expose this version to guests.
Signed-off-by: Aastha Rawat <aastharawat@linux.microsoft.com>
Reviewed-by: Mohamed Mediouni <mohamed@unpredictable.fr>
---
target/arm/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 524ed3536a..aa1b3c364b 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1247,7 +1247,7 @@ static void arm_cpu_initfn(Object *obj)
if (tcg_enabled() || hvf_enabled()) {
/* TCG and HVF implement PSCI 1.1 */
cpu->psci_version = QEMU_PSCI_VERSION_1_1;
- } else if (whpx_enabled()) {
+ } else if (whpx_enabled() || mshv_enabled()) {
cpu->psci_version = QEMU_PSCI_VERSION_1_3;
}
}
--
2.45.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 10/15] accel/mshv: implement cpu_thread_is_idle() hook
2026-05-27 5:00 [PATCH v4 00/15] Add ARM64 support for MSHV accelerator Aastha Rawat
` (8 preceding siblings ...)
2026-05-27 5:00 ` [PATCH v4 09/15] target/arm: cpu: Mark MSHV supporting PSCI 1.3 Aastha Rawat
@ 2026-05-27 5:00 ` Aastha Rawat
2026-06-02 13:24 ` Magnus Kulke
2026-05-27 5:00 ` [PATCH v4 11/15] target/arm: extract MMIO emulation logic for HVF & WHPX Aastha Rawat
` (4 subsequent siblings)
14 siblings, 1 reply; 17+ messages in thread
From: Aastha Rawat @ 2026-05-27 5:00 UTC (permalink / raw)
To: qemu-devel
Cc: Magnus Kulke, Wei Liu, Paolo Bonzini, Marc-André Lureau,
Daniel P. Berrangé, Philippe Mathieu-Daudé,
Peter Maydell, Anirudh Rayabharam, Aastha Rawat, qemu-arm,
Alexander Graf, Pedro Barbuda, Mohamed Mediouni,
Doru Blânzeanu, Pierrick Bouvier, Magnus Kulke
From: Magnus Kulke <magnuskulke@linux.microsoft.com>
In MSHV the hypervisor APIC is always used, so we to implement this hook
to make sure the AP's vcpu thread is not blocked waiting for an INIT SIPI
by the BSP. Without this change soft reboots with -smp cpus>=2 will
hang.
Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>
Reviewed-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Signed-off-by: Aastha Rawat <aastharawat@linux.microsoft.com>
---
accel/mshv/mshv-all.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c
index 927e1b39bb..61a9d58546 100644
--- a/accel/mshv/mshv-all.c
+++ b/accel/mshv/mshv-all.c
@@ -719,11 +719,23 @@ static const TypeInfo mshv_accel_type = {
.instance_size = sizeof(MshvState),
};
+/*
+ * Haulted vCPUs must still enter mshv_cpu_exec() so that MSHV_RUN_VP
+ * is called and the hypervisor can wake them (via SIPI on x86 or
+ * PSCI on ARM64).
+ */
+
+static bool mshv_vcpu_thread_is_idle(CPUState *cpu)
+{
+ return false;
+}
+
static void mshv_accel_ops_class_init(ObjectClass *oc, const void *data)
{
AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
ops->create_vcpu_thread = mshv_start_vcpu_thread;
+ ops->cpu_thread_is_idle = mshv_vcpu_thread_is_idle;
ops->synchronize_post_init = mshv_cpu_synchronize_post_init;
ops->synchronize_post_reset = mshv_cpu_synchronize_post_reset;
ops->synchronize_state = mshv_cpu_synchronize;
--
2.45.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v4 10/15] accel/mshv: implement cpu_thread_is_idle() hook
2026-05-27 5:00 ` [PATCH v4 10/15] accel/mshv: implement cpu_thread_is_idle() hook Aastha Rawat
@ 2026-06-02 13:24 ` Magnus Kulke
0 siblings, 0 replies; 17+ messages in thread
From: Magnus Kulke @ 2026-06-02 13:24 UTC (permalink / raw)
To: Aastha Rawat
Cc: qemu-devel, Wei Liu, Paolo Bonzini, Marc-André Lureau,
Daniel P. Berrangé, Philippe Mathieu-Daudé,
Peter Maydell, Anirudh Rayabharam, qemu-arm, Alexander Graf,
Pedro Barbuda, Mohamed Mediouni, Doru Blânzeanu,
Pierrick Bouvier
On Wed, May 27, 2026 at 05:00:46AM +0000, Aastha Rawat wrote:
> From: Magnus Kulke <magnuskulke@linux.microsoft.com>
>
> In MSHV the hypervisor APIC is always used, so we to implement this hook
> to make sure the AP's vcpu thread is not blocked waiting for an INIT SIPI
> by the BSP. Without this change soft reboots with -smp cpus>=2 will
> hang.
>
> Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com>
> Reviewed-by: Mohamed Mediouni <mohamed@unpredictable.fr>
> Signed-off-by: Aastha Rawat <aastharawat@linux.microsoft.com>
> ---
> accel/mshv/mshv-all.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c
> index 927e1b39bb..61a9d58546 100644
> --- a/accel/mshv/mshv-all.c
> +++ b/accel/mshv/mshv-all.c
> @@ -719,11 +719,23 @@ static const TypeInfo mshv_accel_type = {
> .instance_size = sizeof(MshvState),
> };
>
> +/*
> + * Haulted vCPUs must still enter mshv_cpu_exec() so that MSHV_RUN_VP
> + * is called and the hypervisor can wake them (via SIPI on x86 or
> + * PSCI on ARM64).
> + */
> +
> +static bool mshv_vcpu_thread_is_idle(CPUState *cpu)
> +{
> + return false;
> +}
> +
> static void mshv_accel_ops_class_init(ObjectClass *oc, const void *data)
> {
> AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
>
> ops->create_vcpu_thread = mshv_start_vcpu_thread;
> + ops->cpu_thread_is_idle = mshv_vcpu_thread_is_idle;
> ops->synchronize_post_init = mshv_cpu_synchronize_post_init;
> ops->synchronize_post_reset = mshv_cpu_synchronize_post_reset;
> ops->synchronize_state = mshv_cpu_synchronize;
>
> --
> 2.45.4
this has been merged independently since: dbfb680772d5184544f7c0a8bba96bec229c96e6
best,
magnus
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v4 11/15] target/arm: extract MMIO emulation logic for HVF & WHPX
2026-05-27 5:00 [PATCH v4 00/15] Add ARM64 support for MSHV accelerator Aastha Rawat
` (9 preceding siblings ...)
2026-05-27 5:00 ` [PATCH v4 10/15] accel/mshv: implement cpu_thread_is_idle() hook Aastha Rawat
@ 2026-05-27 5:00 ` Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 12/15] target/arm/mshv: add vCPU run loop Aastha Rawat
` (3 subsequent siblings)
14 siblings, 0 replies; 17+ messages in thread
From: Aastha Rawat @ 2026-05-27 5:00 UTC (permalink / raw)
To: qemu-devel
Cc: Magnus Kulke, Wei Liu, Paolo Bonzini, Marc-André Lureau,
Daniel P. Berrangé, Philippe Mathieu-Daudé,
Peter Maydell, Anirudh Rayabharam, Aastha Rawat, qemu-arm,
Alexander Graf, Pedro Barbuda, Mohamed Mediouni,
Doru Blânzeanu, Pierrick Bouvier, Magnus Kulke
- Move common MMIO emulation code from HVF and WHPX backend to
arm_emulate_mmio() in helper.c.
- Update HVF and WHPX to use the new helper and shared types.
Signed-off-by: Aastha Rawat <aastharawat@linux.microsoft.com>
---
target/arm/helper.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++
target/arm/helper.h | 16 ++++++++++++
target/arm/hvf/hvf.c | 57 +++++++++++++++++++-----------------------
target/arm/syndrome.h | 47 +++++++++++++++++++++++++++++++++++
target/arm/whpx/whpx-all.c | 41 ++++++++++++------------------
5 files changed, 167 insertions(+), 56 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8240f1b384..6e7b4591dc 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -34,6 +34,8 @@
#endif
#include "cpregs.h"
#include "target/arm/gtimer.h"
+#include "target/arm/helper.h"
+#include "target/arm/syndrome.h"
#include "qemu/plugin.h"
static void switch_mode(CPUARMState *env, int mode);
@@ -9097,6 +9099,66 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
take_aarch32_exception(env, new_mode, mask, offset, addr);
}
+/*
+ * Emulate a data abort syndrome for MMIO/guest memory access
+ */
+int arm_emulate_mmio(CPUState *cpu, EsrEl2 syndrome, uint64_t gpa,
+ const struct arm_emul_ops *ops)
+{
+ int ret;
+ IssDataAbort iss = { 0 };
+ iss.raw = syndrome.iss;
+
+ if (!(syndrome.ec == data_abort_lower || syndrome.ec == data_abort)) {
+ error_report("Unknown exception class 0x%x", syndrome.ec);
+ return -1;
+ }
+
+ if (!iss.isv) {
+ error_report("Cannot emulate MMIO. ISS not valid.");
+ return -1;
+ }
+
+ AddressSpace *as = cpu_get_address_space(cpu, ARMASIdx_NS);
+ uint64_t len = 1ULL << iss.sas;
+ bool sign_extend = iss.sse;
+ uint64_t reg_index = iss.srt;
+
+ if (iss.wnr) {
+ uint8_t data[8];
+ uint64_t val = reg_index < 31 ? ops->get_reg(cpu, reg_index) : 0ULL;
+ val = cpu_to_le64(val);
+ memcpy(data, &val, sizeof(val));
+ ret = address_space_write(as, gpa, MEMTXATTRS_UNSPECIFIED, data, len);
+ if (ret != MEMTX_OK) {
+ error_report("Failed to write guest memory");
+ return -1;
+ }
+ } else {
+ uint8_t data[8] = { 0 };
+ ret = address_space_read(as, gpa, MEMTXATTRS_UNSPECIFIED, data, len);
+ if (ret != MEMTX_OK) {
+ error_report("Failed to read guest memory");
+ return -1;
+ }
+ uint64_t val;
+ memcpy(&val, data, sizeof(val));
+ val = le64_to_cpu(val);
+ if (sign_extend) {
+ uint64_t shift = 64 - (len * 8);
+ val = (((int64_t)val << shift) >> shift);
+ }
+ if (!iss.sf) {
+ val &= 0xffffffff;
+ }
+ if (reg_index < 31) {
+ ops->set_reg(cpu, reg_index, val);
+ }
+ }
+
+ return 0;
+}
+
static int aarch64_regnum(CPUARMState *env, int aarch32_reg)
{
/*
diff --git a/target/arm/helper.h b/target/arm/helper.h
index b1c26c180e..503404112d 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -3,8 +3,24 @@
#ifndef HELPER__H
#define HELPER__H
+#include <stdint.h>
+#include <stdbool.h>
#include "exec/helper-proto-common.h"
#include "exec/helper-gen-common.h"
+#include "target/arm/syndrome.h"
+
+/*
+ * Callback ops for per-register access during MMIO emulation.
+ * Each hypervisor backend provides its own implementation to avoid
+ * syncing the full CPU state for a single-register MMIO access.
+ */
+struct arm_emul_ops {
+ uint64_t (*get_reg)(CPUState *cpu, int reg);
+ void (*set_reg)(CPUState *cpu, int reg, uint64_t val);
+};
+
+int arm_emulate_mmio(CPUState *cpu, EsrEl2 syndrome, uint64_t gpa,
+ const struct arm_emul_ops *ops);
#define HELPER_H "tcg/helper-defs.h"
#include "exec/helper-proto.h.inc"
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index d88cbe7c82..18867795ab 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -13,6 +13,7 @@
#include "qemu/error-report.h"
#include "qemu/log.h"
+#include "syndrome.h"
#include "system/runstate.h"
#include "system/hvf.h"
#include "system/hvf_int.h"
@@ -37,6 +38,7 @@
#include "target/arm/multiprocessing.h"
#include "target/arm/gtimer.h"
#include "target/arm/trace.h"
+#include "target/arm/helper.h"
#include "trace.h"
#include "migration/vmstate.h"
@@ -2331,12 +2333,15 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcpu_exit_exception_t *excp)
{
CPUARMState *env = cpu_env(cpu);
ARMCPU *arm_cpu = env_archcpu(env);
- uint64_t syndrome = excp->syndrome;
- uint32_t ec = syn_get_ec(syndrome);
+ uint64_t syndrome;
+ uint32_t ec;
bool advance_pc = false;
hv_return_t r;
int ret = 0;
+ syndrome = excp->syndrome;
+ ec = syn_get_ec(syndrome);
+
switch (ec) {
case EC_SOFTWARESTEP: {
ret = EXCP_DEBUG;
@@ -2382,29 +2387,22 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcpu_exit_exception_t *excp)
break;
}
case EC_DATAABORT: {
- bool isv = FIELD_EX32(syndrome, DABORT_ISS, ISV);
- bool iswrite = FIELD_EX32(syndrome, DABORT_ISS, WNR);
- bool s1ptw = FIELD_EX32(syndrome, DABORT_ISS, S1PTW);
- bool sse = FIELD_EX32(syndrome, DABORT_ISS, SSE);
- uint32_t sas = FIELD_EX32(syndrome, DABORT_ISS, SAS);
- uint32_t len = 1 << sas;
- uint32_t srt = FIELD_EX32(syndrome, DABORT_ISS, SRT);
- uint32_t cm = FIELD_EX32(syndrome, DABORT_ISS, CM);
- uint64_t val = 0;
+ EsrEl2 esr_el2 = { .raw = syndrome };
+ IssDataAbort iss = { .raw = esr_el2.iss };
uint64_t ipa = excp->physical_address;
AddressSpace *as = cpu_get_address_space(cpu, ARMASIdx_NS);
- trace_hvf_data_abort(excp->virtual_address, ipa, isv,
- iswrite, s1ptw, len, srt);
+ trace_hvf_data_abort(excp->virtual_address, ipa, iss.isv,
+ iss.wnr, iss.s1ptw, 1ULL << iss.sas, iss.srt);
- if (cm) {
+ if (iss.cm) {
/* We don't cache MMIO regions */
advance_pc = true;
break;
}
/* Handle dirty page logging for ram. */
- if (iswrite) {
+ if (iss.wnr) {
hwaddr xlat;
MemoryRegion *mr = address_space_translate(as, ipa, &xlat,
NULL, true,
@@ -2431,28 +2429,25 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcpu_exit_exception_t *excp)
* TODO: If s1ptw, this is an error in the guest os page tables.
* Inject the exception into the guest.
*/
- assert(!s1ptw);
-
- /*
- * TODO: ISV will be 0 for SIMD or SVE accesses.
- * Inject the exception into the guest.
- */
- assert(isv);
+ assert(!iss.s1ptw);
/*
* Emulate MMIO.
* TODO: Inject faults for errors.
*/
- if (iswrite) {
- val = hvf_get_reg(cpu, srt);
- address_space_write(as, ipa, MEMTXATTRS_UNSPECIFIED, &val, len);
- } else {
- address_space_read(as, ipa, MEMTXATTRS_UNSPECIFIED, &val, len);
- if (sse) {
- val = sextract64(val, 0, len * 8);
- }
- hvf_set_reg(cpu, srt, val);
+
+ static const struct arm_emul_ops hvf_arm_emul_ops = {
+ .get_reg = hvf_get_reg,
+ .set_reg = hvf_set_reg,
+ };
+
+ ret = arm_emulate_mmio(cpu, esr_el2, ipa, &hvf_arm_emul_ops);
+ if (ret < 0) {
+ error_report("Failed to emulate MMIO, syndrome=0x%llx, gpa=0x%llx",
+ esr_el2.raw, ipa);
+ return -1;
}
+
advance_pc = true;
break;
}
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index 4d1f1c529e..b1a55735ac 100644
--- a/target/arm/syndrome.h
+++ b/target/arm/syndrome.h
@@ -106,6 +106,53 @@ typedef enum {
GCS_IT_GCSPOPX = 9,
} GCSInstructionType;
+typedef union {
+ uint64_t raw;
+ struct {
+ uint32_t iss:25;
+ uint32_t il:1;
+ uint32_t ec:6;
+ uint32_t iss2:5;
+ uint32_t _rsvd:27;
+ } QEMU_PACKED;
+} EsrEl2;
+
+typedef union {
+ uint32_t raw;
+ struct {
+ uint32_t dfsc:6;
+ uint32_t wnr:1;
+ uint32_t s1ptw:1;
+ uint32_t cm:1;
+ uint32_t ea:1;
+ uint32_t fnv:1;
+ uint32_t set:2;
+ uint32_t vncr:1;
+ uint32_t ar:1;
+ uint32_t sf:1;
+ uint32_t srt:5;
+ uint32_t sse:1;
+ uint32_t sas:2;
+ uint32_t isv:1;
+ uint32_t _unused:7;
+ } QEMU_PACKED;
+} IssDataAbort;
+
+typedef enum {
+ data_abort_lower = 36,
+ data_abort = 37,
+} ExceptionClass;
+
+#define ARM_EL_EC_LENGTH 6
+#define ARM_EL_EC_SHIFT 26
+#define ARM_EL_IL_SHIFT 25
+#define ARM_EL_ISV_SHIFT 24
+#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
+#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
+
+/* In the Data Abort syndrome */
+#define ARM_EL_VNCR (1 << 13)
+
static inline uint32_t syn_get_ec(uint32_t syn)
{
return FIELD_EX32(syn, SYNDROME, EC);
diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c
index 3079c6293c..c98450be99 100644
--- a/target/arm/whpx/whpx-all.c
+++ b/target/arm/whpx/whpx-all.c
@@ -28,6 +28,8 @@
#include "syndrome.h"
#include "target/arm/cpregs.h"
+#include "target/arm/helper.h"
+#include "target/arm/syndrome.h"
#include "internals.h"
#include "system/whpx-internal.h"
@@ -354,34 +356,23 @@ static void whpx_set_gp_reg(CPUState *cpu, int rt, uint64_t val)
static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx)
{
- uint64_t syndrome = ctx->Syndrome;
-
- bool isv = FIELD_EX32(syndrome, DABORT_ISS, ISV);
- bool iswrite = FIELD_EX32(syndrome, DABORT_ISS, WNR);
- bool sse = FIELD_EX32(syndrome, DABORT_ISS, SSE);
- uint32_t sas = FIELD_EX32(syndrome, DABORT_ISS, SAS);
- uint32_t len = 1 << sas;
- uint32_t srt = FIELD_EX32(syndrome, DABORT_ISS, SRT);
- uint32_t cm = FIELD_EX32(syndrome, DABORT_ISS, CM);
- uint64_t val = 0;
+ int ret = 0;
+ EsrEl2 esr = { .raw = ctx->Syndrome };
+ uint32_t cm = (esr.iss >> 8) & 0x1;
assert(syn_get_ec(syndrome) == EC_DATAABORT);
assert(!cm);
- assert(isv);
-
- if (iswrite) {
- val = whpx_get_gp_reg(cpu, srt);
- address_space_write(&address_space_memory,
- ctx->Gpa,
- MEMTXATTRS_UNSPECIFIED, &val, len);
- } else {
- address_space_read(&address_space_memory,
- ctx->Gpa,
- MEMTXATTRS_UNSPECIFIED, &val, len);
- if (sse) {
- val = sextract64(val, 0, len * 8);
- }
- whpx_set_gp_reg(cpu, srt, val);
+
+ static const struct arm_emul_ops whpx_arm_emul_ops = {
+ .get_reg = whpx_get_gp_reg,
+ .set_reg = whpx_set_gp_reg,
+ };
+
+ ret = arm_emulate_mmio(cpu, esr, ctx->Gpa, &whpx_arm_emul_ops);
+ if (ret < 0) {
+ error_report("WHPX: Failed to handle MMIO, syndrome=0x%llx, gpa=0x%llx",
+ esr.raw, ctx->Gpa);
+ return -1;
}
return 0;
--
2.45.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 12/15] target/arm/mshv: add vCPU run loop
2026-05-27 5:00 [PATCH v4 00/15] Add ARM64 support for MSHV accelerator Aastha Rawat
` (10 preceding siblings ...)
2026-05-27 5:00 ` [PATCH v4 11/15] target/arm: extract MMIO emulation logic for HVF & WHPX Aastha Rawat
@ 2026-05-27 5:00 ` Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 13/15] include/hw/hyperv: adjust hv_interrupt_control structure for arm64 Aastha Rawat
` (2 subsequent siblings)
14 siblings, 0 replies; 17+ messages in thread
From: Aastha Rawat @ 2026-05-27 5:00 UTC (permalink / raw)
To: qemu-devel
Cc: Magnus Kulke, Wei Liu, Paolo Bonzini, Marc-André Lureau,
Daniel P. Berrangé, Philippe Mathieu-Daudé,
Peter Maydell, Anirudh Rayabharam, Aastha Rawat, qemu-arm,
Alexander Graf, Pedro Barbuda, Mohamed Mediouni,
Doru Blânzeanu, Pierrick Bouvier, Magnus Kulke
From: "Anirudh Rayabharam (Microsoft)" <anirudh@anirudhrb.com>
Add the main vCPU run loop for MSHV using the MSHV_RUN_VP_IOCTL.
Handle MMIO exits by emulating the instruction using the syndrome
information from ESR_EL2.
Signed-off-by: Anirudh Rayabharam (Microsoft) <anirudh@anirudhrb.com>
---
include/hw/hyperv/hvgdk_mini.h | 44 +++++++++++++++
target/arm/mshv/mshv-all.c | 120 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 164 insertions(+)
diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h
index 7dc9511692..192d464d22 100644
--- a/include/hw/hyperv/hvgdk_mini.h
+++ b/include/hw/hyperv/hvgdk_mini.h
@@ -759,6 +759,50 @@ struct hv_x64_memory_intercept_message {
uint8_t instruction_bytes[16];
} QEMU_PACKED;
+union hv_arm64_vp_execution_state {
+ uint16_t as_uint16;
+ struct {
+ uint16_t cpl:2;
+ uint16_t debug_active:1;
+ uint16_t interruption_pending:1;
+ uint16_t vtl:4;
+ uint16_t virtualization_fault_active:1;
+ uint16_t reserved:7;
+ };
+};
+
+struct hv_arm64_intercept_message_header {
+ uint32_t vp_index;
+ uint8_t instruction_length;
+ uint8_t intercept_access_type;
+ union hv_arm64_vp_execution_state execution_state;
+ uint64_t pc;
+ uint64_t cpsr;
+};
+
+union hv_arm64_memory_access_info {
+ uint8_t as_uint8;
+ struct {
+ uint8_t gva_valid:1;
+ uint8_t gva_gpa_valid:1;
+ uint8_t hypercall_output_pending:1;
+ uint8_t reserved:5;
+ };
+};
+
+struct hv_arm64_memory_intercept_message {
+ struct hv_arm64_intercept_message_header header;
+ uint32_t cache_type; /* enum hv_cache_type */
+ uint8_t instruction_byte_count;
+ union hv_arm64_memory_access_info memory_access_info;
+ uint16_t reserved1;
+ uint8_t instruction_bytes[4];
+ uint32_t reserved2;
+ uint64_t guest_virtual_address;
+ uint64_t guest_physical_address;
+ uint64_t syndrome;
+};
+
union hv_message_flags {
uint8_t asu8;
struct {
diff --git a/target/arm/mshv/mshv-all.c b/target/arm/mshv/mshv-all.c
index 96a04df38a..22653eb366 100644
--- a/target/arm/mshv/mshv-all.c
+++ b/target/arm/mshv/mshv-all.c
@@ -20,6 +20,7 @@
#include "target/arm/cpu.h"
#include "target/arm/internals.h"
#include "target/arm/mshv_arm.h"
+#include "target/arm/helper.h"
#include "system/mshv.h"
#include "system/mshv_int.h"
@@ -147,8 +148,127 @@ int mshv_arch_put_registers(const CPUState *cpu)
return 0;
}
+static int set_memory_info(const struct hyperv_message *msg,
+ struct hv_arm64_memory_intercept_message *info)
+{
+ if (msg->header.message_type != HVMSG_GPA_INTERCEPT
+ && msg->header.message_type != HVMSG_UNMAPPED_GPA
+ && msg->header.message_type != HVMSG_UNACCEPTED_GPA) {
+ error_report("invalid message type");
+ return -1;
+ }
+ memcpy(info, msg->payload, sizeof(*info));
+
+ return 0;
+}
+
+int mshv_store_regs(CPUState *cpu)
+{
+ int ret;
+
+ ret = set_standard_regs(cpu);
+ if (ret < 0) {
+ error_report("Failed to store standard registers");
+ return -1;
+ }
+
+ return 0;
+}
+
+static uint64_t mshv_mmio_get_reg(CPUState *cpu, int reg_index)
+{
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
+ CPUARMState *env = &arm_cpu->env;
+ return reg_index < 31 ? env->xregs[reg_index] : 0ULL;
+}
+
+static void mshv_mmio_set_reg(CPUState *cpu, int reg_index, uint64_t val)
+{
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
+ CPUARMState *env = &arm_cpu->env;
+ if (reg_index < 31) {
+ env->xregs[reg_index] = val;
+ }
+}
+
+static int handle_unmapped_mem(int vm_fd, CPUState *cpu,
+ const struct hyperv_message *msg,
+ MshvVmExit *exit_reason)
+{
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
+ CPUARMState *env = &arm_cpu->env;
+ struct hv_arm64_memory_intercept_message info = { 0 };
+ int ret;
+ EsrEl2 syndrome;
+
+ ret = set_memory_info(msg, &info);
+ if (ret < 0) {
+ error_report("failed to convert message to memory info");
+ return -1;
+ }
+
+ syndrome.raw = info.syndrome;
+
+ ret = mshv_load_regs(cpu);
+ if (ret < 0) {
+ error_report("Failed to load registers");
+ return -1;
+ }
+
+ static const struct arm_emul_ops mshv_arm_emul_ops = {
+ .get_reg = mshv_mmio_get_reg,
+ .set_reg = mshv_mmio_set_reg,
+ };
+
+ ret = arm_emulate_mmio(cpu, syndrome, info.guest_physical_address,
+ &mshv_arm_emul_ops);
+ if (ret < 0) {
+ error_report("Failed to emulate with syndrome");
+ return -1;
+ }
+
+ /* Advance PC past the faulting instruction */
+ env->pc += (syndrome.il == 1) ? 4 : 2;
+
+ ret = mshv_store_regs(cpu);
+ if (ret < 0) {
+ error_report("Failed to store registers");
+ return -1;
+ }
+
+ *exit_reason = MshvVmExitIgnore;
+
+ return 0;
+}
+
int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *exit)
{
+ int ret;
+ int cpu_fd = mshv_vcpufd(cpu);
+
+ ret = ioctl(cpu_fd, MSHV_RUN_VP, msg);
+ if (ret < 0) {
+ *exit = MshvVmExitShutdown;
+ return ret;
+ }
+
+ switch (msg->header.message_type) {
+ case HVMSG_UNRECOVERABLE_EXCEPTION:
+ *exit = MshvVmExitShutdown;
+ break;
+ case HVMSG_GPA_INTERCEPT:
+ case HVMSG_UNMAPPED_GPA:
+ ret = handle_unmapped_mem(vm_fd, cpu, msg, exit);
+ if (ret < 0) {
+ error_report("failed to handle mmio");
+ return -1;
+ }
+ break;
+ default:
+ error_report("Unhandled message type: 0x%x", msg->header.message_type);
+ return -1;
+ }
+
return 0;
}
--
2.45.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 13/15] include/hw/hyperv: adjust hv_interrupt_control structure for arm64
2026-05-27 5:00 [PATCH v4 00/15] Add ARM64 support for MSHV accelerator Aastha Rawat
` (11 preceding siblings ...)
2026-05-27 5:00 ` [PATCH v4 12/15] target/arm/mshv: add vCPU run loop Aastha Rawat
@ 2026-05-27 5:00 ` Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 14/15] hw/intc,target/arm/mshv: add MSHV vGICv3 implementation Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 15/15] MAINTAINERS: updates for MSHV arm64 code Aastha Rawat
14 siblings, 0 replies; 17+ messages in thread
From: Aastha Rawat @ 2026-05-27 5:00 UTC (permalink / raw)
To: qemu-devel
Cc: Magnus Kulke, Wei Liu, Paolo Bonzini, Marc-André Lureau,
Daniel P. Berrangé, Philippe Mathieu-Daudé,
Peter Maydell, Anirudh Rayabharam, Aastha Rawat, qemu-arm,
Alexander Graf, Pedro Barbuda, Mohamed Mediouni,
Doru Blânzeanu, Pierrick Bouvier, Magnus Kulke
From: "Anirudh Rayabharam (Microsoft)" <anirudh@anirudhrb.com>
Add the arm64 specific fields to the hv_interrupt_control struct and
adjust the existing usage accordingly. mshv_request_interrupt is only
needed only for x86 so compile it out entirely for arm64.
Signed-off-by: Anirudh Rayabharam (Microsoft) <anirudh@anirudhrb.com>
---
accel/mshv/irq.c | 2 ++
include/hw/hyperv/hvgdk_mini.h | 25 +++++++++++++++++++++++++
include/system/mshv.h | 2 ++
3 files changed, 29 insertions(+)
diff --git a/accel/mshv/irq.c b/accel/mshv/irq.c
index 3c238c33c3..a391d7db86 100644
--- a/accel/mshv/irq.c
+++ b/accel/mshv/irq.c
@@ -310,6 +310,7 @@ int mshv_irqchip_update_msi_route(int virq, MSIMessage msg, PCIDevice *dev)
return 0;
}
+#if defined(__x86_64__)
int mshv_request_interrupt(MshvState *mshv_state, uint32_t interrupt_type, uint32_t vector,
uint32_t vp_index, bool logical_dest_mode,
bool level_triggered)
@@ -346,6 +347,7 @@ int mshv_request_interrupt(MshvState *mshv_state, uint32_t interrupt_type, uint3
}
return 0;
}
+#endif
void mshv_irqchip_commit_routes(void)
{
diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h
index 192d464d22..c3424b760a 100644
--- a/include/hw/hyperv/hvgdk_mini.h
+++ b/include/hw/hyperv/hvgdk_mini.h
@@ -510,13 +510,38 @@ typedef struct hv_input_set_vp_registers {
struct hv_register_assoc elements[];
} QEMU_PACKED hv_input_set_vp_registers;
+enum hv_interrupt_type {
+#if defined(__x86_64__)
+ HV_X64_INTERRUPT_TYPE_FIXED = 0x0000,
+ HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY = 0x0001,
+ HV_X64_INTERRUPT_TYPE_SMI = 0x0002,
+ HV_X64_INTERRUPT_TYPE_REMOTEREAD = 0x0003,
+ HV_X64_INTERRUPT_TYPE_NMI = 0x0004,
+ HV_X64_INTERRUPT_TYPE_INIT = 0x0005,
+ HV_X64_INTERRUPT_TYPE_SIPI = 0x0006,
+ HV_X64_INTERRUPT_TYPE_EXTINT = 0x0007,
+ HV_X64_INTERRUPT_TYPE_LOCALINT0 = 0x0008,
+ HV_X64_INTERRUPT_TYPE_LOCALINT1 = 0x0009,
+ HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A,
+#elif defined(__aarch64__)
+ HV_ARM64_INTERRUPT_TYPE_FIXED = 0x0000,
+ HV_ARM64_INTERRUPT_TYPE_MAXIMUM = 0x0008,
+#endif
+};
+
union hv_interrupt_control {
uint64_t as_uint64;
struct {
uint32_t interrupt_type; /* enum hv_interrupt type */
+#if defined(__x86_64__)
uint32_t level_triggered:1;
uint32_t logical_dest_mode:1;
uint32_t rsvd:30;
+#elif defined(__aarch64__)
+ uint32_t rsvd1:2;
+ uint32_t asserted:1;
+ uint32_t rsvd2:29;
+#endif
};
};
diff --git a/include/system/mshv.h b/include/system/mshv.h
index 75286baf16..0db18fcee9 100644
--- a/include/system/mshv.h
+++ b/include/system/mshv.h
@@ -47,10 +47,12 @@ extern bool mshv_allowed;
typedef struct MshvState MshvState;
extern MshvState *mshv_state;
+#if defined(__x86_64__)
/* interrupt */
int mshv_request_interrupt(MshvState *mshv_state, uint32_t interrupt_type, uint32_t vector,
uint32_t vp_index, bool logical_destination_mode,
bool level_triggered);
+#endif
int mshv_irqchip_add_msi_route(int vector, PCIDevice *dev);
int mshv_irqchip_update_msi_route(int virq, MSIMessage msg, PCIDevice *dev);
--
2.45.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 14/15] hw/intc,target/arm/mshv: add MSHV vGICv3 implementation
2026-05-27 5:00 [PATCH v4 00/15] Add ARM64 support for MSHV accelerator Aastha Rawat
` (12 preceding siblings ...)
2026-05-27 5:00 ` [PATCH v4 13/15] include/hw/hyperv: adjust hv_interrupt_control structure for arm64 Aastha Rawat
@ 2026-05-27 5:00 ` Aastha Rawat
2026-05-27 5:00 ` [PATCH v4 15/15] MAINTAINERS: updates for MSHV arm64 code Aastha Rawat
14 siblings, 0 replies; 17+ messages in thread
From: Aastha Rawat @ 2026-05-27 5:00 UTC (permalink / raw)
To: qemu-devel
Cc: Magnus Kulke, Wei Liu, Paolo Bonzini, Marc-André Lureau,
Daniel P. Berrangé, Philippe Mathieu-Daudé,
Peter Maydell, Anirudh Rayabharam, Aastha Rawat, qemu-arm,
Alexander Graf, Pedro Barbuda, Mohamed Mediouni,
Doru Blânzeanu, Pierrick Bouvier, Magnus Kulke
From: "Anirudh Rayabharam (Microsoft)" <anirudh@anirudhrb.com>
Add in-kernel GICv3 support for the MSHV accelerator, following the
same approach as the KVM and WHPX vGIC backends. The implementation
handles IRQ injection via the HVCALL_ASSERT_VIRTUAL_INTERRUPT hypercall.
Introduce mshv_arch_pre_init_vm(), an arch-specific hook called after
VM creation but before VM initialization, used on arm64 to configure
GIC partition properties (GICD base, ITS translater base, timer and PMU
PPI numbers). The x86 side provides a no-op stub.
Update the virt machine to treat MSHV like WHPX for GIC version
selection (GICv3 only) and MSI controller finalization (no ITS support).
Signed-off-by: Anirudh Rayabharam (Microsoft) <anirudh@anirudhrb.com>
---
accel/mshv/mshv-all.c | 5 +
hw/arm/virt.c | 12 +--
hw/intc/arm_gicv3_common.c | 6 +-
hw/intc/arm_gicv3_mshv.c | 181 +++++++++++++++++++++++++++++++++++++
hw/intc/meson.build | 1 +
include/hw/hyperv/hvgdk_mini.h | 2 +
include/hw/hyperv/hvhdk_mini.h | 6 ++
include/hw/intc/arm_gicv3_common.h | 2 +-
include/system/mshv_int.h | 1 +
target/arm/mshv/mshv-all.c | 61 +++++++++++++
target/i386/mshv/mshv-all.c | 5 +
11 files changed, 270 insertions(+), 12 deletions(-)
diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c
index 61a9d58546..2cad2f0619 100644
--- a/accel/mshv/mshv-all.c
+++ b/accel/mshv/mshv-all.c
@@ -200,6 +200,11 @@ static int create_vm(int mshv_fd, int *vm_fd)
return -1;
}
+ ret = mshv_arch_pre_init_vm(*vm_fd);
+ if (ret < 0) {
+ return -1;
+ }
+
ret = initialize_vm(*vm_fd);
if (ret < 0) {
return -1;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 7803c73b0d..026de919c7 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2663,7 +2663,7 @@ static void finalize_gic_version(VirtMachineState *vms)
/* KVM w/o kernel irqchip can only deal with GICv2 */
gics_supported |= VIRT_GIC_VERSION_2_MASK;
accel_name = "KVM with kernel-irqchip=off";
- } else if (whpx_enabled()) {
+ } else if (whpx_enabled() || mshv_enabled()) {
gics_supported |= VIRT_GIC_VERSION_3_MASK;
} else if (hvf_enabled()) {
if (!hvf_irqchip_in_kernel()) {
@@ -2717,7 +2717,7 @@ static void finalize_msi_controller(VirtMachineState *vms)
if (vms->msi_controller == VIRT_MSI_CTRL_AUTO) {
if (vms->gic_version == VIRT_GIC_VERSION_2) {
vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
- } else if (whpx_enabled()) {
+ } else if (whpx_enabled() || mshv_enabled()) {
vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
} else if (hvf_enabled() && hvf_irqchip_in_kernel()) {
vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
@@ -2739,12 +2739,8 @@ static void finalize_msi_controller(VirtMachineState *vms)
error_report("GICv2 + ITS is an invalid configuration.");
exit(1);
}
- if (vms->gic_version == VIRT_GIC_VERSION_5) {
- error_report("GICv5 + ITS is not yet implemented.");
- exit(1);
- }
- if (whpx_enabled()) {
- error_report("ITS not supported on WHPX.");
+ if (mshv_enabled()) {
+ error_report("ITS not supported on MSHV.");
exit(1);
}
if (hvf_enabled() && hvf_irqchip_in_kernel()) {
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index f7ba74e6d5..bfed6735b0 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -33,7 +33,7 @@
#include "hw/arm/linux-boot-if.h"
#include "system/kvm.h"
#include "system/whpx.h"
-#include "system/hvf.h"
+#include "system/mshv.h"
static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs)
@@ -660,8 +660,8 @@ const char *gicv3_class_name(void)
return "kvm-arm-gicv3";
} else if (whpx_enabled()) {
return TYPE_WHPX_GICV3;
- } else if (hvf_enabled() && hvf_irqchip_in_kernel()) {
- return TYPE_HVF_GICV3;
+ } else if (mshv_enabled()) {
+ return TYPE_MSHV_GICV3;
} else {
if (kvm_enabled()) {
error_report("Userspace GICv3 is not supported with KVM");
diff --git a/hw/intc/arm_gicv3_mshv.c b/hw/intc/arm_gicv3_mshv.c
new file mode 100644
index 0000000000..a87819a5ba
--- /dev/null
+++ b/hw/intc/arm_gicv3_mshv.c
@@ -0,0 +1,181 @@
+/*
+ * ARM Generic Interrupt Controller using MSHV in-kernel support
+ *
+ * Copyright Microsoft, Corp. 2026
+ * Based on vGICv3 KVM code by Pavel Fedin
+ *
+ * Authors:
+ * Aastha Rawat <aastharawat@microsoft.com>
+ * Anirudh Rayabharam (Microsoft) <anirudh@anirudhrb.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+#include "hw/intc/arm_gicv3_common.h"
+#include "migration/blocker.h"
+#include "target/arm/cpregs.h"
+#include "hw/hyperv/hvgdk_mini.h"
+#include "system/mshv.h"
+#include "system/mshv_int.h"
+
+struct MSHVARMGICv3Class {
+ ARMGICv3CommonClass parent_class;
+ DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
+};
+
+OBJECT_DECLARE_TYPE(GICv3State, MSHVARMGICv3Class, MSHV_GICV3)
+
+static void mshv_gicv3_get(GICv3State *s)
+{
+}
+
+static void mshv_gicv3_put(GICv3State *s)
+{
+}
+
+static void mshv_gicv3_reset_hold(Object *obj, ResetType type)
+{
+ GICv3State *s = ARM_GICV3_COMMON(obj);
+ MSHVARMGICv3Class *mgc = MSHV_GICV3_GET_CLASS(s);
+
+ if (mgc->parent_phases.hold) {
+ mgc->parent_phases.hold(obj, type);
+ }
+
+ mshv_gicv3_put(s);
+}
+
+static void mshv_gicv3_set_irq(void *opaque, int irq, int level)
+{
+ int ret;
+ GICv3State *s = (GICv3State *)opaque;
+ int vm_fd = mshv_state->vm;
+ struct hv_input_assert_virtual_interrupt arg = {0};
+ struct mshv_root_hvcall args = {0};
+ union hv_interrupt_control control = {
+ .interrupt_type = HV_ARM64_INTERRUPT_TYPE_FIXED,
+ .rsvd1 = 0,
+ .asserted = level,
+ .rsvd2 = 0
+ };
+
+ if (irq >= s->num_irq) {
+ return;
+ }
+
+ arg.control = control;
+ arg.vector = GIC_INTERNAL + irq;
+
+ args.code = HVCALL_ASSERT_VIRTUAL_INTERRUPT;
+ args.in_sz = sizeof(arg);
+ args.in_ptr = (uint64_t)&arg;
+
+ ret = mshv_hvcall(vm_fd, &args);
+ if (ret < 0) {
+ error_report("Failed to set GICv3 IRQ %d to level %d", irq, level);
+ }
+}
+
+static void mshv_gicv3_realize(DeviceState *dev, Error **errp)
+{
+ ERRP_GUARD();
+ GICv3State *s = MSHV_GICV3(dev);
+ MSHVARMGICv3Class *mgc = MSHV_GICV3_GET_CLASS(s);
+ int i, ret;
+
+ mgc->parent_realize(dev, errp);
+ if (*errp) {
+ return;
+ }
+
+ if (s->revision != 3) {
+ error_setg(errp, "unsupported GIC revision %d for platform GIC",
+ s->revision);
+ return;
+ }
+
+ if (s->security_extn) {
+ error_setg(errp, "the platform vGICv3 does not implement the "
+ "security extensions");
+ return;
+ }
+
+ if (s->nmi_support) {
+ error_setg(errp, "NMI is not supported with the platform GIC");
+ return;
+ }
+
+ if (s->nb_redist_regions > 1) {
+ error_setg(errp, "Multiple VGICv3 redistributor regions are not "
+ "supported by MSHV");
+ error_append_hint(errp, "A maximum of %d VCPUs can be used",
+ s->redist_region_count[0]);
+ return;
+ }
+
+ gicv3_init_irqs_and_mmio(s, mshv_gicv3_set_irq, NULL);
+
+ for (i = 0; i < s->num_cpu; i++) {
+ CPUState *cpu_state = qemu_get_cpu(i);
+
+ hv_register_assoc gicr_base = {
+ .name = HV_ARM64_REGISTER_GICR_BASE_GPA,
+ .value = {
+ .reg64 = 0x080A0000 + (GICV3_REDIST_SIZE * i)
+ }
+ };
+
+ ret = mshv_set_generic_regs(cpu_state, &gicr_base, 1);
+ if (ret < 0) {
+ error_setg(errp, "Failed to set GICR base for CPU %d", i);
+ return;
+ }
+ }
+
+ if (s->maint_irq) {
+ error_setg(errp,
+ "Nested virtualisation not currently supported by MSHV");
+ return;
+ }
+
+ error_setg(&s->migration_blocker,
+ "Live migration disabled because GIC state save/restore not supported on MSHV");
+ if (migrate_add_blocker(&s->migration_blocker, errp) < 0) {
+ error_report_err(*errp);
+ }
+}
+
+static void mshv_gicv3_class_init(ObjectClass *klass, const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);
+ MSHVARMGICv3Class *mgc = MSHV_GICV3_CLASS(klass);
+
+ agcc->pre_save = mshv_gicv3_get;
+ agcc->post_load = mshv_gicv3_put;
+
+ device_class_set_parent_realize(dc, mshv_gicv3_realize,
+ &mgc->parent_realize);
+ resettable_class_set_parent_phases(rc, NULL, mshv_gicv3_reset_hold, NULL,
+ &mgc->parent_phases);
+}
+
+static const TypeInfo mshv_arm_gicv3_info = {
+ .name = TYPE_MSHV_GICV3,
+ .parent = TYPE_ARM_GICV3_COMMON,
+ .instance_size = sizeof(GICv3State),
+ .class_init = mshv_gicv3_class_init,
+ .class_size = sizeof(MSHVARMGICv3Class),
+};
+
+static void mshv_gicv3_register_types(void)
+{
+ type_register_static(&mshv_arm_gicv3_info);
+}
+
+type_init(mshv_gicv3_register_types)
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index fac2d228f9..57505303e2 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -49,6 +49,7 @@ specific_ss.add(when: ['CONFIG_WHPX', 'TARGET_AARCH64'], if_true: files('arm_gic
specific_ss.add(when: ['CONFIG_HVF', 'CONFIG_ARM_GICV3'], if_true: files('arm_gicv3_hvf.c'))
stub_ss.add(files('arm_gicv3_hvf_stub.c'))
specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
+specific_ss.add(when: ['CONFIG_MSHV', 'TARGET_AARCH64'], if_true: files('arm_gicv3_mshv.c'))
arm_common_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c'))
specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c'))
diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h
index c3424b760a..e8c448b32e 100644
--- a/include/hw/hyperv/hvgdk_mini.h
+++ b/include/hw/hyperv/hvgdk_mini.h
@@ -66,6 +66,8 @@ typedef enum hv_register_name {
HV_ARM64_REGISTER_MIDR_EL1 = 0x00040051,
HV_ARM64_REGISTER_MPIDR_EL1 = 0x00040001,
+ HV_ARM64_REGISTER_GICR_BASE_GPA = 0x00063000,
+
#elif defined(__x86_64__)
/* X64 User-Mode Registers */
HV_X64_REGISTER_RAX = 0x00020000,
diff --git a/include/hw/hyperv/hvhdk_mini.h b/include/hw/hyperv/hvhdk_mini.h
index 9c2f3cf5ae..4d78fa0677 100644
--- a/include/hw/hyperv/hvhdk_mini.h
+++ b/include/hw/hyperv/hvhdk_mini.h
@@ -62,6 +62,12 @@ enum hv_partition_property_code {
HV_PARTITION_PROPERTY_ISOLATION_POLICY = 0x00050014,
HV_PARTITION_PROPERTY_UNIMPLEMENTED_MSR_ACTION = 0x00050017,
HV_PARTITION_PROPERTY_SEV_VMGEXIT_OFFLOADS = 0x00050022,
+ HV_PARTITION_PROPERTY_GICD_BASE_ADDRESS = 0x00050028,
+ HV_PARTITION_PROPERTY_GITS_TRANSLATER_BASE_ADDRESS = 0x00050029,
+ HV_PARTITION_PROPERTY_GIC_LPI_INT_ID_BITS = 0x0005002A,
+ HV_PARTITION_PROPERTY_GIC_PPI_OVERFLOW_INTERRUPT_FROM_CNTV = 0x0005002B,
+ HV_PARTITION_PROPERTY_GIC_PPI_OVERFLOW_INTERRUPT_FROM_CNTP = 0x0005002C,
+ HV_PARTITION_PROPERTY_GIC_PPI_PERFORMANCE_MONITORS_INTERRUPT = 0x0005002D,
/* Compatibility properties */
HV_PARTITION_PROPERTY_PROCESSOR_VENDOR = 0x00060000,
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index 03ab3e8f2f..2eb5219a54 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -315,7 +315,7 @@ DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3CommonClass,
/* Types for GICv3 kernel-irqchip */
#define TYPE_WHPX_GICV3 "whpx-arm-gicv3"
-#define TYPE_HVF_GICV3 "hvf-arm-gicv3"
+#define TYPE_MSHV_GICV3 "mshv-arm-gicv3"
struct ARMGICv3CommonClass {
/*< private >*/
diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h
index 62fad48895..3e88f6b178 100644
--- a/include/system/mshv_int.h
+++ b/include/system/mshv_int.h
@@ -96,6 +96,7 @@ void mshv_arch_destroy_vcpu(CPUState *cpu);
void mshv_arch_amend_proc_features(
union hv_partition_synthetic_processor_features *features);
int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd);
+int mshv_arch_pre_init_vm(int vm_fd);
int mshv_arch_post_init_vm(int vm_fd);
void mshv_setup_hvcall_args(AccelCPUState *state);
diff --git a/target/arm/mshv/mshv-all.c b/target/arm/mshv/mshv-all.c
index 22653eb366..88531f6e73 100644
--- a/target/arm/mshv/mshv-all.c
+++ b/target/arm/mshv/mshv-all.c
@@ -290,6 +290,67 @@ void mshv_arch_destroy_vcpu(CPUState *cpu)
state->hvcall_args = (MshvHvCallArgs){0};
}
+static int set_partition_prop(int vm_fd, uint32_t prop_code,
+ uint64_t prop_value)
+{
+ int ret;
+ struct hv_input_set_partition_property in = {0};
+ in.property_code = prop_code;
+ in.property_value = prop_value;
+
+ struct mshv_root_hvcall args = {0};
+ args.code = HVCALL_SET_PARTITION_PROPERTY;
+ args.in_sz = sizeof(in);
+ args.in_ptr = (uint64_t)∈
+
+ ret = mshv_hvcall(vm_fd, &args);
+ if (ret < 0) {
+ error_report("Failed to set partition property code %u", prop_code);
+ return -1;
+ }
+
+ return 0;
+}
+
+int mshv_arch_pre_init_vm(int vm_fd)
+{
+ int ret;
+ VirtMachineState *vms = VIRT_MACHINE(qdev_get_machine());
+
+ ret = set_partition_prop(vm_fd,
+ HV_PARTITION_PROPERTY_GICD_BASE_ADDRESS,
+ vms->memmap[VIRT_GIC_DIST].base);
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = set_partition_prop(vm_fd,
+ HV_PARTITION_PROPERTY_GITS_TRANSLATER_BASE_ADDRESS,
+ vms->memmap[VIRT_GIC_ITS].base);
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = set_partition_prop(vm_fd,
+ HV_PARTITION_PROPERTY_GIC_LPI_INT_ID_BITS,
+ 0);
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = set_partition_prop(vm_fd,
+ HV_PARTITION_PROPERTY_GIC_PPI_OVERFLOW_INTERRUPT_FROM_CNTV,
+ ARCH_TIMER_VIRT_IRQ);
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = set_partition_prop(vm_fd,
+ HV_PARTITION_PROPERTY_GIC_PPI_PERFORMANCE_MONITORS_INTERRUPT,
+ VIRTUAL_PMU_IRQ);
+
+ return ret;
+}
static uint32_t mshv_arm_get_ipa_bit_size(int mshv_fd)
{
diff --git a/target/i386/mshv/mshv-all.c b/target/i386/mshv/mshv-all.c
index f0b43aa86f..ce8b426ea4 100644
--- a/target/i386/mshv/mshv-all.c
+++ b/target/i386/mshv/mshv-all.c
@@ -39,6 +39,11 @@ int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd)
return 0;
}
+int mshv_arch_pre_init_vm(int vm_fd)
+{
+ return 0;
+}
+
/*
* Default Microsoft Hypervisor behavior for unimplemented MSR is to send a
* fault to the guest if it tries to access it. It is possible to override
--
2.45.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v4 15/15] MAINTAINERS: updates for MSHV arm64 code
2026-05-27 5:00 [PATCH v4 00/15] Add ARM64 support for MSHV accelerator Aastha Rawat
` (13 preceding siblings ...)
2026-05-27 5:00 ` [PATCH v4 14/15] hw/intc,target/arm/mshv: add MSHV vGICv3 implementation Aastha Rawat
@ 2026-05-27 5:00 ` Aastha Rawat
14 siblings, 0 replies; 17+ messages in thread
From: Aastha Rawat @ 2026-05-27 5:00 UTC (permalink / raw)
To: qemu-devel
Cc: Magnus Kulke, Wei Liu, Paolo Bonzini, Marc-André Lureau,
Daniel P. Berrangé, Philippe Mathieu-Daudé,
Peter Maydell, Anirudh Rayabharam, Aastha Rawat, qemu-arm,
Alexander Graf, Pedro Barbuda, Mohamed Mediouni,
Doru Blânzeanu, Pierrick Bouvier, Magnus Kulke
From: "Anirudh Rayabharam (Microsoft)" <anirudh@anirudhrb.com>
Add myself and Aastha Rawat as maintainers.
Add Magnus Kulke as reviewer.
Signed-off-by: Anirudh Rayabharam (Microsoft) <anirudh@anirudhrb.com>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index cd5c4831e2..761f802a98 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -611,6 +611,14 @@ R: Doru Blânzeanu <dblanzeanu@linux.microsoft.com>
S: Supported
F: target/i386/mshv/
+ARM64 MSHV CPUs
+M: Anirudh Rayabharam <anirudh@anirudhrb.com>
+M: Aastha Rawat <aastharawat@linux.microsoft.com>
+R: Magnus Kulke <magnus.kulke@linux.microsoft.com>
+S: Supported
+F: target/arm/mshv/
+F: hw/intc/arm_gicv3_mshv.c
+
X86 Instruction Emulator
M: Roman Bolshakov <rbolshakov@ddn.com>
R: Phil Dennis-Jordan <phil@philjordan.eu>
--
2.45.4
^ permalink raw reply related [flat|nested] 17+ messages in thread