[PATCH v2 0/2] Add support for Renesas RZ/G3L LVDS encoder

[PATCH v2 0/2] Add support for Renesas RZ/G3L LVDS encoder

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add support for the RZ/G3L LVDS encoder driver. It operates in single-link
mode with 4 lanes (Data) + 1 lane (Clock) and supports pixel clock rates
from 25 to 87 MHz. The LVDS module cannot be used at the same time as
MIPI-DSI. However, LVDS and the DSI interface share a peripheral clock and
the MIPI_DSI_PRESET_N reset signal. Also, the MIPI_DSI_CMN_RSTB and
MIPI_DSI_ARESET_N reset signals must be asserted before using the LVDS
module.

v2->v3:
 * Dropped patch#1 as it is accepted.
 * Replace drm_atomic_state with drm_atomic_commit in
   rzg3l_lvds_atomic_{en,dis}able().
 * Drop local variable ret and dev_err() messages in
   rzg3l_lvds_atomic_enable(); use WARN_ON() instead to
   capture unexpected failures since atomic_enable should not fail.
 * Drop local variable next_bridge from rzg3l_lvds_probe().
v1->v2:
 * Collected the tags for binding patches.
 * Dropped unused function rzg3l_lvds_is_connected() and removed the 
   corresponding header file rzg3l_lvds.h
 * Dropped next_bridge from struct rzg3l_lvds instead using bridge's
   next_bridge.
 * Replaced pm_runtime_resume_and_get()->pm_runtime_get_sync() as
   atomic_enable doesn't fail and for each enable there always will be an
   atomic_disable() call.
 * Started using DEFINE_RUNTIME_DEV_PM_OPS for PM callback.
 * Replaced rzg3l_lvds_parse_dt() with devm_drm_of_get_bridge() in probe()
 * Started using reset_control_bulk_*() in rzg3l_lvds_pm_runtime_{suspend,
   resume}().

Biju Das (2):
  dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder
  drm: renesas: rz-du: Add support for RZ/G3L LVDS encoder

 .../bridge/renesas,r9a08g046-lvds.yaml        | 128 ++++++++
 drivers/gpu/drm/renesas/rz-du/Kconfig         |  13 +
 drivers/gpu/drm/renesas/rz-du/Makefile        |   1 +
 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c    | 277 ++++++++++++++++++
 .../gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h   |  26 ++
 5 files changed, 445 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
 create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c
 create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h

-- 
2.43.0

[PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Document the LVDS encoder IP found on the RZ/G3L SoC. It supports
single-link mode. LVDS and the DSI interface share a peripheral clock and
the MIPI_DSI_PRESET_N reset signal. However, the LVDS module cannot be
used at the same time as MIPI-DSI.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change.
v1->v2:
 * Collected tag.
---
 .../bridge/renesas,r9a08g046-lvds.yaml        | 128 ++++++++++++++++++
 1 file changed, 128 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
new file mode 100644
index 000000000000..b1f6d020ae7b
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
@@ -0,0 +1,128 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/renesas,r9a08g046-lvds.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G3L LVDS Encoder
+
+maintainers:
+  - Biju Das <biju.das.jz@bp.renesas.com>
+  - Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
+
+description: |
+  This binding describe the LVDS encoder embedded in the Renesas RZ/G3L
+  SoC. The encoder can operate in LVDS Single-link mode with 4 lanes
+  (Data) + 1 lane (Clock).
+
+properties:
+  compatible:
+    const: renesas,r9a08g046-lvds
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Peripheral clock
+      - description: PHY clock
+      - description: Dot clock
+
+  clock-names:
+    items:
+      - const: pclk
+      - const: phyclk
+      - const: dotclk
+
+  resets:
+    items:
+      - description: LVDS_RESET_N
+      - description: MIPI_DSI_PRESET_N
+      - description: MIPI_DSI_CMN_RSTB
+      - description: MIPI_DSI_ARESET_N
+
+  reset-names:
+    items:
+      - const: lvdrst
+      - const: prst
+      - const: rst
+      - const: arst
+
+  power-domains:
+    maxItems: 1
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Input channel, directly connected to the Display Unit.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: |
+          Output channel, directly connected to the LVDS panel or bridge.
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - power-domains
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
+
+    lvds-cmn@108a0000 {
+        compatible = "renesas,r9a08g046-lvds-cmn",
+                     "simple-mfd", "syscon";
+        reg = <0x108a0000 0x10000>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        lvds0: lvds@10 {
+            compatible = "renesas,r9a08g046-lvds";
+            reg = <0x10 0x8>;
+            clocks = <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>,
+                     <&cpg CPG_MOD R9A08G046_LVDS_PLLCLK>,
+                     <&cpg CPG_MOD R9A08G046_LVDS_CLK_DOT0>;
+            clock-names = "pclk", "phyclk", "dotclk";
+            resets = <&cpg R9A08G046_LVDS_RESET_N>,
+                     <&cpg R9A08G046_MIPI_DSI_PRESET_N>,
+                     <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>,
+                     <&cpg R9A08G046_MIPI_DSI_ARESET_N>;
+            reset-names = "lvdrst", "prst", "rst", "arst";
+            power-domains = <&cpg>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+                    lvds0_in: endpoint {
+                        remote-endpoint = <&du_out_lvds0>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+                    lvds0_out: endpoint {
+                        remote-endpoint = <&panel_in>;
+                    };
+                };
+            };
+        };
+    };
+...
-- 
2.43.0

[PATCH v2 2/2] drm: renesas: rz-du: Add support for RZ/G3L LVDS encoder

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add support for the RZ/G3L LVDS encoder driver. It operates in single-link
mode with 4 lanes (Data) + 1 lane (Clock) and supports pixel clock rates
from 25 to 87 MHz. The LVDS module cannot be used at the same time as
MIPI-DSI. However, LVDS and the DSI interface share a peripheral clock and
the MIPI_DSI_PRESET_N reset signal. Also, the MIPI_DSI_CMN_RSTB and
MIPI_DSI_ARESET_N reset signals must be asserted before using the LVDS
module.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * Replace drm_atomic_state with drm_atomic_commit in
   rzg3l_lvds_atomic_{en,dis}able().
 * Drop local variable ret and dev_err() messages in
   rzg3l_lvds_atomic_enable(); use WARN_ON() instead to
   capture unexpected failures since atomic_enable should not fail.
 * Drop local variable next_bridge from rzg3l_lvds_probe().
v1->v2:
 * Dropped unused function rzg3l_lvds_is_connected() and removed the 
   corresponding header file rzg3l_lvds.h
 * Dropped next_bridge from struct rzg3l_lvds instead using bridge's
   next_bridge.
 * Replaced pm_runtime_resume_and_get()->pm_runtime_get_sync() as
   atomic_enable doesn't fail and for each enable there always will be an
   atomic_disable() call.
 * Started using DEFINE_RUNTIME_DEV_PM_OPS for PM callback.
 * Replaced rzg3l_lvds_parse_dt() with devm_drm_of_get_bridge() in probe()
 * Started using reset_control_bulk_*() in rzg3l_lvds_pm_runtime_{suspend,
   resume}()
---
 drivers/gpu/drm/renesas/rz-du/Kconfig         |  13 +
 drivers/gpu/drm/renesas/rz-du/Makefile        |   1 +
 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c    | 277 ++++++++++++++++++
 .../gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h   |  26 ++
 4 files changed, 317 insertions(+)
 create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c
 create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h

diff --git a/drivers/gpu/drm/renesas/rz-du/Kconfig b/drivers/gpu/drm/renesas/rz-du/Kconfig
index 7f2ef7137ae5..cbfc7b6bccb8 100644
--- a/drivers/gpu/drm/renesas/rz-du/Kconfig
+++ b/drivers/gpu/drm/renesas/rz-du/Kconfig
@@ -26,3 +26,16 @@ config DRM_RZG2L_MIPI_DSI
 	def_tristate DRM_RZG2L_DU
 	depends on DRM_RZG2L_USE_MIPI_DSI
 	select DRM_MIPI_DSI
+
+config DRM_RZG3L_USE_LVDS
+	bool "RZ/G3L DU LVDS Encoder Support"
+	depends on DRM_BRIDGE && OF
+	default DRM_RZG2L_DU
+	help
+	  Enable support for the RZ/G3L Display Unit embedded LVDS encoders.
+
+config DRM_RZG3L_LVDS
+	def_tristate DRM_RZG2L_DU
+	depends on DRM_RZG3L_USE_LVDS
+	select DRM_KMS_HELPER
+	select DRM_PANEL
diff --git a/drivers/gpu/drm/renesas/rz-du/Makefile b/drivers/gpu/drm/renesas/rz-du/Makefile
index 2987900ea6b6..46decb7ac4f1 100644
--- a/drivers/gpu/drm/renesas/rz-du/Makefile
+++ b/drivers/gpu/drm/renesas/rz-du/Makefile
@@ -8,3 +8,4 @@ rzg2l-du-drm-$(CONFIG_VIDEO_RENESAS_VSP1)	+= rzg2l_du_vsp.o
 obj-$(CONFIG_DRM_RZG2L_DU)		+= rzg2l-du-drm.o
 
 obj-$(CONFIG_DRM_RZG2L_MIPI_DSI)	+= rzg2l_mipi_dsi.o
+obj-$(CONFIG_DRM_RZG3L_LVDS)		+= rzg3l_lvds.o
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c
new file mode 100644
index 000000000000..a51c3e5a2efe
--- /dev/null
+++ b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G3L LVDS Encoder Driver
+ *
+ * Copyright (C) 2026 Renesas Electronics Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/media-bus-format.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_probe_helper.h>
+
+#include "rzg3l_lvds_regs.h"
+
+enum rzg3l_lvds_mode {
+	RZG3L_LVDS_MODE_JEIDA = 0,
+	RZG3L_LVDS_MODE_JEIDA_MIRROR = 1,
+	RZG3L_LVDS_MODE_MODE2 = 2,
+	RZG3L_LVDS_MODE_MODE2_MIRROR = 3,
+	RZG3L_LVDS_MODE_VESA = 4,
+	RZG3L_LVDS_MODE_VESA_MIRROR = 5,
+	RZG3L_LVDS_MODE_MODE6 = 6,
+	RZG3L_LVDS_MODE_MODE6_MIRROR = 7,
+};
+
+struct rzg3l_lvds {
+	struct device *dev;
+	struct reset_control *prstc;
+	struct reset_control *lvd_rstc;
+	struct regmap *regmap;
+	struct drm_bridge bridge;
+};
+
+#define bridge_to_rzg3l_lvds(b) \
+	container_of(b, struct rzg3l_lvds, bridge)
+
+/* -----------------------------------------------------------------------------
+ * Bridge
+ */
+
+static void rzg3l_lvds_atomic_enable(struct drm_bridge *bridge,
+				     struct drm_atomic_commit *state)
+{
+	struct rzg3l_lvds *lvds = bridge_to_rzg3l_lvds(bridge);
+	const struct drm_bridge_state *bridge_state;
+	u32 fmt;
+
+	/* Get the LVDS format from the bridge state. */
+	bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
+	if (WARN_ON(!bridge_state))
+		return;
+
+	switch (bridge_state->output_bus_cfg.format) {
+	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+		fmt = RZG3L_LVDS_MODE_JEIDA;
+		break;
+	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+		fmt = RZG3L_LVDS_MODE_VESA;
+		break;
+	default:
+		fmt = RZG3L_LVDS_MODE_VESA;
+		dev_warn(lvds->dev, "Unsupported bus fmt 0x%04x\n",
+			 bridge_state->output_bus_cfg.format);
+		break;
+	}
+
+	if (WARN_ON(pm_runtime_get_sync(lvds->dev) < 0))
+		return;
+
+	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
+			   LVDS_0_PHY_CH_EN_BGR, LVDS_0_PHY_CH_EN_BGR);
+	fsleep(20);
+
+	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
+			   LVDS_0_PHY_CH_EN_LDO, LVDS_0_PHY_CH_EN_LDO);
+	fsleep(10);
+
+	regmap_write(lvds->regmap, LVDS_CMN, LVDS_CMN_RST_PHY0_SEL);
+	regmap_update_bits(lvds->regmap, LVDS_0_CTL_OFFSET,
+			   LVDS_0_CTL_FMT_SEL_MSK,
+			   FIELD_PREP(LVDS_0_CTL_FMT_SEL_MSK, fmt));
+	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
+			   LVDS_0_PHY_CH_IO_EN_MSK, LVDS_0_PHY_CH_IO_EN);
+	regmap_write(lvds->regmap, LVDS_CMN,
+		     LVDS_CMN_RST_PHY0_SEL | LVDS_CMN_PHY_RESET);
+	fsleep(100);
+}
+
+static void rzg3l_lvds_atomic_disable(struct drm_bridge *bridge,
+				      struct drm_atomic_commit *state)
+{
+	struct rzg3l_lvds *lvds = bridge_to_rzg3l_lvds(bridge);
+
+	regmap_update_bits(lvds->regmap, LVDS_CMN, LVDS_CMN_PHY_RESET, 0);
+	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
+			   LVDS_0_PHY_CH_IO_EN_MSK, 0);
+	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
+			   LVDS_0_PHY_CH_EN_LDO, 0);
+	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
+			   LVDS_0_PHY_CH_EN_BGR, 0);
+
+	pm_runtime_put(lvds->dev);
+}
+
+static int rzg3l_lvds_attach(struct drm_bridge *bridge,
+			     struct drm_encoder *encoder,
+			     enum drm_bridge_attach_flags flags)
+{
+	struct rzg3l_lvds *lvds = bridge_to_rzg3l_lvds(bridge);
+
+	if (!lvds->bridge.next_bridge)
+		return 0;
+
+	return drm_bridge_attach(encoder, lvds->bridge.next_bridge, bridge, flags);
+}
+
+static enum drm_mode_status
+rzg3l_lvds_bridge_mode_valid(struct drm_bridge *bridge,
+			     const struct drm_display_info *info,
+			     const struct drm_display_mode *mode)
+{
+	if (mode->clock > 87000)
+		return MODE_CLOCK_HIGH;
+
+	if (mode->clock < 25000)
+		return MODE_CLOCK_LOW;
+
+	return MODE_OK;
+}
+
+static const struct drm_bridge_funcs rzg3l_lvds_bridge_ops = {
+	.attach = rzg3l_lvds_attach,
+	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+	.atomic_reset = drm_atomic_helper_bridge_reset,
+	.atomic_enable = rzg3l_lvds_atomic_enable,
+	.atomic_disable = rzg3l_lvds_atomic_disable,
+	.mode_valid = rzg3l_lvds_bridge_mode_valid,
+};
+
+/* -----------------------------------------------------------------------------
+ * Power Management
+ */
+
+static int rzg3l_lvds_pm_runtime_suspend(struct device *dev)
+{
+	struct rzg3l_lvds *lvds = dev_get_drvdata(dev);
+	struct reset_control_bulk_data resets[] = {
+		{ .rstc = lvds->lvd_rstc },
+		{ .rstc = lvds->prstc },
+	};
+
+	return reset_control_bulk_assert(ARRAY_SIZE(resets), resets);
+}
+
+static int rzg3l_lvds_pm_runtime_resume(struct device *dev)
+{
+	struct rzg3l_lvds *lvds = dev_get_drvdata(dev);
+	struct reset_control_bulk_data resets[] = {
+		{ .rstc = lvds->lvd_rstc },
+		{ .rstc = lvds->prstc },
+	};
+
+	return reset_control_bulk_deassert(ARRAY_SIZE(resets), resets);
+}
+
+static DEFINE_RUNTIME_DEV_PM_OPS(rzg3l_lvds_pm_ops,
+				 rzg3l_lvds_pm_runtime_suspend,
+				 rzg3l_lvds_pm_runtime_resume, NULL);
+
+/* -----------------------------------------------------------------------------
+ * Probe & Remove
+ */
+
+static int rzg3l_lvds_probe(struct platform_device *pdev)
+{
+	struct reset_control *rstc, *arstc;
+	struct device *dev = &pdev->dev;
+	struct rzg3l_lvds *lvds;
+	int ret;
+
+	lvds = devm_drm_bridge_alloc(dev, struct rzg3l_lvds, bridge,
+				     &rzg3l_lvds_bridge_ops);
+	if (IS_ERR(lvds))
+		return PTR_ERR(lvds);
+
+	lvds->dev = dev;
+	lvds->bridge.of_node = pdev->dev.of_node;
+
+	lvds->regmap = syscon_node_to_regmap(dev->of_node->parent);
+	if (IS_ERR(lvds->regmap))
+		return PTR_ERR(lvds->regmap);
+
+	rstc = devm_reset_control_get_optional_exclusive(dev, "rst");
+	if (IS_ERR(rstc))
+		return dev_err_probe(dev, PTR_ERR(rstc), "failed to get rst\n");
+
+	arstc = devm_reset_control_get_optional_exclusive(dev, "arst");
+	if (IS_ERR(arstc))
+		return dev_err_probe(dev, PTR_ERR(arstc),
+				     "failed to get arst\n");
+
+	lvds->prstc = devm_reset_control_get_shared(dev, "prst");
+	if (IS_ERR(lvds->prstc))
+		return dev_err_probe(dev, PTR_ERR(lvds->prstc),
+				     "failed to get prst\n");
+
+	lvds->lvd_rstc = devm_reset_control_get_shared(dev, "lvdrst");
+	if (IS_ERR(lvds->lvd_rstc))
+		return dev_err_probe(dev, PTR_ERR(lvds->lvd_rstc),
+				     "failed to get core reset\n");
+
+	platform_set_drvdata(pdev, lvds);
+	ret = devm_pm_runtime_enable(dev);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to enable Runtime PM\n");
+
+	lvds->bridge.next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
+	if (IS_ERR(lvds->bridge.next_bridge))
+		return dev_err_probe(dev, PTR_ERR(lvds->bridge.next_bridge),
+				     "failed to get next bridge\n");
+
+	ret = reset_control_assert(rstc);
+	if (ret < 0)
+		return ret;
+
+	ret = reset_control_assert(arstc);
+	if (ret < 0)
+		return ret;
+
+	ret = devm_drm_bridge_add(dev, &lvds->bridge);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				     "Failed to register drm bridge\n");
+
+	return ret;
+}
+
+static const struct of_device_id rzg3l_lvds_of_table[] = {
+	{ .compatible = "renesas,r9a08g046-lvds" },
+	{ /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, rzg3l_lvds_of_table);
+
+static struct platform_driver rzg3l_lvds_platform_driver = {
+	.probe		= rzg3l_lvds_probe,
+	.driver		= {
+		.name	= "rzg3l-lvds",
+		.pm	= pm_ptr(&rzg3l_lvds_pm_ops),
+		.of_match_table = rzg3l_lvds_of_table,
+	},
+};
+
+module_platform_driver(rzg3l_lvds_platform_driver);
+
+MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
+MODULE_AUTHOR("Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>");
+MODULE_DESCRIPTION("Renesas RZ/G3L LVDS Encoder Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h
new file mode 100644
index 000000000000..281b7648f168
--- /dev/null
+++ b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * RZ/G3L LVDS Interface Registers Definitions
+ *
+ * Copyright (C) 2026 Renesas Electronics Corporation
+ *
+ */
+
+#ifndef __RZG3L_LVDS_REGS_H__
+#define __RZG3L_LVDS_REGS_H__
+
+#define LVDS_CMN			0x00
+#define LVDS_CMN_RST_PHY0_SEL		(1 << 24)
+#define LVDS_CMN_RST_PHY0_SEL_CH0	(1 << 24)
+#define LVDS_CMN_PHY_RESET		(1 << 0)
+
+#define LVDS_0_PHY_OFFSET		0x10
+#define LVDS_0_PHY_CH_IO_EN_MSK		(0x1f)
+#define LVDS_0_PHY_CH_IO_EN		(LVDS_0_PHY_CH_IO_EN_MSK << 0)
+#define LVDS_0_PHY_CH_EN_BGR		BIT(8)
+#define LVDS_0_PHY_CH_EN_LDO		BIT(9)
+
+#define LVDS_0_CTL_OFFSET		0x14
+#define LVDS_0_CTL_FMT_SEL_MSK		GENMASK(23, 20)
+
+#endif /* __RZG3L_LVDS_REGS_H__ */
-- 
2.43.0

Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] The compatible string 'renesas,r9a08g046-lvds-cmn' is used in the dt-binding example but is not documented.
- [Low] The parent node 'lvds-cmn' in the example lacks a 'ranges' property, breaking address translation for its child nodes.
--

commit be595c0db2d85d9ea1396f0f30ac7ad75f4101fe
Author: Biju Das <biju.das.jz@bp.renesas.com>

dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

Documents the LVDS encoder IP found on the RZ/G3L SoC. It supports
single-link mode and shares a peripheral clock and reset signal with the
MIPI-DSI interface.

> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> new file mode 100644
> index 0000000000000..b1f6d020ae7b1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml

[ ... ]

> +examples:
> +  - |
> +    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
> +
> +    lvds-cmn@108a0000 {
> +        compatible = "renesas,r9a08g046-lvds-cmn",
> +                     "simple-mfd", "syscon";

[Severity: Low]
Is this compatible string documented somewhere else? It looks like
renesas,r9a08g046-lvds-cmn isn't present in the tree, which might cause
dt_binding_check to fail when it validates the example.

> +        reg = <0x108a0000 0x10000>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;

[Severity: Low]
Does this parent node need a ranges property? Without it, address translation
for the child node's reg = <0x10 0x8> might fail, and dtc often warns about
missing ranges in simple-mfd nodes with children.

> +
> +        lvds0: lvds@10 {
> +            compatible = "renesas,r9a08g046-lvds";
> +            reg = <0x10 0x8>;

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260524194457.479681-1-biju.das.jz@bp.renesas.com?part=1

Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

[Biju Das]

Hi Bot,

On Sun, May 24, 2026 at 8:58 PM <sashiko-bot@kernel.org> wrote:
>
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [Low] The compatible string 'renesas,r9a08g046-lvds-cmn' is used in the dt-binding example but is not documented.
> - [Low] The parent node 'lvds-cmn' in the example lacks a 'ranges' property, breaking address translation for its child nodes.
> --
>
> commit be595c0db2d85d9ea1396f0f30ac7ad75f4101fe
> Author: Biju Das <biju.das.jz@bp.renesas.com>
>
> dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder
>
> Documents the LVDS encoder IP found on the RZ/G3L SoC. It supports
> single-link mode and shares a peripheral clock and reset signal with the
> MIPI-DSI interface.
>
> > diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> > new file mode 100644
> > index 0000000000000..b1f6d020ae7b1
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
>
> [ ... ]
>
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
> > +
> > +    lvds-cmn@108a0000 {
> > +        compatible = "renesas,r9a08g046-lvds-cmn",
> > +                     "simple-mfd", "syscon";
>
> [Severity: Low]
> Is this compatible string documented somewhere else? It looks like
> renesas,r9a08g046-lvds-cmn isn't present in the tree, which might cause
> dt_binding_check to fail when it validates the example.

This compatible is documented and is in next [1].

Q1) Can you please reun the AI review with [1] ?

[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20260522&id=51284d8b1dbcd7fa0220c49eeab29b14617e0d88

>
> > +        reg = <0x108a0000 0x10000>;
> > +        #address-cells = <1>;
> > +        #size-cells = <1>;
>
> [Severity: Low]
> Does this parent node need a ranges property? Without it, address translation
> for the child node's reg = <0x10 0x8> might fail, and dtc often warns about
> missing ranges in simple-mfd nodes with children.

I don't get any error or dtc warnings. Have you ran dt-binding check
before providing
such comment?

Cheers,
Biju

Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2574 bytes --]

On Mon, May 25, 2026 at 08:45:00AM +0100, Biju Das wrote:
> Hi Bot,
> 
> On Sun, May 24, 2026 at 8:58 PM <sashiko-bot@kernel.org> wrote:
> >
> > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> > - [Low] The compatible string 'renesas,r9a08g046-lvds-cmn' is used in the dt-binding example but is not documented.
> > - [Low] The parent node 'lvds-cmn' in the example lacks a 'ranges' property, breaking address translation for its child nodes.
> > --
> >
> > commit be595c0db2d85d9ea1396f0f30ac7ad75f4101fe
> > Author: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder
> >
> > Documents the LVDS encoder IP found on the RZ/G3L SoC. It supports
> > single-link mode and shares a peripheral clock and reset signal with the
> > MIPI-DSI interface.
> >
> > > diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> > > new file mode 100644
> > > index 0000000000000..b1f6d020ae7b1
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> >
> > [ ... ]
> >
> > > +examples:
> > > +  - |
> > > +    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
> > > +
> > > +    lvds-cmn@108a0000 {
> > > +        compatible = "renesas,r9a08g046-lvds-cmn",
> > > +                     "simple-mfd", "syscon";
> >
> > [Severity: Low]
> > Is this compatible string documented somewhere else? It looks like
> > renesas,r9a08g046-lvds-cmn isn't present in the tree, which might cause
> > dt_binding_check to fail when it validates the example.
> 
> This compatible is documented and is in next [1].
> 
> Q1) Can you please reun the AI review with [1] ?
> 
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20260522&id=51284d8b1dbcd7fa0220c49eeab29b14617e0d88
> 
> >
> > > +        reg = <0x108a0000 0x10000>;
> > > +        #address-cells = <1>;
> > > +        #size-cells = <1>;
> >
> > [Severity: Low]
> > Does this parent node need a ranges property? Without it, address translation
> > for the child node's reg = <0x10 0x8> might fail, and dtc often warns about
> > missing ranges in simple-mfd nodes with children.
> 
> I don't get any error or dtc warnings. Have you ran dt-binding check
> before providing
> such comment?

From what I can establish, it mentions the checks etc but never actually
runs them.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v2 2/2] drm: renesas: rz-du: Add support for RZ/G3L LVDS encoder

[Tommaso Merciai]

Hi Biju,
Thanks for your patch.

On Sun, May 24, 2026 at 08:44:51PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Add support for the RZ/G3L LVDS encoder driver. It operates in single-link
> mode with 4 lanes (Data) + 1 lane (Clock) and supports pixel clock rates
> from 25 to 87 MHz. The LVDS module cannot be used at the same time as
> MIPI-DSI. However, LVDS and the DSI interface share a peripheral clock and
> the MIPI_DSI_PRESET_N reset signal. Also, the MIPI_DSI_CMN_RSTB and
> MIPI_DSI_ARESET_N reset signals must be asserted before using the LVDS
> module.
> 

I thinks this should be v3 instead of v2.
Apart from that patch LGTM.

Tested on RZ/G3E LVDS ch0.

Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Kind Regards,
Tommaso

> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2->v3:
>  * Replace drm_atomic_state with drm_atomic_commit in
>    rzg3l_lvds_atomic_{en,dis}able().
>  * Drop local variable ret and dev_err() messages in
>    rzg3l_lvds_atomic_enable(); use WARN_ON() instead to
>    capture unexpected failures since atomic_enable should not fail.
>  * Drop local variable next_bridge from rzg3l_lvds_probe().
> v1->v2:
>  * Dropped unused function rzg3l_lvds_is_connected() and removed the 
>    corresponding header file rzg3l_lvds.h
>  * Dropped next_bridge from struct rzg3l_lvds instead using bridge's
>    next_bridge.
>  * Replaced pm_runtime_resume_and_get()->pm_runtime_get_sync() as
>    atomic_enable doesn't fail and for each enable there always will be an
>    atomic_disable() call.
>  * Started using DEFINE_RUNTIME_DEV_PM_OPS for PM callback.
>  * Replaced rzg3l_lvds_parse_dt() with devm_drm_of_get_bridge() in probe()
>  * Started using reset_control_bulk_*() in rzg3l_lvds_pm_runtime_{suspend,
>    resume}()
> ---
>  drivers/gpu/drm/renesas/rz-du/Kconfig         |  13 +
>  drivers/gpu/drm/renesas/rz-du/Makefile        |   1 +
>  drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c    | 277 ++++++++++++++++++
>  .../gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h   |  26 ++
>  4 files changed, 317 insertions(+)
>  create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c
>  create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h
> 
> diff --git a/drivers/gpu/drm/renesas/rz-du/Kconfig b/drivers/gpu/drm/renesas/rz-du/Kconfig
> index 7f2ef7137ae5..cbfc7b6bccb8 100644
> --- a/drivers/gpu/drm/renesas/rz-du/Kconfig
> +++ b/drivers/gpu/drm/renesas/rz-du/Kconfig
> @@ -26,3 +26,16 @@ config DRM_RZG2L_MIPI_DSI
>  	def_tristate DRM_RZG2L_DU
>  	depends on DRM_RZG2L_USE_MIPI_DSI
>  	select DRM_MIPI_DSI
> +
> +config DRM_RZG3L_USE_LVDS
> +	bool "RZ/G3L DU LVDS Encoder Support"
> +	depends on DRM_BRIDGE && OF
> +	default DRM_RZG2L_DU
> +	help
> +	  Enable support for the RZ/G3L Display Unit embedded LVDS encoders.
> +
> +config DRM_RZG3L_LVDS
> +	def_tristate DRM_RZG2L_DU
> +	depends on DRM_RZG3L_USE_LVDS
> +	select DRM_KMS_HELPER
> +	select DRM_PANEL
> diff --git a/drivers/gpu/drm/renesas/rz-du/Makefile b/drivers/gpu/drm/renesas/rz-du/Makefile
> index 2987900ea6b6..46decb7ac4f1 100644
> --- a/drivers/gpu/drm/renesas/rz-du/Makefile
> +++ b/drivers/gpu/drm/renesas/rz-du/Makefile
> @@ -8,3 +8,4 @@ rzg2l-du-drm-$(CONFIG_VIDEO_RENESAS_VSP1)	+= rzg2l_du_vsp.o
>  obj-$(CONFIG_DRM_RZG2L_DU)		+= rzg2l-du-drm.o
>  
>  obj-$(CONFIG_DRM_RZG2L_MIPI_DSI)	+= rzg2l_mipi_dsi.o
> +obj-$(CONFIG_DRM_RZG3L_LVDS)		+= rzg3l_lvds.o
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c
> new file mode 100644
> index 000000000000..a51c3e5a2efe
> --- /dev/null
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c
> @@ -0,0 +1,277 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * RZ/G3L LVDS Encoder Driver
> + *
> + * Copyright (C) 2026 Renesas Electronics Corporation
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/media-bus-format.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_graph.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +
> +#include <drm/drm_atomic.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_bridge.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_panel.h>
> +#include <drm/drm_probe_helper.h>
> +
> +#include "rzg3l_lvds_regs.h"
> +
> +enum rzg3l_lvds_mode {
> +	RZG3L_LVDS_MODE_JEIDA = 0,
> +	RZG3L_LVDS_MODE_JEIDA_MIRROR = 1,
> +	RZG3L_LVDS_MODE_MODE2 = 2,
> +	RZG3L_LVDS_MODE_MODE2_MIRROR = 3,
> +	RZG3L_LVDS_MODE_VESA = 4,
> +	RZG3L_LVDS_MODE_VESA_MIRROR = 5,
> +	RZG3L_LVDS_MODE_MODE6 = 6,
> +	RZG3L_LVDS_MODE_MODE6_MIRROR = 7,
> +};
> +
> +struct rzg3l_lvds {
> +	struct device *dev;
> +	struct reset_control *prstc;
> +	struct reset_control *lvd_rstc;
> +	struct regmap *regmap;
> +	struct drm_bridge bridge;
> +};
> +
> +#define bridge_to_rzg3l_lvds(b) \
> +	container_of(b, struct rzg3l_lvds, bridge)
> +
> +/* -----------------------------------------------------------------------------
> + * Bridge
> + */
> +
> +static void rzg3l_lvds_atomic_enable(struct drm_bridge *bridge,
> +				     struct drm_atomic_commit *state)
> +{
> +	struct rzg3l_lvds *lvds = bridge_to_rzg3l_lvds(bridge);
> +	const struct drm_bridge_state *bridge_state;
> +	u32 fmt;
> +
> +	/* Get the LVDS format from the bridge state. */
> +	bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
> +	if (WARN_ON(!bridge_state))
> +		return;
> +
> +	switch (bridge_state->output_bus_cfg.format) {
> +	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
> +		fmt = RZG3L_LVDS_MODE_JEIDA;
> +		break;
> +	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
> +		fmt = RZG3L_LVDS_MODE_VESA;
> +		break;
> +	default:
> +		fmt = RZG3L_LVDS_MODE_VESA;
> +		dev_warn(lvds->dev, "Unsupported bus fmt 0x%04x\n",
> +			 bridge_state->output_bus_cfg.format);
> +		break;
> +	}
> +
> +	if (WARN_ON(pm_runtime_get_sync(lvds->dev) < 0))
> +		return;
> +
> +	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
> +			   LVDS_0_PHY_CH_EN_BGR, LVDS_0_PHY_CH_EN_BGR);
> +	fsleep(20);
> +
> +	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
> +			   LVDS_0_PHY_CH_EN_LDO, LVDS_0_PHY_CH_EN_LDO);
> +	fsleep(10);
> +
> +	regmap_write(lvds->regmap, LVDS_CMN, LVDS_CMN_RST_PHY0_SEL);
> +	regmap_update_bits(lvds->regmap, LVDS_0_CTL_OFFSET,
> +			   LVDS_0_CTL_FMT_SEL_MSK,
> +			   FIELD_PREP(LVDS_0_CTL_FMT_SEL_MSK, fmt));
> +	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
> +			   LVDS_0_PHY_CH_IO_EN_MSK, LVDS_0_PHY_CH_IO_EN);
> +	regmap_write(lvds->regmap, LVDS_CMN,
> +		     LVDS_CMN_RST_PHY0_SEL | LVDS_CMN_PHY_RESET);
> +	fsleep(100);
> +}
> +
> +static void rzg3l_lvds_atomic_disable(struct drm_bridge *bridge,
> +				      struct drm_atomic_commit *state)
> +{
> +	struct rzg3l_lvds *lvds = bridge_to_rzg3l_lvds(bridge);
> +
> +	regmap_update_bits(lvds->regmap, LVDS_CMN, LVDS_CMN_PHY_RESET, 0);
> +	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
> +			   LVDS_0_PHY_CH_IO_EN_MSK, 0);
> +	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
> +			   LVDS_0_PHY_CH_EN_LDO, 0);
> +	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
> +			   LVDS_0_PHY_CH_EN_BGR, 0);
> +
> +	pm_runtime_put(lvds->dev);
> +}
> +
> +static int rzg3l_lvds_attach(struct drm_bridge *bridge,
> +			     struct drm_encoder *encoder,
> +			     enum drm_bridge_attach_flags flags)
> +{
> +	struct rzg3l_lvds *lvds = bridge_to_rzg3l_lvds(bridge);
> +
> +	if (!lvds->bridge.next_bridge)
> +		return 0;
> +
> +	return drm_bridge_attach(encoder, lvds->bridge.next_bridge, bridge, flags);
> +}
> +
> +static enum drm_mode_status
> +rzg3l_lvds_bridge_mode_valid(struct drm_bridge *bridge,
> +			     const struct drm_display_info *info,
> +			     const struct drm_display_mode *mode)
> +{
> +	if (mode->clock > 87000)
> +		return MODE_CLOCK_HIGH;
> +
> +	if (mode->clock < 25000)
> +		return MODE_CLOCK_LOW;
> +
> +	return MODE_OK;
> +}
> +
> +static const struct drm_bridge_funcs rzg3l_lvds_bridge_ops = {
> +	.attach = rzg3l_lvds_attach,
> +	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> +	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> +	.atomic_reset = drm_atomic_helper_bridge_reset,
> +	.atomic_enable = rzg3l_lvds_atomic_enable,
> +	.atomic_disable = rzg3l_lvds_atomic_disable,
> +	.mode_valid = rzg3l_lvds_bridge_mode_valid,
> +};
> +
> +/* -----------------------------------------------------------------------------
> + * Power Management
> + */
> +
> +static int rzg3l_lvds_pm_runtime_suspend(struct device *dev)
> +{
> +	struct rzg3l_lvds *lvds = dev_get_drvdata(dev);
> +	struct reset_control_bulk_data resets[] = {
> +		{ .rstc = lvds->lvd_rstc },
> +		{ .rstc = lvds->prstc },
> +	};
> +
> +	return reset_control_bulk_assert(ARRAY_SIZE(resets), resets);
> +}
> +
> +static int rzg3l_lvds_pm_runtime_resume(struct device *dev)
> +{
> +	struct rzg3l_lvds *lvds = dev_get_drvdata(dev);
> +	struct reset_control_bulk_data resets[] = {
> +		{ .rstc = lvds->lvd_rstc },
> +		{ .rstc = lvds->prstc },
> +	};
> +
> +	return reset_control_bulk_deassert(ARRAY_SIZE(resets), resets);
> +}
> +
> +static DEFINE_RUNTIME_DEV_PM_OPS(rzg3l_lvds_pm_ops,
> +				 rzg3l_lvds_pm_runtime_suspend,
> +				 rzg3l_lvds_pm_runtime_resume, NULL);
> +
> +/* -----------------------------------------------------------------------------
> + * Probe & Remove
> + */
> +
> +static int rzg3l_lvds_probe(struct platform_device *pdev)
> +{
> +	struct reset_control *rstc, *arstc;
> +	struct device *dev = &pdev->dev;
> +	struct rzg3l_lvds *lvds;
> +	int ret;
> +
> +	lvds = devm_drm_bridge_alloc(dev, struct rzg3l_lvds, bridge,
> +				     &rzg3l_lvds_bridge_ops);
> +	if (IS_ERR(lvds))
> +		return PTR_ERR(lvds);
> +
> +	lvds->dev = dev;
> +	lvds->bridge.of_node = pdev->dev.of_node;
> +
> +	lvds->regmap = syscon_node_to_regmap(dev->of_node->parent);
> +	if (IS_ERR(lvds->regmap))
> +		return PTR_ERR(lvds->regmap);
> +
> +	rstc = devm_reset_control_get_optional_exclusive(dev, "rst");
> +	if (IS_ERR(rstc))
> +		return dev_err_probe(dev, PTR_ERR(rstc), "failed to get rst\n");
> +
> +	arstc = devm_reset_control_get_optional_exclusive(dev, "arst");
> +	if (IS_ERR(arstc))
> +		return dev_err_probe(dev, PTR_ERR(arstc),
> +				     "failed to get arst\n");
> +
> +	lvds->prstc = devm_reset_control_get_shared(dev, "prst");
> +	if (IS_ERR(lvds->prstc))
> +		return dev_err_probe(dev, PTR_ERR(lvds->prstc),
> +				     "failed to get prst\n");
> +
> +	lvds->lvd_rstc = devm_reset_control_get_shared(dev, "lvdrst");
> +	if (IS_ERR(lvds->lvd_rstc))
> +		return dev_err_probe(dev, PTR_ERR(lvds->lvd_rstc),
> +				     "failed to get core reset\n");
> +
> +	platform_set_drvdata(pdev, lvds);
> +	ret = devm_pm_runtime_enable(dev);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "Failed to enable Runtime PM\n");
> +
> +	lvds->bridge.next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
> +	if (IS_ERR(lvds->bridge.next_bridge))
> +		return dev_err_probe(dev, PTR_ERR(lvds->bridge.next_bridge),
> +				     "failed to get next bridge\n");
> +
> +	ret = reset_control_assert(rstc);
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = reset_control_assert(arstc);
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = devm_drm_bridge_add(dev, &lvds->bridge);
> +	if (ret)
> +		return dev_err_probe(dev, ret,
> +				     "Failed to register drm bridge\n");
> +
> +	return ret;
> +}
> +
> +static const struct of_device_id rzg3l_lvds_of_table[] = {
> +	{ .compatible = "renesas,r9a08g046-lvds" },
> +	{ /* sentinel */ }
> +};
> +
> +MODULE_DEVICE_TABLE(of, rzg3l_lvds_of_table);
> +
> +static struct platform_driver rzg3l_lvds_platform_driver = {
> +	.probe		= rzg3l_lvds_probe,
> +	.driver		= {
> +		.name	= "rzg3l-lvds",
> +		.pm	= pm_ptr(&rzg3l_lvds_pm_ops),
> +		.of_match_table = rzg3l_lvds_of_table,
> +	},
> +};
> +
> +module_platform_driver(rzg3l_lvds_platform_driver);
> +
> +MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
> +MODULE_AUTHOR("Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>");
> +MODULE_DESCRIPTION("Renesas RZ/G3L LVDS Encoder Driver");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h
> new file mode 100644
> index 000000000000..281b7648f168
> --- /dev/null
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h
> @@ -0,0 +1,26 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * RZ/G3L LVDS Interface Registers Definitions
> + *
> + * Copyright (C) 2026 Renesas Electronics Corporation
> + *
> + */
> +
> +#ifndef __RZG3L_LVDS_REGS_H__
> +#define __RZG3L_LVDS_REGS_H__
> +
> +#define LVDS_CMN			0x00
> +#define LVDS_CMN_RST_PHY0_SEL		(1 << 24)
> +#define LVDS_CMN_RST_PHY0_SEL_CH0	(1 << 24)
> +#define LVDS_CMN_PHY_RESET		(1 << 0)
> +
> +#define LVDS_0_PHY_OFFSET		0x10
> +#define LVDS_0_PHY_CH_IO_EN_MSK		(0x1f)
> +#define LVDS_0_PHY_CH_IO_EN		(LVDS_0_PHY_CH_IO_EN_MSK << 0)
> +#define LVDS_0_PHY_CH_EN_BGR		BIT(8)
> +#define LVDS_0_PHY_CH_EN_LDO		BIT(9)
> +
> +#define LVDS_0_CTL_OFFSET		0x14
> +#define LVDS_0_CTL_FMT_SEL_MSK		GENMASK(23, 20)
> +
> +#endif /* __RZG3L_LVDS_REGS_H__ */
> -- 
> 2.43.0
> 

Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

[Tommaso Merciai]

Hi Biju,
Thanks for your patch.

On Sun, May 24, 2026 at 08:44:50PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Document the LVDS encoder IP found on the RZ/G3L SoC. It supports
> single-link mode. LVDS and the DSI interface share a peripheral clock and
> the MIPI_DSI_PRESET_N reset signal. However, the LVDS module cannot be
> used at the same time as MIPI-DSI.
> 

Same here, this should be v3 instead of v2.
Apart from that patch LGTM.

Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Kind Regards,
Tommaso

> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2->v3:
>  * No change.
> v1->v2:
>  * Collected tag.
> ---
>  .../bridge/renesas,r9a08g046-lvds.yaml        | 128 ++++++++++++++++++
>  1 file changed, 128 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> new file mode 100644
> index 000000000000..b1f6d020ae7b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> @@ -0,0 +1,128 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/renesas,r9a08g046-lvds.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G3L LVDS Encoder
> +
> +maintainers:
> +  - Biju Das <biju.das.jz@bp.renesas.com>
> +  - Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> +
> +description: |
> +  This binding describe the LVDS encoder embedded in the Renesas RZ/G3L
> +  SoC. The encoder can operate in LVDS Single-link mode with 4 lanes
> +  (Data) + 1 lane (Clock).
> +
> +properties:
> +  compatible:
> +    const: renesas,r9a08g046-lvds
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: Peripheral clock
> +      - description: PHY clock
> +      - description: Dot clock
> +
> +  clock-names:
> +    items:
> +      - const: pclk
> +      - const: phyclk
> +      - const: dotclk
> +
> +  resets:
> +    items:
> +      - description: LVDS_RESET_N
> +      - description: MIPI_DSI_PRESET_N
> +      - description: MIPI_DSI_CMN_RSTB
> +      - description: MIPI_DSI_ARESET_N
> +
> +  reset-names:
> +    items:
> +      - const: lvdrst
> +      - const: prst
> +      - const: rst
> +      - const: arst
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +
> +    properties:
> +      port@0:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description: Input channel, directly connected to the Display Unit.
> +
> +      port@1:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description: |
> +          Output channel, directly connected to the LVDS panel or bridge.
> +
> +    required:
> +      - port@0
> +      - port@1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - resets
> +  - reset-names
> +  - power-domains
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
> +
> +    lvds-cmn@108a0000 {
> +        compatible = "renesas,r9a08g046-lvds-cmn",
> +                     "simple-mfd", "syscon";
> +        reg = <0x108a0000 0x10000>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +
> +        lvds0: lvds@10 {
> +            compatible = "renesas,r9a08g046-lvds";
> +            reg = <0x10 0x8>;
> +            clocks = <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>,
> +                     <&cpg CPG_MOD R9A08G046_LVDS_PLLCLK>,
> +                     <&cpg CPG_MOD R9A08G046_LVDS_CLK_DOT0>;
> +            clock-names = "pclk", "phyclk", "dotclk";
> +            resets = <&cpg R9A08G046_LVDS_RESET_N>,
> +                     <&cpg R9A08G046_MIPI_DSI_PRESET_N>,
> +                     <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>,
> +                     <&cpg R9A08G046_MIPI_DSI_ARESET_N>;
> +            reset-names = "lvdrst", "prst", "rst", "arst";
> +            power-domains = <&cpg>;
> +
> +            ports {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +
> +                port@0 {
> +                    reg = <0>;
> +                    lvds0_in: endpoint {
> +                        remote-endpoint = <&du_out_lvds0>;
> +                    };
> +                };
> +
> +                port@1 {
> +                    reg = <1>;
> +                    lvds0_out: endpoint {
> +                        remote-endpoint = <&panel_in>;
> +                    };
> +                };
> +            };
> +        };
> +    };
> +...
> -- 
> 2.43.0
> 

RE: [PATCH v2 2/2] drm: renesas: rz-du: Add support for RZ/G3L LVDS encoder

[Biju Das]

Hi Tommaso,

Thanks for the feedback.

> -----Original Message-----
> From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Sent: 26 May 2026 08:04
> Subject: Re: [PATCH v2 2/2] drm: renesas: rz-du: Add support for RZ/G3L LVDS encoder
> 
> Hi Biju,
> Thanks for your patch.
> 
> On Sun, May 24, 2026 at 08:44:51PM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Add support for the RZ/G3L LVDS encoder driver. It operates in
> > single-link mode with 4 lanes (Data) + 1 lane (Clock) and supports
> > pixel clock rates from 25 to 87 MHz. The LVDS module cannot be used at
> > the same time as MIPI-DSI. However, LVDS and the DSI interface share a
> > peripheral clock and the MIPI_DSI_PRESET_N reset signal. Also, the
> > MIPI_DSI_CMN_RSTB and MIPI_DSI_ARESET_N reset signals must be asserted
> > before using the LVDS module.
> >
> 
> I thinks this should be v3 instead of v2.

Oops, you are correct.

I will send this series as v3.

Cheers,
Biju

> Apart from that patch LGTM.
> 
> Tested on RZ/G3E LVDS ch0.
> 
> Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> 
> Kind Regards,
> Tommaso
> 
> > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v2->v3:
> >  * Replace drm_atomic_state with drm_atomic_commit in
> >    rzg3l_lvds_atomic_{en,dis}able().
> >  * Drop local variable ret and dev_err() messages in
> >    rzg3l_lvds_atomic_enable(); use WARN_ON() instead to
> >    capture unexpected failures since atomic_enable should not fail.
> >  * Drop local variable next_bridge from rzg3l_lvds_probe().
> > v1->v2:
> >  * Dropped unused function rzg3l_lvds_is_connected() and removed the
> >    corresponding header file rzg3l_lvds.h
> >  * Dropped next_bridge from struct rzg3l_lvds instead using bridge's
> >    next_bridge.
> >  * Replaced pm_runtime_resume_and_get()->pm_runtime_get_sync() as
> >    atomic_enable doesn't fail and for each enable there always will be an
> >    atomic_disable() call.
> >  * Started using DEFINE_RUNTIME_DEV_PM_OPS for PM callback.
> >  * Replaced rzg3l_lvds_parse_dt() with devm_drm_of_get_bridge() in
> > probe()
> >  * Started using reset_control_bulk_*() in rzg3l_lvds_pm_runtime_{suspend,
> >    resume}()
> > ---
> >  drivers/gpu/drm/renesas/rz-du/Kconfig         |  13 +
> >  drivers/gpu/drm/renesas/rz-du/Makefile        |   1 +
> >  drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c    | 277 ++++++++++++++++++
> >  .../gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h   |  26 ++
> >  4 files changed, 317 insertions(+)
> >  create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c
> >  create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h
> >
> > diff --git a/drivers/gpu/drm/renesas/rz-du/Kconfig
> > b/drivers/gpu/drm/renesas/rz-du/Kconfig
> > index 7f2ef7137ae5..cbfc7b6bccb8 100644
> > --- a/drivers/gpu/drm/renesas/rz-du/Kconfig
> > +++ b/drivers/gpu/drm/renesas/rz-du/Kconfig
> > @@ -26,3 +26,16 @@ config DRM_RZG2L_MIPI_DSI
> >  	def_tristate DRM_RZG2L_DU
> >  	depends on DRM_RZG2L_USE_MIPI_DSI
> >  	select DRM_MIPI_DSI
> > +
> > +config DRM_RZG3L_USE_LVDS
> > +	bool "RZ/G3L DU LVDS Encoder Support"
> > +	depends on DRM_BRIDGE && OF
> > +	default DRM_RZG2L_DU
> > +	help
> > +	  Enable support for the RZ/G3L Display Unit embedded LVDS encoders.
> > +
> > +config DRM_RZG3L_LVDS
> > +	def_tristate DRM_RZG2L_DU
> > +	depends on DRM_RZG3L_USE_LVDS
> > +	select DRM_KMS_HELPER
> > +	select DRM_PANEL
> > diff --git a/drivers/gpu/drm/renesas/rz-du/Makefile
> > b/drivers/gpu/drm/renesas/rz-du/Makefile
> > index 2987900ea6b6..46decb7ac4f1 100644
> > --- a/drivers/gpu/drm/renesas/rz-du/Makefile
> > +++ b/drivers/gpu/drm/renesas/rz-du/Makefile
> > @@ -8,3 +8,4 @@ rzg2l-du-drm-$(CONFIG_VIDEO_RENESAS_VSP1)	+= rzg2l_du_vsp.o
> >  obj-$(CONFIG_DRM_RZG2L_DU)		+= rzg2l-du-drm.o
> >
> >  obj-$(CONFIG_DRM_RZG2L_MIPI_DSI)	+= rzg2l_mipi_dsi.o
> > +obj-$(CONFIG_DRM_RZG3L_LVDS)		+= rzg3l_lvds.o
> > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c
> > b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c
> > new file mode 100644
> > index 000000000000..a51c3e5a2efe
> > --- /dev/null
> > +++ b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c
> > @@ -0,0 +1,277 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * RZ/G3L LVDS Encoder Driver
> > + *
> > + * Copyright (C) 2026 Renesas Electronics Corporation  */
> > +
> > +#include <linux/bitfield.h>
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/io.h>
> > +#include <linux/media-bus-format.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_graph.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/regmap.h>
> > +#include <linux/reset.h>
> > +
> > +#include <drm/drm_atomic.h>
> > +#include <drm/drm_atomic_helper.h>
> > +#include <drm/drm_bridge.h>
> > +#include <drm/drm_of.h>
> > +#include <drm/drm_panel.h>
> > +#include <drm/drm_probe_helper.h>
> > +
> > +#include "rzg3l_lvds_regs.h"
> > +
> > +enum rzg3l_lvds_mode {
> > +	RZG3L_LVDS_MODE_JEIDA = 0,
> > +	RZG3L_LVDS_MODE_JEIDA_MIRROR = 1,
> > +	RZG3L_LVDS_MODE_MODE2 = 2,
> > +	RZG3L_LVDS_MODE_MODE2_MIRROR = 3,
> > +	RZG3L_LVDS_MODE_VESA = 4,
> > +	RZG3L_LVDS_MODE_VESA_MIRROR = 5,
> > +	RZG3L_LVDS_MODE_MODE6 = 6,
> > +	RZG3L_LVDS_MODE_MODE6_MIRROR = 7,
> > +};
> > +
> > +struct rzg3l_lvds {
> > +	struct device *dev;
> > +	struct reset_control *prstc;
> > +	struct reset_control *lvd_rstc;
> > +	struct regmap *regmap;
> > +	struct drm_bridge bridge;
> > +};
> > +
> > +#define bridge_to_rzg3l_lvds(b) \
> > +	container_of(b, struct rzg3l_lvds, bridge)
> > +
> > +/*
> > +---------------------------------------------------------------------
> > +--------
> > + * Bridge
> > + */
> > +
> > +static void rzg3l_lvds_atomic_enable(struct drm_bridge *bridge,
> > +				     struct drm_atomic_commit *state) {
> > +	struct rzg3l_lvds *lvds = bridge_to_rzg3l_lvds(bridge);
> > +	const struct drm_bridge_state *bridge_state;
> > +	u32 fmt;
> > +
> > +	/* Get the LVDS format from the bridge state. */
> > +	bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
> > +	if (WARN_ON(!bridge_state))
> > +		return;
> > +
> > +	switch (bridge_state->output_bus_cfg.format) {
> > +	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
> > +		fmt = RZG3L_LVDS_MODE_JEIDA;
> > +		break;
> > +	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
> > +		fmt = RZG3L_LVDS_MODE_VESA;
> > +		break;
> > +	default:
> > +		fmt = RZG3L_LVDS_MODE_VESA;
> > +		dev_warn(lvds->dev, "Unsupported bus fmt 0x%04x\n",
> > +			 bridge_state->output_bus_cfg.format);
> > +		break;
> > +	}
> > +
> > +	if (WARN_ON(pm_runtime_get_sync(lvds->dev) < 0))
> > +		return;
> > +
> > +	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
> > +			   LVDS_0_PHY_CH_EN_BGR, LVDS_0_PHY_CH_EN_BGR);
> > +	fsleep(20);
> > +
> > +	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
> > +			   LVDS_0_PHY_CH_EN_LDO, LVDS_0_PHY_CH_EN_LDO);
> > +	fsleep(10);
> > +
> > +	regmap_write(lvds->regmap, LVDS_CMN, LVDS_CMN_RST_PHY0_SEL);
> > +	regmap_update_bits(lvds->regmap, LVDS_0_CTL_OFFSET,
> > +			   LVDS_0_CTL_FMT_SEL_MSK,
> > +			   FIELD_PREP(LVDS_0_CTL_FMT_SEL_MSK, fmt));
> > +	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
> > +			   LVDS_0_PHY_CH_IO_EN_MSK, LVDS_0_PHY_CH_IO_EN);
> > +	regmap_write(lvds->regmap, LVDS_CMN,
> > +		     LVDS_CMN_RST_PHY0_SEL | LVDS_CMN_PHY_RESET);
> > +	fsleep(100);
> > +}
> > +
> > +static void rzg3l_lvds_atomic_disable(struct drm_bridge *bridge,
> > +				      struct drm_atomic_commit *state) {
> > +	struct rzg3l_lvds *lvds = bridge_to_rzg3l_lvds(bridge);
> > +
> > +	regmap_update_bits(lvds->regmap, LVDS_CMN, LVDS_CMN_PHY_RESET, 0);
> > +	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
> > +			   LVDS_0_PHY_CH_IO_EN_MSK, 0);
> > +	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
> > +			   LVDS_0_PHY_CH_EN_LDO, 0);
> > +	regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET,
> > +			   LVDS_0_PHY_CH_EN_BGR, 0);
> > +
> > +	pm_runtime_put(lvds->dev);
> > +}
> > +
> > +static int rzg3l_lvds_attach(struct drm_bridge *bridge,
> > +			     struct drm_encoder *encoder,
> > +			     enum drm_bridge_attach_flags flags) {
> > +	struct rzg3l_lvds *lvds = bridge_to_rzg3l_lvds(bridge);
> > +
> > +	if (!lvds->bridge.next_bridge)
> > +		return 0;
> > +
> > +	return drm_bridge_attach(encoder, lvds->bridge.next_bridge, bridge,
> > +flags); }
> > +
> > +static enum drm_mode_status
> > +rzg3l_lvds_bridge_mode_valid(struct drm_bridge *bridge,
> > +			     const struct drm_display_info *info,
> > +			     const struct drm_display_mode *mode) {
> > +	if (mode->clock > 87000)
> > +		return MODE_CLOCK_HIGH;
> > +
> > +	if (mode->clock < 25000)
> > +		return MODE_CLOCK_LOW;
> > +
> > +	return MODE_OK;
> > +}
> > +
> > +static const struct drm_bridge_funcs rzg3l_lvds_bridge_ops = {
> > +	.attach = rzg3l_lvds_attach,
> > +	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> > +	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> > +	.atomic_reset = drm_atomic_helper_bridge_reset,
> > +	.atomic_enable = rzg3l_lvds_atomic_enable,
> > +	.atomic_disable = rzg3l_lvds_atomic_disable,
> > +	.mode_valid = rzg3l_lvds_bridge_mode_valid, };
> > +
> > +/*
> > +---------------------------------------------------------------------
> > +--------
> > + * Power Management
> > + */
> > +
> > +static int rzg3l_lvds_pm_runtime_suspend(struct device *dev) {
> > +	struct rzg3l_lvds *lvds = dev_get_drvdata(dev);
> > +	struct reset_control_bulk_data resets[] = {
> > +		{ .rstc = lvds->lvd_rstc },
> > +		{ .rstc = lvds->prstc },
> > +	};
> > +
> > +	return reset_control_bulk_assert(ARRAY_SIZE(resets), resets); }
> > +
> > +static int rzg3l_lvds_pm_runtime_resume(struct device *dev) {
> > +	struct rzg3l_lvds *lvds = dev_get_drvdata(dev);
> > +	struct reset_control_bulk_data resets[] = {
> > +		{ .rstc = lvds->lvd_rstc },
> > +		{ .rstc = lvds->prstc },
> > +	};
> > +
> > +	return reset_control_bulk_deassert(ARRAY_SIZE(resets), resets); }
> > +
> > +static DEFINE_RUNTIME_DEV_PM_OPS(rzg3l_lvds_pm_ops,
> > +				 rzg3l_lvds_pm_runtime_suspend,
> > +				 rzg3l_lvds_pm_runtime_resume, NULL);
> > +
> > +/*
> > +---------------------------------------------------------------------
> > +--------
> > + * Probe & Remove
> > + */
> > +
> > +static int rzg3l_lvds_probe(struct platform_device *pdev) {
> > +	struct reset_control *rstc, *arstc;
> > +	struct device *dev = &pdev->dev;
> > +	struct rzg3l_lvds *lvds;
> > +	int ret;
> > +
> > +	lvds = devm_drm_bridge_alloc(dev, struct rzg3l_lvds, bridge,
> > +				     &rzg3l_lvds_bridge_ops);
> > +	if (IS_ERR(lvds))
> > +		return PTR_ERR(lvds);
> > +
> > +	lvds->dev = dev;
> > +	lvds->bridge.of_node = pdev->dev.of_node;
> > +
> > +	lvds->regmap = syscon_node_to_regmap(dev->of_node->parent);
> > +	if (IS_ERR(lvds->regmap))
> > +		return PTR_ERR(lvds->regmap);
> > +
> > +	rstc = devm_reset_control_get_optional_exclusive(dev, "rst");
> > +	if (IS_ERR(rstc))
> > +		return dev_err_probe(dev, PTR_ERR(rstc), "failed to get rst\n");
> > +
> > +	arstc = devm_reset_control_get_optional_exclusive(dev, "arst");
> > +	if (IS_ERR(arstc))
> > +		return dev_err_probe(dev, PTR_ERR(arstc),
> > +				     "failed to get arst\n");
> > +
> > +	lvds->prstc = devm_reset_control_get_shared(dev, "prst");
> > +	if (IS_ERR(lvds->prstc))
> > +		return dev_err_probe(dev, PTR_ERR(lvds->prstc),
> > +				     "failed to get prst\n");
> > +
> > +	lvds->lvd_rstc = devm_reset_control_get_shared(dev, "lvdrst");
> > +	if (IS_ERR(lvds->lvd_rstc))
> > +		return dev_err_probe(dev, PTR_ERR(lvds->lvd_rstc),
> > +				     "failed to get core reset\n");
> > +
> > +	platform_set_drvdata(pdev, lvds);
> > +	ret = devm_pm_runtime_enable(dev);
> > +	if (ret)
> > +		return dev_err_probe(dev, ret, "Failed to enable Runtime PM\n");
> > +
> > +	lvds->bridge.next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
> > +	if (IS_ERR(lvds->bridge.next_bridge))
> > +		return dev_err_probe(dev, PTR_ERR(lvds->bridge.next_bridge),
> > +				     "failed to get next bridge\n");
> > +
> > +	ret = reset_control_assert(rstc);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	ret = reset_control_assert(arstc);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	ret = devm_drm_bridge_add(dev, &lvds->bridge);
> > +	if (ret)
> > +		return dev_err_probe(dev, ret,
> > +				     "Failed to register drm bridge\n");
> > +
> > +	return ret;
> > +}
> > +
> > +static const struct of_device_id rzg3l_lvds_of_table[] = {
> > +	{ .compatible = "renesas,r9a08g046-lvds" },
> > +	{ /* sentinel */ }
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, rzg3l_lvds_of_table);
> > +
> > +static struct platform_driver rzg3l_lvds_platform_driver = {
> > +	.probe		= rzg3l_lvds_probe,
> > +	.driver		= {
> > +		.name	= "rzg3l-lvds",
> > +		.pm	= pm_ptr(&rzg3l_lvds_pm_ops),
> > +		.of_match_table = rzg3l_lvds_of_table,
> > +	},
> > +};
> > +
> > +module_platform_driver(rzg3l_lvds_platform_driver);
> > +
> > +MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
> > +MODULE_AUTHOR("Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>");
> > +MODULE_DESCRIPTION("Renesas RZ/G3L LVDS Encoder Driver");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h
> > b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h
> > new file mode 100644
> > index 000000000000..281b7648f168
> > --- /dev/null
> > +++ b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h
> > @@ -0,0 +1,26 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * RZ/G3L LVDS Interface Registers Definitions
> > + *
> > + * Copyright (C) 2026 Renesas Electronics Corporation
> > + *
> > + */
> > +
> > +#ifndef __RZG3L_LVDS_REGS_H__
> > +#define __RZG3L_LVDS_REGS_H__
> > +
> > +#define LVDS_CMN			0x00
> > +#define LVDS_CMN_RST_PHY0_SEL		(1 << 24)
> > +#define LVDS_CMN_RST_PHY0_SEL_CH0	(1 << 24)
> > +#define LVDS_CMN_PHY_RESET		(1 << 0)
> > +
> > +#define LVDS_0_PHY_OFFSET		0x10
> > +#define LVDS_0_PHY_CH_IO_EN_MSK		(0x1f)
> > +#define LVDS_0_PHY_CH_IO_EN		(LVDS_0_PHY_CH_IO_EN_MSK << 0)
> > +#define LVDS_0_PHY_CH_EN_BGR		BIT(8)
> > +#define LVDS_0_PHY_CH_EN_LDO		BIT(9)
> > +
> > +#define LVDS_0_CTL_OFFSET		0x14
> > +#define LVDS_0_CTL_FMT_SEL_MSK		GENMASK(23, 20)
> > +
> > +#endif /* __RZG3L_LVDS_REGS_H__ */
> > --
> > 2.43.0
> >

RE: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

[Biju Das]

Hi Tommaso,

Thanks for the feedback.

> -----Original Message-----
> From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Sent: 26 May 2026 08:07
> Subject: Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder
> 
> Hi Biju,
> Thanks for your patch.
> 
> On Sun, May 24, 2026 at 08:44:50PM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Document the LVDS encoder IP found on the RZ/G3L SoC. It supports
> > single-link mode. LVDS and the DSI interface share a peripheral clock
> > and the MIPI_DSI_PRESET_N reset signal. However, the LVDS module
> > cannot be used at the same time as MIPI-DSI.
> >
> 
> Same here, this should be v3 instead of v2.

Will send this as v3.

Cheers,
Biju

> Apart from that patch LGTM.
> 
> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> 
> Kind Regards,
> Tommaso
> 
> > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v2->v3:
> >  * No change.
> > v1->v2:
> >  * Collected tag.
> > ---
> >  .../bridge/renesas,r9a08g046-lvds.yaml        | 128 ++++++++++++++++++
> >  1 file changed, 128 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvd
> > s.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-l
> > vds.yaml
> > b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-l
> > vds.yaml
> > new file mode 100644
> > index 000000000000..b1f6d020ae7b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g0
> > +++ 46-lvds.yaml
> > @@ -0,0 +1,128 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +http://devicetree.org/schemas/display/bridge/renesas,r9a08g046-lvds.y
> > +aml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas RZ/G3L LVDS Encoder
> > +
> > +maintainers:
> > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > +  - Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> > +
> > +description: |
> > +  This binding describe the LVDS encoder embedded in the Renesas
> > +RZ/G3L
> > +  SoC. The encoder can operate in LVDS Single-link mode with 4 lanes
> > +  (Data) + 1 lane (Clock).
> > +
> > +properties:
> > +  compatible:
> > +    const: renesas,r9a08g046-lvds
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: Peripheral clock
> > +      - description: PHY clock
> > +      - description: Dot clock
> > +
> > +  clock-names:
> > +    items:
> > +      - const: pclk
> > +      - const: phyclk
> > +      - const: dotclk
> > +
> > +  resets:
> > +    items:
> > +      - description: LVDS_RESET_N
> > +      - description: MIPI_DSI_PRESET_N
> > +      - description: MIPI_DSI_CMN_RSTB
> > +      - description: MIPI_DSI_ARESET_N
> > +
> > +  reset-names:
> > +    items:
> > +      - const: lvdrst
> > +      - const: prst
> > +      - const: rst
> > +      - const: arst
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  ports:
> > +    $ref: /schemas/graph.yaml#/properties/ports
> > +
> > +    properties:
> > +      port@0:
> > +        $ref: /schemas/graph.yaml#/properties/port
> > +        description: Input channel, directly connected to the Display Unit.
> > +
> > +      port@1:
> > +        $ref: /schemas/graph.yaml#/properties/port
> > +        description: |
> > +          Output channel, directly connected to the LVDS panel or bridge.
> > +
> > +    required:
> > +      - port@0
> > +      - port@1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - clock-names
> > +  - resets
> > +  - reset-names
> > +  - power-domains
> > +  - ports
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
> > +
> > +    lvds-cmn@108a0000 {
> > +        compatible = "renesas,r9a08g046-lvds-cmn",
> > +                     "simple-mfd", "syscon";
> > +        reg = <0x108a0000 0x10000>;
> > +        #address-cells = <1>;
> > +        #size-cells = <1>;
> > +
> > +        lvds0: lvds@10 {
> > +            compatible = "renesas,r9a08g046-lvds";
> > +            reg = <0x10 0x8>;
> > +            clocks = <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>,
> > +                     <&cpg CPG_MOD R9A08G046_LVDS_PLLCLK>,
> > +                     <&cpg CPG_MOD R9A08G046_LVDS_CLK_DOT0>;
> > +            clock-names = "pclk", "phyclk", "dotclk";
> > +            resets = <&cpg R9A08G046_LVDS_RESET_N>,
> > +                     <&cpg R9A08G046_MIPI_DSI_PRESET_N>,
> > +                     <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>,
> > +                     <&cpg R9A08G046_MIPI_DSI_ARESET_N>;
> > +            reset-names = "lvdrst", "prst", "rst", "arst";
> > +            power-domains = <&cpg>;
> > +
> > +            ports {
> > +                #address-cells = <1>;
> > +                #size-cells = <0>;
> > +
> > +                port@0 {
> > +                    reg = <0>;
> > +                    lvds0_in: endpoint {
> > +                        remote-endpoint = <&du_out_lvds0>;
> > +                    };
> > +                };
> > +
> > +                port@1 {
> > +                    reg = <1>;
> > +                    lvds0_out: endpoint {
> > +                        remote-endpoint = <&panel_in>;
> > +                    };
> > +                };
> > +            };
> > +        };
> > +    };
> > +...
> > --
> > 2.43.0
> >

Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

[Rob Herring]

On Mon, May 25, 2026 at 08:45:00AM +0100, Biju Das wrote:
> Hi Bot,
> 
> On Sun, May 24, 2026 at 8:58 PM <sashiko-bot@kernel.org> wrote:
> >
> > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> > - [Low] The compatible string 'renesas,r9a08g046-lvds-cmn' is used in the dt-binding example but is not documented.
> > - [Low] The parent node 'lvds-cmn' in the example lacks a 'ranges' property, breaking address translation for its child nodes.
> > --
> >
> > commit be595c0db2d85d9ea1396f0f30ac7ad75f4101fe
> > Author: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder
> >
> > Documents the LVDS encoder IP found on the RZ/G3L SoC. It supports
> > single-link mode and shares a peripheral clock and reset signal with the
> > MIPI-DSI interface.
> >
> > > diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> > > new file mode 100644
> > > index 0000000000000..b1f6d020ae7b1
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml
> >
> > [ ... ]
> >
> > > +examples:
> > > +  - |
> > > +    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
> > > +
> > > +    lvds-cmn@108a0000 {
> > > +        compatible = "renesas,r9a08g046-lvds-cmn",
> > > +                     "simple-mfd", "syscon";
> >
> > [Severity: Low]
> > Is this compatible string documented somewhere else? It looks like
> > renesas,r9a08g046-lvds-cmn isn't present in the tree, which might cause
> > dt_binding_check to fail when it validates the example.
> 
> This compatible is documented and is in next [1].
> 
> Q1) Can you please reun the AI review with [1] ?
> 
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20260522&id=51284d8b1dbcd7fa0220c49eeab29b14617e0d88
> 
> >
> > > +        reg = <0x108a0000 0x10000>;
> > > +        #address-cells = <1>;
> > > +        #size-cells = <1>;
> >
> > [Severity: Low]
> > Does this parent node need a ranges property? Without it, address translation
> > for the child node's reg = <0x10 0x8> might fail, and dtc often warns about
> > missing ranges in simple-mfd nodes with children.
> 
> I don't get any error or dtc warnings. Have you ran dt-binding check
> before providing
> such comment?

There probably isn't any warning, but sashiko is correct that 'ranges' 
should be present. The schema for the parent should require 'ranges'. 
The 'simple-mfd' binding does not as not all simple-mfd's have MMIO 
addresess in the child nodes.

Rob

RE: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

[Biju Das]

Hi Rob,

Thanks for the feedback.

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 01 June 2026 03:26
> Subject: Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder
> 
> On Mon, May 25, 2026 at 08:45:00AM +0100, Biju Das wrote:
> > Hi Bot,
> >
> > On Sun, May 24, 2026 at 8:58 PM <sashiko-bot@kernel.org> wrote:
> > >
> > > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> > > - [Low] The compatible string 'renesas,r9a08g046-lvds-cmn' is used in the dt-binding example but
> is not documented.
> > > - [Low] The parent node 'lvds-cmn' in the example lacks a 'ranges' property, breaking address
> translation for its child nodes.
> > > --
> > >
> > > commit be595c0db2d85d9ea1396f0f30ac7ad75f4101fe
> > > Author: Biju Das <biju.das.jz@bp.renesas.com>
> > >
> > > dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder
> > >
> > > Documents the LVDS encoder IP found on the RZ/G3L SoC. It supports
> > > single-link mode and shares a peripheral clock and reset signal with
> > > the MIPI-DSI interface.
> > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g0
> > > > 46-lvds.yaml
> > > > b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g0
> > > > 46-lvds.yaml
> > > > new file mode 100644
> > > > index 0000000000000..b1f6d020ae7b1
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a
> > > > +++ 08g046-lvds.yaml
> > >
> > > [ ... ]
> > >
> > > > +examples:
> > > > +  - |
> > > > +    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
> > > > +
> > > > +    lvds-cmn@108a0000 {
> > > > +        compatible = "renesas,r9a08g046-lvds-cmn",
> > > > +                     "simple-mfd", "syscon";
> > >
> > > [Severity: Low]
> > > Is this compatible string documented somewhere else? It looks like
> > > renesas,r9a08g046-lvds-cmn isn't present in the tree, which might
> > > cause dt_binding_check to fail when it validates the example.
> >
> > This compatible is documented and is in next [1].
> >
> > Q1) Can you please reun the AI review with [1] ?
> >
> > [1]
> > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/co
> > mmit/?h=next-20260522&id=51284d8b1dbcd7fa0220c49eeab29b14617e0d88
> >
> > >
> > > > +        reg = <0x108a0000 0x10000>;
> > > > +        #address-cells = <1>;
> > > > +        #size-cells = <1>;
> > >
> > > [Severity: Low]
> > > Does this parent node need a ranges property? Without it, address
> > > translation for the child node's reg = <0x10 0x8> might fail, and
> > > dtc often warns about missing ranges in simple-mfd nodes with children.
> >
> > I don't get any error or dtc warnings. Have you ran dt-binding check
> > before providing such comment?
> 
> There probably isn't any warning, but sashiko is correct that 'ranges'
> should be present. The schema for the parent should require 'ranges'.
> The 'simple-mfd' binding does not as not all simple-mfd's have MMIO addresess in the child nodes.

OK, I will send a patch for RZ/G3L with below changes as it has MMIO address.

+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a08g046-lvds-cmn
+    then:
+      properties:
+        ranges: true
+
+      required:
+        - ranges


Cheers,
Biju

RE: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder

[Biju Das]

+ Lee Jones

> -----Original Message-----
> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 01 June 2026 11:21
> Subject: RE: [PATCH v2 1/2] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder
> 
> Hi Rob,
> 
> Thanks for the feedback.
> 
> > -----Original Message-----
> > From: Rob Herring <robh@kernel.org>
> > Sent: 01 June 2026 03:26
> > Subject: Re: [PATCH v2 1/2] dt-bindings: display: bridge: Document
> > Renesas RZ/G3L LVDS encoder
> >
> > On Mon, May 25, 2026 at 08:45:00AM +0100, Biju Das wrote:
> > > Hi Bot,
> > >
> > > On Sun, May 24, 2026 at 8:58 PM <sashiko-bot@kernel.org> wrote:
> > > >
> > > > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> > > > - [Low] The compatible string 'renesas,r9a08g046-lvds-cmn' is used
> > > > in the dt-binding example but
> > is not documented.
> > > > - [Low] The parent node 'lvds-cmn' in the example lacks a 'ranges'
> > > > property, breaking address
> > translation for its child nodes.
> > > > --
> > > >
> > > > commit be595c0db2d85d9ea1396f0f30ac7ad75f4101fe
> > > > Author: Biju Das <biju.das.jz@bp.renesas.com>
> > > >
> > > > dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder
> > > >
> > > > Documents the LVDS encoder IP found on the RZ/G3L SoC. It supports
> > > > single-link mode and shares a peripheral clock and reset signal
> > > > with the MIPI-DSI interface.
> > > >
> > > > > diff --git
> > > > > a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08
> > > > > g0
> > > > > 46-lvds.yaml
> > > > > b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08
> > > > > g0
> > > > > 46-lvds.yaml
> > > > > new file mode 100644
> > > > > index 0000000000000..b1f6d020ae7b1
> > > > > --- /dev/null
> > > > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r
> > > > > +++ 9a
> > > > > +++ 08g046-lvds.yaml
> > > >
> > > > [ ... ]
> > > >
> > > > > +examples:
> > > > > +  - |
> > > > > +    #include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
> > > > > +
> > > > > +    lvds-cmn@108a0000 {
> > > > > +        compatible = "renesas,r9a08g046-lvds-cmn",
> > > > > +                     "simple-mfd", "syscon";
> > > >
> > > > [Severity: Low]
> > > > Is this compatible string documented somewhere else? It looks like
> > > > renesas,r9a08g046-lvds-cmn isn't present in the tree, which might
> > > > cause dt_binding_check to fail when it validates the example.
> > >
> > > This compatible is documented and is in next [1].
> > >
> > > Q1) Can you please reun the AI review with [1] ?
> > >
> > > [1]
> > > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/
> > > co
> > > mmit/?h=next-20260522&id=51284d8b1dbcd7fa0220c49eeab29b14617e0d88
> > >
> > > >
> > > > > +        reg = <0x108a0000 0x10000>;
> > > > > +        #address-cells = <1>;
> > > > > +        #size-cells = <1>;
> > > >
> > > > [Severity: Low]
> > > > Does this parent node need a ranges property? Without it, address
> > > > translation for the child node's reg = <0x10 0x8> might fail, and
> > > > dtc often warns about missing ranges in simple-mfd nodes with children.
> > >
> > > I don't get any error or dtc warnings. Have you ran dt-binding check
> > > before providing such comment?
> >
> > There probably isn't any warning, but sashiko is correct that 'ranges'
> > should be present. The schema for the parent should require 'ranges'.
> > The 'simple-mfd' binding does not as not all simple-mfd's have MMIO addresess in the child nodes.
> 
> OK, I will send a patch for RZ/G3L with below changes as it has MMIO address.
> 
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a08g046-lvds-cmn
> +    then:
> +      properties:
> +        ranges: true
> +
> +      required:
> +        - ranges
> 
> 
> Cheers,
> Biju