From: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: Alistair Francis <alistair23@gmail.com>, <qemu-devel@nongnu.org>,
"Michal Simek" <michal.simek@amd.com>,
Alistair Francis <alistair.francis@wdc.com>,
Anton Johansson <anjo@rev.ng>
Subject: Re: [PULL v2 19/39] hw/riscv: Add Microblaze V generic board
Date: Wed, 3 Jun 2026 20:35:45 +0530 [thread overview]
Message-ID: <aiBCycdn/2THWQrd@xhdsaipava41> (raw)
In-Reply-To: <85827a75-e224-448d-8c16-5ca9238737e5@linaro.org>
On Tue, May 26, 2026 at 10:34:04AM +0200, Philippe Mathieu-Daudé wrote:
Hi Philippe,
> Hi Sai,
>
> On 20/12/24 02:54, Alistair Francis wrote:
> > From: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
> >
> > Add a basic board with interrupt controller (intc), timer, serial
> > (uartlite), small memory called LMB@0 (128kB) and DDR@0x80000000
> > (configured via command line eg. -m 2g).
> > This is basic configuration which matches HW generated out of AMD Vivado
> > (design tools). But initial configuration is going beyond what it is
> > configured by default because validation should be done on other
> > configurations too. That's why wire also additional uart16500, axi
> > ethernet(with axi dma).
> > GPIOs, i2c and qspi is also listed for completeness.
> >
> > IRQ map is: (addr)
> > 0 - timer (0x41c00000)
> > 1 - uartlite (0x40600000)
> > 2 - i2c (0x40800000)
> > 3 - qspi (0x44a00000)
> > 4 - uart16550 (0x44a10000)
> > 5 - emaclite (0x40e00000)
> > 6 - timer2 (0x41c10000)
> > 7 - axi emac (0x40c00000)
> > 8 - axi dma (0x41e00000)
> > 9 - axi dma
> > 10 - gpio (0x40000000)
> > 11 - gpio2 (0x40010000)
> > 12 - gpio3 (0x40020000)
> >
> > Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
> > Signed-off-by: Michal Simek <michal.simek@amd.com>
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > Message-ID: <20241125134739.18189-1-sai.pavan.boddu@amd.com>
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > MAINTAINERS | 6 +
> > docs/system/riscv/microblaze-v-generic.rst | 42 +++++
> > docs/system/target-riscv.rst | 1 +
> > hw/riscv/microblaze-v-generic.c | 184 +++++++++++++++++++++
> > hw/riscv/Kconfig | 8 +
> > hw/riscv/meson.build | 1 +
> > 6 files changed, 242 insertions(+)
> > create mode 100644 docs/system/riscv/microblaze-v-generic.rst
> > create mode 100644 hw/riscv/microblaze-v-generic.c
>
>
> > +static void mb_v_generic_machine_init(MachineClass *mc)
> > +{
> > + mc->desc = "AMD Microblaze-V generic platform";
> > + mc->init = mb_v_generic_init;
> > + mc->min_cpus = 1;
> > + mc->max_cpus = 1;
> > + mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
>
> Could you use or provide a proper CPU type for this machine?
since MicroBlaze-V extensions are FPGA-design-time configurable,
the CPU type inherits from `DYNAMIC_CPU` to allow CLI configuration,
with sensible defaults for a typical MicroBlaze-V configuration.
We need a new type `amd-microblaze-v` that inherits from DYNAMIC_CPU,
allowing users to specify extensions via command line matching
their design (e.g., `-cpu amd-microblaze-v,m=true,c=true`).
Does that sound good? Would you like me to send a patch for it?
Regards,
Sai Pavan
>
Regards,
Sai Pavan
>
> > + mc->default_cpus = 1;
> > +}
>
next prev parent reply other threads:[~2026-06-03 15:11 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-20 1:54 [PULL v2 00/39] riscv-to-apply queue Alistair Francis
2024-12-20 1:54 ` [PULL v2 01/39] hw/riscv/riscv-iommu.c: Correct the validness check of iova Alistair Francis
2024-12-20 1:54 ` [PULL v2 02/39] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation Alistair Francis
2024-12-20 1:54 ` [PULL v2 03/39] hw/riscv/riscv-iommu.c: add riscv_iommu_instance_init() Alistair Francis
2024-12-20 1:54 ` [PULL v2 04/39] hw/riscv/riscv-iommu: parametrize CAP.IGS Alistair Francis
2024-12-20 1:54 ` [PULL v2 05/39] hw/riscv: add riscv-iommu-sys platform device Alistair Francis
2024-12-20 1:54 ` [PULL v2 06/39] hw/riscv/virt: Add IOMMU as platform device if the option is set Alistair Francis
2024-12-20 1:54 ` [PULL v2 07/39] hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support Alistair Francis
2024-12-20 1:54 ` [PULL v2 08/39] hw/riscv/riscv-iommu: implement reset protocol Alistair Francis
2024-12-20 1:54 ` [PULL v2 09/39] docs/specs: add riscv-iommu-sys information Alistair Francis
2024-12-20 1:54 ` [PULL v2 10/39] target/riscv: Add Tenstorrent Ascalon CPU Alistair Francis
2024-12-20 1:54 ` [PULL v2 11/39] hw/intc/riscv_aplic: rename is_kvm_aia() Alistair Francis
2024-12-20 1:54 ` [PULL v2 12/39] hw/riscv/virt.c: reduce virt_use_kvm_aia() usage Alistair Francis
2024-12-20 1:54 ` [PULL v2 13/39] hw/riscv/virt.c: rename helper to virt_use_kvm_aia_aplic_imsic() Alistair Francis
2024-12-20 1:54 ` [PULL v2 14/39] target/riscv/kvm: consider irqchip_split() in aia_create() Alistair Francis
2024-12-20 1:54 ` [PULL v2 15/39] hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers Alistair Francis
2024-12-20 1:54 ` [PULL v2 16/39] hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic Alistair Francis
2024-12-20 1:54 ` [PULL v2 17/39] target/riscv/kvm: remove irqchip_split() restriction Alistair Francis
2024-12-20 1:54 ` [PULL v2 18/39] docs: update riscv/virt.rst with kernel-irqchip=split support Alistair Francis
2024-12-20 1:54 ` [PULL v2 19/39] hw/riscv: Add Microblaze V generic board Alistair Francis
2026-05-26 8:34 ` Philippe Mathieu-Daudé
2026-06-03 15:05 ` Sai Pavan Boddu [this message]
2024-12-20 1:54 ` [PULL v2 20/39] qtest: allow SPCR acpi table changes Alistair Francis
2024-12-20 1:54 ` [PULL v2 21/39] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format Alistair Francis
2024-12-20 1:54 ` [PULL v2 22/39] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V Alistair Francis
2024-12-20 1:54 ` [PULL v2 23/39] MAINTAINERS: Cover RISC-V HTIF interface Alistair Francis
2024-12-20 1:54 ` [PULL v2 24/39] hw/char/riscv_htif: Explicit little-endian implementation Alistair Francis
2024-12-20 1:54 ` [PULL v2 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses Alistair Francis
2024-12-20 1:54 ` [PULL v2 26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system Alistair Francis
2024-12-20 1:54 ` [PULL v2 27/39] hw/riscv: Add a new struct RISCVBootInfo Alistair Francis
2024-12-20 1:54 ` [PULL v2 28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd Alistair Francis
2024-12-20 1:54 ` [PULL v2 29/39] target/riscv: Add svukte extension capability variable Alistair Francis
2024-12-20 1:54 ` [PULL v2 30/39] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled Alistair Francis
2024-12-20 1:54 ` [PULL v2 31/39] target/riscv: Support hstatus[HUKTE] " Alistair Francis
2024-12-20 1:54 ` [PULL v2 32/39] target/riscv: Check memory access to meet svukte rule Alistair Francis
2024-12-20 1:54 ` [PULL v2 33/39] target/riscv: Expose svukte ISA extension Alistair Francis
2024-12-20 1:54 ` [PULL v2 34/39] target/riscv: Check svukte is not enabled in RV32 Alistair Francis
2024-12-20 1:54 ` [PULL v2 35/39] target/riscv: Include missing headers in 'vector_internals.h' Alistair Francis
2024-12-20 1:54 ` [PULL v2 36/39] target/riscv: Include missing headers in 'internals.h' Alistair Francis
2024-12-20 1:54 ` [PULL v2 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver Alistair Francis
2024-12-20 1:54 ` [PULL v2 38/39] target/riscv: add ssstateen Alistair Francis
2024-12-20 1:54 ` [PULL v2 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU Alistair Francis
2024-12-21 17:51 ` [PULL v2 00/39] riscv-to-apply queue Stefan Hajnoczi
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