* [PATCH v2 1/2] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v3.1
2026-06-03 17:10 [PATCH v2 0/2] x86/cpuid: kcpuid: v3.1 x86-cpuid-db update with fixes Maciej Wieczor-Retman
@ 2026-06-03 17:10 ` Maciej Wieczor-Retman
2026-06-03 17:10 ` [PATCH v2 2/2] x86/cpuid: " Maciej Wieczor-Retman
1 sibling, 0 replies; 7+ messages in thread
From: Maciej Wieczor-Retman @ 2026-06-03 17:10 UTC (permalink / raw)
To: mingo, dave.hansen, bp
Cc: hpa, darwi, tglx, sohil.mehta, andrew.cooper3, linux-kernel, x86,
m.wieczorretman, john.ogness, ludloff, maciej.wieczor-retman,
x86-cpuid
From: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Update kcpuid's CSV file to version 3.1, as generated by x86-cpuid-db.
Summary of the v3.1 changes:
* Fix a few typos that were found during the kernel CPUID data model
review. Also include fixes found using an LLM agent review.
* Rename thrd_director_nclasses to hw_feedback_nclasses as it's the
name used in Intel SDM.
Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v3.1/CHANGELOG.rst
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
---
tools/arch/x86/kcpuid/cpuid.csv | 52 ++++++++++++++++-----------------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.csv
index 9f5155c825ca..45a876d3519f 100644
--- a/tools/arch/x86/kcpuid/cpuid.csv
+++ b/tools/arch/x86/kcpuid/cpuid.csv
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: CC0-1.0
-# Generator: x86-cpuid-db v3.0
+# Generator: x86-cpuid-db v3.1
#
# Auto-generated file.
@@ -177,7 +177,7 @@
0x6, 0, ebx, 3:0, n_therm_thresholds , Digital thermometer thresholds
0x6, 0, ecx, 0, aperfmperf , MPERF/APERF MSRs (effective frequency interface)
0x6, 0, ecx, 3, epb , IA32_ENERGY_PERF_BIAS MSR
- 0x6, 0, ecx, 15:8, thrd_director_nclasses , Number of classes, Intel thread director
+ 0x6, 0, ecx, 15:8, hw_feedback_nclasses , Number of Intel Thread Director classes
0x6, 0, edx, 0, perfcap_reporting , Performance capability reporting
0x6, 0, edx, 1, encap_reporting , Energy efficiency capability reporting
0x6, 0, edx, 11:8, feedback_sz , Feedback interface structure size, in 4K pages
@@ -247,10 +247,10 @@
0x7, 0, edx, 1, sgx_keys , Intel SGX attestation services
0x7, 0, edx, 2, avx512_4vnniw , AVX-512 neural network instructions
0x7, 0, edx, 3, avx512_4fmaps , AVX-512 multiply accumulation single precision
- 0x7, 0, edx, 4, fsrm , Fast short REP MOV
+ 0x7, 0, edx, 4, fsrm , Fast short REP MOVSB
0x7, 0, edx, 5, uintr , User interrupts
0x7, 0, edx, 8, avx512_vp2intersect , VP2INTERSECT{D,Q} instructions
- 0x7, 0, edx, 9, srdbs_ctrl , SRBDS mitigation MSR
+ 0x7, 0, edx, 9, srbds_ctrl , SRBDS mitigation MSR
0x7, 0, edx, 10, md_clear , VERW MD_CLEAR microcode
0x7, 0, edx, 11, rtm_always_abort , XBEGIN (RTM transaction) always aborts
0x7, 0, edx, 13, tsx_force_abort , MSR TSX_FORCE_ABORT, RTM_ABORT bit
@@ -296,8 +296,8 @@
0x7, 2, edx, 0, intel_psfd , Intel predictive store forward disable
0x7, 2, edx, 1, ipred_ctrl , MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}
0x7, 2, edx, 2, rrsba_ctrl , MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}
- 0x7, 2, edx, 3, ddp_ctrl , MSR bit IA32_SPEC_CTRL.DDPD_U
- 0x7, 2, edx, 4, bhi_ctrl , MSR bit IA32_SPEC_CTRL.BHI_DIS_S
+ 0x7, 2, edx, 3, ddp_ctrl , MSR bit IA32_SPEC_CTRL.DDPD_U
+ 0x7, 2, edx, 4, bhi_ctrl , MSR bit IA32_SPEC_CTRL.BHI_DIS_S
0x7, 2, edx, 5, mcdt_no , MCDT mitigation not needed
0x7, 2, edx, 6, uclock_disable , UC-lock disable
@@ -368,7 +368,7 @@
0xd, 1, ecx, 8, xss_pt , PT state
0xd, 1, ecx, 10, xss_pasid , PASID state
0xd, 1, ecx, 11, xss_cet_u , CET user state
- 0xd, 1, ecx, 12, xss_cet_p , CET supervisor state
+ 0xd, 1, ecx, 12, xss_cet_s , CET supervisor state
0xd, 1, ecx, 13, xss_hdc , HDC state
0xd, 1, ecx, 14, xss_uintr , UINTR state
0xd, 1, ecx, 15, xss_lbr , LBR state
@@ -433,7 +433,7 @@
0x12, 1, eax, 7, secs_attr_kss , Key Separation and Sharing
0x12, 1, eax, 10, secs_attr_aexnotify , Enclave threads: AEX notifications
0x12, 1, ecx, 0, xfrm_x87 , Enclave XFRM.X87
- 0x12, 1, ecx, 1, xfrm_sse , Enclave XFRM.SEE
+ 0x12, 1, ecx, 1, xfrm_sse , Enclave XFRM.SSE
0x12, 1, ecx, 2, xfrm_avx , Enclave XFRM.AVX
0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave XFRM.BNDREGS (MPX BND0-BND3 registers)
0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave XFRM.BNDCSR (MPX BNDCFGU/BNDSTATUS registers)
@@ -466,9 +466,9 @@
0x14, 0, ecx, 0, topa_output , ToPA output scheme
0x14, 0, ecx, 1, topa_multiple_entries , ToPA tables can hold multiple entries
0x14, 0, ecx, 2, single_range_output , Single-range output
- 0x14, 0, ecx, 3, trance_transport_output, Trace Transport subsystem output
+ 0x14, 0, ecx, 3, trace_transport_output , Trace Transport subsystem output
0x14, 0, ecx, 31, ip_payloads_lip , IP payloads have LIP values (CS base included)
- 0x14, 1, eax, 2:0, num_address_ranges , Number of configurable Address Ranges
+ 0x14, 1, eax, 2:0, num_address_ranges , Number of configurable address ranges
0x14, 1, eax, 31:16, mtc_periods_bmp , MTC period encodings bitmap
0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Cycle Threshold encodings bitmap
0x14, 1, ebx, 31:16, psb_periods_bmp , Configurable PSB frequency encodings bitmap
@@ -494,7 +494,7 @@
0x17, 0, ebx, 15:0, soc_vendor_id , SoC vendor ID
0x17, 0, ebx, 16, is_vendor_scheme , Assigned by industry enumeration scheme (not Intel)
0x17, 0, ecx, 31:0, soc_proj_id , SoC project ID, assigned by vendor
- 0x17, 0, edx, 31:0, soc_stepping_id , Soc project stepping ID, assigned by vendor
+ 0x17, 0, edx, 31:0, soc_stepping_id , SoC project stepping ID, assigned by vendor
0x17, 3:1, eax, 31:0, vendor_brand_a , Vendor Brand ID string, bytes subleaf_nr * (0 -> 3)
0x17, 3:1, ebx, 31:0, vendor_brand_b , Vendor Brand ID string, bytes subleaf_nr * (4 -> 7)
0x17, 3:1, ecx, 31:0, vendor_brand_c , Vendor Brand ID string, bytes subleaf_nr * (8 -> 11)
@@ -514,12 +514,12 @@
0x18, 31:0, edx, 4:0, tlb_type , Translation cache type (TLB type)
0x18, 31:0, edx, 7:5, tlb_cache_level , Translation cache level (1-based)
0x18, 31:0, edx, 8, is_fully_associative , Fully-associative
- 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max number of addressable IDs - 1
+ 0x18, 31:0, edx, 25:14, tlb_max_addressable_ids, Max number of addressable IDs - 1
# Leaf 19H
# Intel key locker
- 0x19, 0, eax, 0, kl_cpl0_only , CPL0-only key Locker restriction
+ 0x19, 0, eax, 0, kl_cpl0_only , CPL0-only key locker restriction
0x19, 0, eax, 1, kl_no_encrypt , No-encrypt key locker restriction
0x19, 0, eax, 2, kl_no_decrypt , No-decrypt key locker restriction
0x19, 0, ebx, 0, aes_keylocker , AES key locker instructions
@@ -546,7 +546,7 @@
# Intel LBR (Last Branch Record)
0x1c, 0, eax, 7:0, lbr_depth_mask , Max LBR stack depth bitmask
- 0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs maybe cleared on MWAIT C-state > C1
+ 0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs may be cleared on MWAIT C-state > C1
0x1c, 0, eax, 31, lbr_ip_is_lip , LBR IP contain Last IP (otherwise effective IP)
0x1c, 0, ebx, 0, lbr_cpl , CPL filtering
0x1c, 0, ebx, 1, lbr_branch_filter , Branch filtering
@@ -591,8 +591,8 @@
# Intel TD (Trust Domain)
0x21, 0, ebx, 31:0, tdx_vendorid_0 , TDX vendor ID string bytes 0 - 3
- 0x21, 0, ecx, 31:0, tdx_vendorid_2 , CPU vendor ID string bytes 8 - 11
- 0x21, 0, edx, 31:0, tdx_vendorid_1 , CPU vendor ID string bytes 4 - 7
+ 0x21, 0, ecx, 31:0, tdx_vendorid_2 , TDX vendor ID string bytes 8 - 11
+ 0x21, 0, edx, 31:0, tdx_vendorid_1 , TDX vendor ID string bytes 4 - 7
# Leaf 23H
# Intel Architectural Performance Monitoring Extended (ArchPerfmonExt)
@@ -857,7 +857,7 @@
0x8000000a, 0, edx, 1, lbrv , LBR virtualization
0x8000000a, 0, edx, 2, svm_lock , SVM lock
0x8000000a, 0, edx, 3, nrip_save , NRIP save support on #VMEXIT
-0x8000000a, 0, edx, 4, tsc_scale , MSR based TSC rate control
+0x8000000a, 0, edx, 4, tsc_scale , MSR-based TSC rate control
0x8000000a, 0, edx, 5, vmcb_clean , VMCB clean bits support
0x8000000a, 0, edx, 6, flushbyasid , Flush by ASID + Extended VMCB TLB_Control
0x8000000a, 0, edx, 7, decodeassists , Decode Assists support
@@ -895,7 +895,7 @@
0x8000001a, 0, eax, 0, fp_128 , Internal FP/SIMD exec data path is 128-bits wide
0x8000001a, 0, eax, 1, movu_preferred , SSE: MOVU* better than MOVL*/MOVH*
-0x8000001a, 0, eax, 2, fp_256 , internal FP/SSE exec data path is 256-bits wide
+0x8000001a, 0, eax, 2, fp_256 , Internal FP/SSE exec data path is 256-bits wide
# Leaf 8000001BH
# AMD IBS (Instruction-Based Sampling)
@@ -917,7 +917,7 @@
# AMD LWP (Lightweight Profiling)
0x8000001c, 0, eax, 0, os_lwp_avail , OS: LWP is available to application programs
-0x8000001c, 0, eax, 1, os_lpwval , OS: LWPVAL instruction
+0x8000001c, 0, eax, 1, os_lwpval , OS: LWPVAL instruction
0x8000001c, 0, eax, 2, os_lwp_ire , OS: Instructions Retired Event
0x8000001c, 0, eax, 3, os_lwp_bre , OS: Branch Retired Event
0x8000001c, 0, eax, 4, os_lwp_dme , OS: Dcache Miss Event
@@ -934,13 +934,13 @@
0x8000001c, 0, ecx, 5, lwp_data_addr , Cache miss events report data cache address
0x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Cache latency rounding amount
0x8000001c, 0, ecx, 15:9, lwp_version , LWP version
-0x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP event ring buffer min size, 32 event records units
+0x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP event ring buffer min size, 32 event record units
0x8000001c, 0, ecx, 28, lwp_branch_predict , Branches Retired events can be filtered
0x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filtering (IPI, IPF, BaseIP, and LimitIP @ LWPCP)
0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-related events: filter by cache level
0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-related events: filter by latency
0x8000001c, 0, edx, 0, hw_lwp_avail , HW: LWP available
-0x8000001c, 0, edx, 1, hw_lpwval , HW: LWPVAL available
+0x8000001c, 0, edx, 1, hw_lwpval , HW: LWPVAL available
0x8000001c, 0, edx, 2, hw_lwp_ire , HW: Instructions Retired Event
0x8000001c, 0, edx, 3, hw_lwp_bre , HW: Branch Retired Event
0x8000001c, 0, edx, 4, hw_lwp_dme , HW: Dcache Miss Event
@@ -1040,8 +1040,8 @@
0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR Upper Address Ignore
0x80000021, 0, eax, 8, autoibrs , EFER MSR Automatic IBRS
0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL MSR not available
-0x80000021, 0, eax, 10, fsrs , Fast Short Rep STOSB
-0x80000021, 0, eax, 11, fsrc , Fast Short Rep CMPSB
+0x80000021, 0, eax, 10, fsrs , Fast Short REP STOSB
+0x80000021, 0, eax, 11, fsrc , Fast Short REP CMPSB
0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch control MSR
0x80000021, 0, eax, 16, opcode_reclaim , Reserves opcode space
0x80000021, 0, eax, 17, user_cpuid_disable , #GP when executing CPUID at CPL > 0
@@ -1093,9 +1093,9 @@
# Maximum Transmeta leaf + CPU vendor string
0x80860000, 0, eax, 31:0, max_tra_leaf , Maximum Transmeta leaf
-0x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmeta Vendor ID string bytes 0 - 3
-0x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmeta Vendor ID string bytes 8 - 11
-0x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmeta Vendor ID string bytes 4 - 7
+0x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmeta vendor ID string bytes 0 - 3
+0x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmeta vendor ID string bytes 8 - 11
+0x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmeta vendor ID string bytes 4 - 7
# Leaf 80860001H
# Transmeta extended CPU features
--
2.54.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v2 2/2] x86/cpuid: Update bitfields to x86-cpuid-db v3.1
2026-06-03 17:10 [PATCH v2 0/2] x86/cpuid: kcpuid: v3.1 x86-cpuid-db update with fixes Maciej Wieczor-Retman
2026-06-03 17:10 ` [PATCH v2 1/2] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v3.1 Maciej Wieczor-Retman
@ 2026-06-03 17:10 ` Maciej Wieczor-Retman
2026-06-04 7:41 ` Ingo Molnar
1 sibling, 1 reply; 7+ messages in thread
From: Maciej Wieczor-Retman @ 2026-06-03 17:10 UTC (permalink / raw)
To: mingo, dave.hansen, bp
Cc: hpa, darwi, tglx, sohil.mehta, andrew.cooper3, linux-kernel, x86,
m.wieczorretman, john.ogness, ludloff, maciej.wieczor-retman,
x86-cpuid
From: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Update leaf_types.h to version 3.1, as generated by x86-cpuid-db.
Summary of the v3.1 changes:
* Fix a few typos that were found during the kernel CPUID data model
review. Also include fixes found using an LLM agent review.
* Rename thrd_director_nclasses to hw_feedback_nclasses as it's the
name used in Intel SDM.
Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v3.1/CHANGELOG.rst
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
---
arch/x86/include/asm/cpuid/leaf_types.h | 62 ++++++++++++-------------
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/arch/x86/include/asm/cpuid/leaf_types.h b/arch/x86/include/asm/cpuid/leaf_types.h
index 5b0008e455e2..222d2d2682c8 100644
--- a/arch/x86/include/asm/cpuid/leaf_types.h
+++ b/arch/x86/include/asm/cpuid/leaf_types.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: MIT */
-/* Generator: x86-cpuid-db v3.0 */
+/* Generator: x86-cpuid-db v3.1 */
/*
* Auto-generated file.
@@ -246,7 +246,7 @@ struct leaf_0x6_0 {
: 2, // Reserved
energy_perf_bias : 1, // IA32_ENERGY_PERF_BIAS MSR
: 4, // Reserved
- thrd_director_nclasses : 8, // Number of classes, Intel thread director
+ hw_feedback_nclasses : 8, // Number of Intel Thread Director classes
: 16; // Reserved
// edx
u32 perfcap_reporting : 1, // Performance capability reporting
@@ -332,11 +332,11 @@ struct leaf_0x7_0 {
sgx_keys : 1, // Intel SGX attestation services
avx512_4vnniw : 1, // AVX-512 neural network instructions
avx512_4fmaps : 1, // AVX-512 multiply accumulation single precision
- fsrm : 1, // Fast short REP MOV
+ fsrm : 1, // Fast short REP MOVSB
uintr : 1, // User interrupts
: 2, // Reserved
avx512_vp2intersect : 1, // VP2INTERSECT{D,Q} instructions
- srdbs_ctrl : 1, // SRBDS mitigation MSR
+ srbds_ctrl : 1, // SRBDS mitigation MSR
md_clear : 1, // VERW MD_CLEAR microcode
rtm_always_abort : 1, // XBEGIN (RTM transaction) always aborts
: 1, // Reserved
@@ -379,7 +379,7 @@ struct leaf_0x7_1 {
wrmsrns : 1, // WRMSRNS instruction (WRMSR-non-serializing)
nmi_src : 1, // NMI-source reporting with FRED event data
amx_fp16 : 1, // AMX-FP16: FP16 tile operations
- hreset : 1, // HRESET (Thread director history reset)
+ hreset : 1, // HRESET (Thread director history reset)
avx_ifma : 1, // Integer fused multiply add
: 2, // Reserved
lam : 1, // Linear address masking
@@ -414,8 +414,8 @@ struct leaf_0x7_2 {
u32 intel_psfd : 1, // Intel predictive store forward disable
ipred_ctrl : 1, // MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}
rrsba_ctrl : 1, // MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}
- ddp_ctrl : 1, // MSR bit IA32_SPEC_CTRL.DDPD_U
- bhi_ctrl : 1, // MSR bit IA32_SPEC_CTRL.BHI_DIS_S
+ ddp_ctrl : 1, // MSR bit IA32_SPEC_CTRL.DDPD_U
+ bhi_ctrl : 1, // MSR bit IA32_SPEC_CTRL.BHI_DIS_S
mcdt_no : 1, // MCDT mitigation not needed
uclock_disable : 1, // UC-lock disable
: 25; // Reserved
@@ -547,7 +547,7 @@ struct leaf_0xd_1 {
: 1, // Reserved
xss_pasid : 1, // PASID state
xss_cet_u : 1, // CET user state
- xss_cet_p : 1, // CET supervisor state
+ xss_cet_s : 1, // CET supervisor state
xss_hdc : 1, // HDC state
xss_uintr : 1, // UINTR state
xss_lbr : 1, // LBR state
@@ -711,7 +711,7 @@ struct leaf_0x12_1 {
u32 : 32; // Reserved
// ecx
u32 xfrm_x87 : 1, // Enclave XFRM.X87
- xfrm_sse : 1, // Enclave XFRM.SEE
+ xfrm_sse : 1, // Enclave XFRM.SSE
xfrm_avx : 1, // Enclave XFRM.AVX
xfrm_mpx_bndregs : 1, // Enclave XFRM.BNDREGS (MPX BND0-BND3 registers)
xfrm_mpx_bndcsr : 1, // Enclave XFRM.BNDCSR (MPX BNDCFGU/BNDSTATUS registers)
@@ -771,7 +771,7 @@ struct leaf_0x14_0 {
u32 topa_output : 1, // ToPA output scheme
topa_multiple_entries : 1, // ToPA tables can hold multiple entries
single_range_output : 1, // Single-range output
- trance_transport_output : 1, // Trace Transport subsystem output
+ trace_transport_output : 1, // Trace Transport subsystem output
: 27, // Reserved
ip_payloads_lip : 1; // IP payloads have LIP values (CS base included)
// edx
@@ -780,7 +780,7 @@ struct leaf_0x14_0 {
struct leaf_0x14_1 {
// eax
- u32 num_address_ranges : 3, // Number of configurable Address Ranges
+ u32 num_address_ranges : 3, // Number of configurable address ranges
: 13, // Reserved
mtc_periods_bmp : 16; // MTC period encodings bitmap
// ebx
@@ -842,7 +842,7 @@ struct leaf_0x17_0 {
// ecx
u32 soc_proj_id : 32; // SoC project ID, assigned by vendor
// edx
- u32 soc_stepping_id : 32; // Soc project stepping ID, assigned by vendor
+ u32 soc_stepping_id : 32; // SoC project stepping ID, assigned by vendor
};
struct leaf_0x17_n {
@@ -883,7 +883,7 @@ struct leaf_0x18_n {
tlb_cache_level : 3, // Translation cache level (1-based)
is_fully_associative : 1, // Fully-associative
: 5, // Reserved
- tlb_max_addressible_ids : 12, // Max number of addressable IDs - 1
+ tlb_max_addressable_ids : 12, // Max number of addressable IDs - 1
: 6; // Reserved
};
@@ -897,7 +897,7 @@ struct leaf_0x18_n {
struct leaf_0x19_0 {
// eax
- u32 kl_cpl0_only : 1, // CPL0-only key Locker restriction
+ u32 kl_cpl0_only : 1, // CPL0-only key locker restriction
kl_no_encrypt : 1, // No-encrypt key locker restriction
kl_no_decrypt : 1, // No-decrypt key locker restriction
: 29; // Reserved
@@ -962,7 +962,7 @@ struct leaf_0x1c_0 {
// eax
u32 lbr_depth_mask : 8, // Max LBR stack depth bitmask
: 22, // Reserved
- lbr_deep_c_reset : 1, // LBRs maybe cleared on MWAIT C-state > C1
+ lbr_deep_c_reset : 1, // LBRs may be cleared on MWAIT C-state > C1
lbr_ip_is_lip : 1; // LBR IP contain Last IP (otherwise effective IP)
// ebx
u32 lbr_cpl : 1, // CPL filtering
@@ -1079,9 +1079,9 @@ struct leaf_0x21_0 {
// ebx
u32 tdx_vendorid_0 : 32; // TDX vendor ID string bytes 0 - 3
// ecx
- u32 tdx_vendorid_2 : 32; // CPU vendor ID string bytes 8 - 11
+ u32 tdx_vendorid_2 : 32; // TDX vendor ID string bytes 8 - 11
// edx
- u32 tdx_vendorid_1 : 32; // CPU vendor ID string bytes 4 - 7
+ u32 tdx_vendorid_1 : 32; // TDX vendor ID string bytes 4 - 7
};
/*
@@ -1281,12 +1281,12 @@ struct leaf_0x4c780001_0 {
flexpriority : 1, // Intel FlexPriority
ept : 1, // Intel Extended Page Table
vpid : 1, // Intel Virtual Processor ID
- coherency_sfw_no : 1, // SNP cache coherency software work around not needed
+ coherency_sfw_no : 1, // SNP cache coherency software workaround not needed
: 10, // Reserved
vmmcall : 1, // Prefer VMMCALL to VMCALL
xenpv : 1, // Xen paravirtual guest
ept_ad : 1, // Intel Extended Page Table access-dirty bit
- VMCALL : 1, // Hypervisor supports the VMCALL instruction
+ vmcall : 1, // Hypervisor supports the VMCALL instruction
vmw_vmmcall : 1, // VMware prefers the VMMCALL instruction
pvunlock : 1, // PV unlock function
vcpupreempt : 1, // PV vcpu_is_preempted function
@@ -1380,11 +1380,11 @@ struct leaf_0x4c780002_0 {
amd_e400 : 1, // CPU is among the affected by Erratum 400
cpu_meltdown : 1, // CPU affected by meltdown; needs kernel page table isolation
spectre_v1 : 1, // CPU affected by Spectre variant 1 with conditional branches
- specture_v2 : 1, // CPU affected by Spectre variant 2 with indirect branches
+ spectre_v2 : 1, // CPU affected by Spectre variant 2 with indirect branches
spec_store_bypass : 1, // CPU affected by speculative store bypass attack
l1tf : 1, // CPU affected by L1 Terminal Fault
mds : 1, // CPU affected by Microarchitectural data sampling
- msbds_only : 1, // Microarchitectural data sampling: CPU only affected by the MSDBS variant
+ msbds_only : 1, // Microarchitectural data sampling: CPU only affected by the MSBDS variant
swapgs : 1, // CPU affected by speculation through SWAPGS
taa : 1, // CPU is affected by TSX Async Abort (TAA)
itlb_multihit : 1, // CPU may incur MCE during certain page attribute changes
@@ -1732,7 +1732,7 @@ struct leaf_0x8000000a_0 {
lbr_virt : 1, // LBR virtualization
svm_lock : 1, // SVM lock
nrip_save : 1, // NRIP save support on #VMEXIT
- tsc_rate_msr : 1, // MSR based TSC rate control
+ tsc_rate_msr : 1, // MSR-based TSC rate control
vmcb_clean : 1, // VMCB clean bits support
flush_by_asid : 1, // Flush by ASID + Extended VMCB TLB_Control
decode_assists : 1, // Decode Assists support
@@ -1790,7 +1790,7 @@ struct leaf_0x8000001a_0 {
// eax
u32 fp_128 : 1, // Internal FP/SIMD exec data path is 128-bits wide
movu_preferred : 1, // SSE: MOVU* better than MOVL*/MOVH*
- fp_256 : 1, // internal FP/SSE exec data path is 256-bits wide
+ fp_256 : 1, // Internal FP/SSE exec data path is 256-bits wide
: 29; // Reserved
// ebx
u32 : 32; // Reserved
@@ -1836,7 +1836,7 @@ struct leaf_0x8000001b_0 {
struct leaf_0x8000001c_0 {
// eax
u32 os_lwp_avail : 1, // OS: LWP is available to application programs
- os_lpwval : 1, // OS: LWPVAL instruction
+ os_lwpval : 1, // OS: LWPVAL instruction
os_lwp_ire : 1, // OS: Instructions Retired Event
os_lwp_bre : 1, // OS: Branch Retired Event
os_lwp_dme : 1, // OS: Dcache Miss Event
@@ -1856,7 +1856,7 @@ struct leaf_0x8000001c_0 {
lwp_data_addr : 1, // Cache miss events report data cache address
lwp_latency_rnd : 3, // Cache latency rounding amount
lwp_version : 7, // LWP version
- lwp_buf_min_sz : 8, // LWP event ring buffer min size, 32 event records units
+ lwp_buf_min_sz : 8, // LWP event ring buffer min size, 32 event record units
: 4, // Reserved
lwp_branch_predict : 1, // Branches Retired events can be filtered
lwp_ip_filtering : 1, // IP filtering (IPI, IPF, BaseIP, and LimitIP @ LWPCP)
@@ -1864,7 +1864,7 @@ struct leaf_0x8000001c_0 {
lwp_cache_latency : 1; // Cache-related events: filter by latency
// edx
u32 hw_lwp_avail : 1, // HW: LWP available
- hw_lpwval : 1, // HW: LWPVAL available
+ hw_lwpval : 1, // HW: LWPVAL available
hw_lwp_ire : 1, // HW: Instructions Retired Event
hw_lwp_bre : 1, // HW: Branch Retired Event
hw_lwp_dme : 1, // HW: Dcache Miss Event
@@ -2051,8 +2051,8 @@ struct leaf_0x80000021_0 {
upper_addr_ignore : 1, // EFER MSR Upper Address Ignore
auto_ibrs : 1, // EFER MSR Automatic IBRS
no_smm_ctl_msr : 1, // SMM_CTL MSR not available
- fsrs : 1, // Fast Short Rep STOSB
- fsrc : 1, // Fast Short Rep CMPSB
+ fsrs : 1, // Fast Short REP STOSB
+ fsrc : 1, // Fast Short REP CMPSB
: 1, // Reserved
prefetch_ctl_msr : 1, // Prefetch control MSR
: 2, // Reserved
@@ -2157,11 +2157,11 @@ struct leaf_0x80860000_0 {
// eax
u32 max_tra_leaf : 32; // Maximum Transmeta leaf
// ebx
- u32 cpu_vendorid_0 : 32; // Transmeta Vendor ID string bytes 0 - 3
+ u32 cpu_vendorid_0 : 32; // Transmeta vendor ID string bytes 0 - 3
// ecx
- u32 cpu_vendorid_2 : 32; // Transmeta Vendor ID string bytes 8 - 11
+ u32 cpu_vendorid_2 : 32; // Transmeta vendor ID string bytes 8 - 11
// edx
- u32 cpu_vendorid_1 : 32; // Transmeta Vendor ID string bytes 4 - 7
+ u32 cpu_vendorid_1 : 32; // Transmeta vendor ID string bytes 4 - 7
};
/*
--
2.54.0
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