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From: Joshua Milas <josh.milas@gmail.com>
To: Shuwei Wu <shuwei.wu@mailbox.org>
Cc: tglx@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, pjw@kernel.org, samuel.holland@sifive.com,
	unicorn_wang@outlook.com, inochiama@gmail.com,
	daniel.lezcano@linaro.org, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, alex@ghiti.fr,
	liujingqi@lanxincomputing.com, alexander.sverdlin@gmail.com,
	rabenda.cn@gmail.com, dlan@kernel.org, chao.wei@sophgo.com,
	anup@brainfault.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	sophgo@lists.linux.dev, hanguidong02@gmail.com,
	michael.opdenacker@rootcommit.com,
	linux-riscv <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH v5 RESEND 4/5] riscv64: dts: sophgo: add SG2000 dtsi
Date: Mon, 8 Jun 2026 08:06:59 -0400	[thread overview]
Message-ID: <aiawY8BlHlSFXbSJ@sleek> (raw)
In-Reply-To: <DJ10GDDAE672.1N365YARL5KV1@mailbox.org>

Hi Shuwei,

The 256 MB was not intentional and was a holdover from testing. I updated the
DT to use 512 MB of RAM. The issue was only on the riscv side. This will be
fixed in the next patch.

- Joshua Milas

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Joshua Milas <josh.milas@gmail.com>
To: Shuwei Wu <shuwei.wu@mailbox.org>
Cc: tglx@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, pjw@kernel.org, samuel.holland@sifive.com,
	unicorn_wang@outlook.com, inochiama@gmail.com,
	daniel.lezcano@linaro.org, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, alex@ghiti.fr,
	liujingqi@lanxincomputing.com, alexander.sverdlin@gmail.com,
	rabenda.cn@gmail.com, dlan@kernel.org, chao.wei@sophgo.com,
	anup@brainfault.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	sophgo@lists.linux.dev, hanguidong02@gmail.com,
	michael.opdenacker@rootcommit.com,
	linux-riscv <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH v5 RESEND 4/5] riscv64: dts: sophgo: add SG2000 dtsi
Date: Mon, 8 Jun 2026 08:06:59 -0400	[thread overview]
Message-ID: <aiawY8BlHlSFXbSJ@sleek> (raw)
In-Reply-To: <DJ10GDDAE672.1N365YARL5KV1@mailbox.org>

Hi Shuwei,

The 256 MB was not intentional and was a holdover from testing. I updated the
DT to use 512 MB of RAM. The issue was only on the riscv side. This will be
fixed in the next patch.

- Joshua Milas

  reply	other threads:[~2026-06-08 12:07 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-30 17:33 [PATCH v5 RESEND 0/5] Add initial Milk-V Duo S board support Joshua Milas
2026-05-30 17:33 ` Joshua Milas
2026-05-30 17:33 ` [PATCH v5 RESEND 1/5] dt-bindings: soc: sophgo: add Milk-V Duo S board compatibles Joshua Milas
2026-05-30 17:33   ` Joshua Milas
2026-05-31 12:29   ` Krzysztof Kozlowski
2026-05-31 12:29     ` Krzysztof Kozlowski
2026-05-30 17:33 ` [PATCH v5 RESEND 2/5] arm64: dts: sophgo: add initial Milk-V Duo S board support Joshua Milas
2026-05-30 17:33   ` Joshua Milas
2026-05-30 17:46   ` sashiko-bot
2026-05-30 22:01   ` Inochi Amaoto
2026-05-30 22:01     ` Inochi Amaoto
2026-05-30 17:33 ` [PATCH v5 RESEND 3/5] dt-bindings: soc: sophgo: add sg2000 plic and clint documentation Joshua Milas
2026-05-30 17:33   ` Joshua Milas
2026-05-31 12:30   ` Krzysztof Kozlowski
2026-05-31 12:30     ` Krzysztof Kozlowski
2026-05-30 17:33 ` [PATCH v5 RESEND 4/5] riscv64: dts: sophgo: add SG2000 dtsi Joshua Milas
2026-05-30 17:33   ` Joshua Milas
2026-05-30 17:56   ` sashiko-bot
2026-06-05  9:33   ` Shuwei Wu
2026-06-05  9:33     ` Shuwei Wu
2026-06-08 12:06     ` Joshua Milas [this message]
2026-06-08 12:06       ` Joshua Milas
2026-05-30 17:33 ` [PATCH v5 RESEND 5/5] riscv64: dts: sophgo: add initial Milk-V Duo S board support Joshua Milas
2026-05-30 17:33   ` Joshua Milas
2026-05-30 18:02   ` sashiko-bot
2026-05-30 22:00   ` Inochi Amaoto
2026-05-30 22:00     ` Inochi Amaoto
2026-06-05  9:09   ` Shuwei Wu
2026-06-05  9:09     ` Shuwei Wu
2026-06-08 12:06     ` Joshua Milas
2026-06-08 12:06       ` Joshua Milas
2026-05-30 22:02 ` [PATCH v5 RESEND 0/5] Add " Inochi Amaoto
2026-05-30 22:02   ` Inochi Amaoto
2026-06-08 13:28   ` Joshua Milas
2026-06-08 13:28     ` Joshua Milas
2026-06-02  8:19 ` (subset) " Inochi Amaoto
2026-06-02  8:19   ` Inochi Amaoto
2026-06-02  8:22   ` Inochi Amaoto
2026-06-02  8:22     ` Inochi Amaoto
2026-06-02  8:26 ` Inochi Amaoto
2026-06-02  8:26   ` Inochi Amaoto

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