[LTP] [PATCH v14] high_freq_hwp_cap_cppc.c: new test

[LTP] [PATCH v14] high_freq_hwp_cap_cppc.c: new test

[Piotr Kubaj]

Verify for all online logical CPUs that their highest performance value are
the same for HWP Capability MSR 0x771 and CPPC sysfs file.

On HWP-capable x86 platforms the acpi_cppc/highest_perf sysfs attribute is
expected to reflect the same highest-performance value that firmware
programs into the HWP Capabilities MSR (0x771, bits 7:0). A mismatch
between the two interfaces indicates a kernel regression in how CPPC
values are exposed to userspace, and would break tools (e.g. cpupower,
intel_pstate tuning scripts) that rely on the sysfs interface to make
frequency-scaling decisions.

The test is valid only for Intel platforms.

Signed-off-by: Piotr Kubaj <piotr.kubaj@intel.com>
---
The new version checks the CPU vendor and only runs on Intel.
 runtest/power_management_tests                |   1 +
 testcases/kernel/power_management/.gitignore  |   1 +
 .../power_management/high_freq_hwp_cap_cppc.c | 133 ++++++++++++++++++
 3 files changed, 135 insertions(+)
 create mode 100644 testcases/kernel/power_management/.gitignore
 create mode 100644 testcases/kernel/power_management/high_freq_hwp_cap_cppc.c

diff --git a/runtest/power_management_tests b/runtest/power_management_tests
index b670da6ec..4da57ee72 100644
--- a/runtest/power_management_tests
+++ b/runtest/power_management_tests
@@ -1,4 +1,5 @@
 #POWER_MANAGEMENT
+high_freq_hwp_cap_cppc high_freq_hwp_cap_cppc
 runpwtests03 runpwtests03.sh
 runpwtests04 runpwtests04.sh
 runpwtests06 runpwtests06.sh
diff --git a/testcases/kernel/power_management/.gitignore b/testcases/kernel/power_management/.gitignore
new file mode 100644
index 000000000..03f0c83e4
--- /dev/null
+++ b/testcases/kernel/power_management/.gitignore
@@ -0,0 +1 @@
+high_freq_hwp_cap_cppc
diff --git a/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
new file mode 100644
index 000000000..107b8ceeb
--- /dev/null
+++ b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2026 Piotr Kubaj <piotr.kubaj@intel.com>
+ */
+
+/*\
+ * Verify for all online logical CPUs that their highest performance value are
+ * the same for HWP Capability MSR 0x771 and CPPC sysfs file.
+ *
+ * On HWP-capable x86 platforms the acpi_cppc/highest_perf sysfs attribute is
+ * expected to reflect the same highest-performance value that firmware
+ * programs into the HWP Capabilities MSR (0x771, bits 7:0). A mismatch
+ * between the two interfaces indicates a kernel regression in how CPPC
+ * values are exposed to userspace, and would break tools (e.g. cpupower,
+ * intel_pstate tuning scripts) that rely on the sysfs interface to make
+ * frequency-scaling decisions.
+ */
+
+#include "tst_test.h"
+#include "tst_safe_prw.h"
+#include "lapi/cpuid.h"
+
+#define MSR_HWP_CAPABILITIES	0x771
+#define HIGHEST_PERF_MASK	0xFF
+
+#define CPUID_VENDOR_EBX	0x756e6547
+#define CPUID_VENDOR_EDX	0x49656e69
+#define CPUID_VENDOR_ECX	0x6c65746e
+
+#define CPUID_LEAF_THERMAL	0x6
+#define CPUID_HWP_BIT		(1 << 7)
+
+static int nproc;
+static int fd = -1;
+static int *mismatch;
+
+static void setup(void)
+{
+	unsigned int eax, ebx, ecx, edx;
+
+	__cpuid_count(0, 0, eax, ebx, ecx, edx);
+	if (ebx != CPUID_VENDOR_EBX || edx != CPUID_VENDOR_EDX ||
+	    ecx != CPUID_VENDOR_ECX)
+		tst_brk(TCONF, "not a GenuineIntel CPU");
+
+	__cpuid_count(CPUID_LEAF_THERMAL, 0, eax, ebx, ecx, edx);
+	if (!(eax & CPUID_HWP_BIT))
+		tst_brk(TCONF, "HWP not supported (MSR 0x771 unavailable)");
+
+	if (access("/dev/cpu/0/msr", F_OK) == -1)
+		tst_brk(TCONF | TERRNO, "msr driver not loaded");
+
+	if (access("/sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf", F_OK) == -1)
+		tst_brk(TCONF | TERRNO, "CPPC sysfs not available");
+
+	nproc = tst_ncpus_conf();
+	mismatch = SAFE_MALLOC(nproc * sizeof(int));
+}
+
+static void cleanup(void)
+{
+	if (fd != -1)
+		SAFE_CLOSE(fd);
+
+	free(mismatch);
+}
+
+static void run(void)
+{
+	bool status = true;
+	char path[PATH_MAX];
+
+	memset(mismatch, 0, nproc * sizeof(*mismatch));
+
+	for (int i = 0; i < nproc; i++) {
+		int online = 1;
+		unsigned long long msr_highest_perf = 0, sysfs_highest_perf = 0;
+
+		if (i) {
+			snprintf(path, sizeof(path), "/sys/devices/system/cpu/cpu%d/online", i);
+			SAFE_FILE_SCANF(path, "%d", &online);
+		}
+
+		if (!online) {
+			tst_res(TINFO, "CPU%d offline, skipping", i);
+			continue;
+		}
+
+		snprintf(path, sizeof(path), "/sys/devices/system/cpu/cpu%d/acpi_cppc/highest_perf", i);
+		SAFE_FILE_SCANF(path, "%llu", &sysfs_highest_perf);
+		tst_res(TDEBUG, "%s: %llu", path, sysfs_highest_perf);
+
+		snprintf(path, sizeof(path), "/dev/cpu/%d/msr", i);
+		fd = SAFE_OPEN(path, O_RDONLY);
+
+		SAFE_PREAD(1, fd, &msr_highest_perf, sizeof(msr_highest_perf), MSR_HWP_CAPABILITIES);
+		SAFE_CLOSE(fd);
+		msr_highest_perf &= HIGHEST_PERF_MASK;
+		tst_res(TDEBUG, "%s: %llu", path, msr_highest_perf);
+
+		if (msr_highest_perf != sysfs_highest_perf) {
+			tst_res(TINFO, "cpu%d: sysfs=%llu MSR=%llu",
+				i, sysfs_highest_perf, msr_highest_perf);
+			mismatch[i] = 1;
+			status = false;
+		}
+	}
+
+	for (int i = 0; i < nproc; i++)
+		tst_res(TINFO, "cpu%d: %s", i, mismatch[i] ? "MISMATCH" : "OK");
+
+	if (status)
+		tst_res(TPASS, "Sysfs and MSR values are equal");
+	else
+		tst_res(TFAIL, "Highest performance values differ between sysfs and MSR");
+}
+
+static struct tst_test test = {
+	.needs_kconfigs = (const char *const []) {
+		"CONFIG_ACPI_CPPC_LIB",
+		"CONFIG_X86_MSR",
+		NULL
+	},
+	.needs_root = 1,
+	.setup = setup,
+	.cleanup = cleanup,
+	.supported_archs = (const char *const []) {
+		"x86",
+		"x86_64",
+		NULL
+	},
+	.test_all = run
+};
-- 
2.47.3

---------------------------------------------------------------------
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.
Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w transakcjach handlowych.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.


-- 
Mailing list info: https://lists.linux.it/listinfo/ltp

Re: [LTP] high_freq_hwp_cap_cppc.c: new test

[linuxtestproject.agent]

Hi Piotr,

On Tue, Jun 9 2026, Piotr Kubaj wrote:
> high_freq_hwp_cap_cppc.c: new test

> +#include "tst_test.h"
> +#include "tst_safe_prw.h"
> +#include "lapi/cpuid.h"

lapi/cpuid.h contains #error on non-x86 architectures and
__cpuid_count uses x86 inline assembly, so this file will not
compile on ARM, s390x, etc.

Ground rule 6 requires architecture-specific tests to still compile
everywhere. The existing ptrace07.c shows the correct pattern:
wrap the entire file body in
#if defined(__i386__) || defined(__x86_64__) with a
TST_TEST_TCONF("test requires x86") in the #else branch.

> +	for (int i = 0; i < nproc; i++)
> +		tst_res(TINFO, "cpu%d: %s", i, mismatch[i] ? "MISMATCH" : "OK");

Offline CPUs are skipped during the comparison loop but the
summary still prints "OK" for them (mismatch[i] is zero from
memset). This is misleading -- "OK" implies the values matched
when no check was performed. Consider skipping offline CPUs here
too, or printing "OFFLINE" instead.

> +/*\
> + * Verify for all online logical CPUs that their highest performance value are
> + * the same for HWP Capability MSR 0x771 and CPPC sysfs file.

The test sets .needs_root = 1 but the doc comment does not explain
why root is required. Per the LTP guidelines, the reason should be
stated (reading /dev/cpu/N/msr needs CAP_SYS_RAWIO / root).

Verdict: Needs revision

---
Note:

The agent can sometimes produce false positives although often its
findings are genuine. If you find issues with the review, please
comment this email or ignore the suggestions.

Regards,
LTP AI Reviewer

-- 
Mailing list info: https://lists.linux.it/listinfo/ltp

Re: [LTP] high_freq_hwp_cap_cppc.c: new test

[Cyril Hrubis]

Hi!
> On Tue, Jun 9 2026, Piotr Kubaj wrote:
> > high_freq_hwp_cap_cppc.c: new test
> 
> > +#include "tst_test.h"
> > +#include "tst_safe_prw.h"
> > +#include "lapi/cpuid.h"
> 
> lapi/cpuid.h contains #error on non-x86 architectures and
> __cpuid_count uses x86 inline assembly, so this file will not
> compile on ARM, s390x, etc.

I think that more generic solution is to add the functionality into the
test library. Let me draft a patch.

-- 
Cyril Hrubis
chrubis@suse.cz

-- 
Mailing list info: https://lists.linux.it/listinfo/ltp

Re: [LTP] [PATCH v14] high_freq_hwp_cap_cppc.c: new test

[Cyril Hrubis]

Hi!
> +static void setup(void)
> +{
> +	unsigned int eax, ebx, ecx, edx;
> +
> +	__cpuid_count(0, 0, eax, ebx, ecx, edx);
> +	if (ebx != CPUID_VENDOR_EBX || edx != CPUID_VENDOR_EDX ||
> +	    ecx != CPUID_VENDOR_ECX)
> +		tst_brk(TCONF, "not a GenuineIntel CPU");

I've send a patch for the tst_test structure that adds .needs_cpu_vendor
field. If that gets merged you can just set it to "GenuineIntel" and the
test should be automatically skipped on anything but Intel CPUs.

> +	__cpuid_count(CPUID_LEAF_THERMAL, 0, eax, ebx, ecx, edx);
> +	if (!(eax & CPUID_HWP_BIT))
> +		tst_brk(TCONF, "HWP not supported (MSR 0x771 unavailable)");

This specific check still needs to be ifdefed around with x86 and x86_64
macros.

-- 
Cyril Hrubis
chrubis@suse.cz

-- 
Mailing list info: https://lists.linux.it/listinfo/ltp

Re: [LTP] [PATCH v14] high_freq_hwp_cap_cppc.c: new test

[Andrea Cervesato via ltp]

Hi Piotr,

this patch is failing to build on Debian Stable (ppc64el, arm64, s390x):
https://patchwork.ozlabs.org/project/ltp/patch/20260609121840.61087-2-piotr.kubaj@intel.com/

Please fix the patch-set and send a new version.

Regards,
--
Andrea Cervesato
SUSE QE Automation Engineer Linux
andrea.cervesato@suse.com

-- 
Mailing list info: https://lists.linux.it/listinfo/ltp