[PATCH 00/14] drm/i915/cdclk: cdclk pcode related fixes and refactoring

[PATCH 00/14] drm/i915/cdclk: cdclk pcode related fixes and refactoring

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Fix up some bugs around the cdclk pcode notificatiosn on DG2,
follow up with some unification/cleanups, and finally convert
the pcode stuff (except on dg2, due to it doing weird things)
into vfuncs (goal being to make the code less messy).

Ville Syrjälä (14):
  drm/i915/cdclk: Don't bail if pcode post nofify fails
  drm/i915/cdclk: Pass CDCLK in MHz to pcode on DG2
  drm/i915/cdclk: Do the DG2 CDCLK/pipe power well notify properly
  drm/i915/cdclk: Notify DG2 pcode about pipe power wells regardless of
    CDCLK
  drm/i915/cdclk: Stop forcing voltage level to 3 all the time on DG2
  drm/i915/cdclk: Drop pointless platform check from bxt_set_cdclk()
  drm/i915/dg2: s/intel_/dg2_/ for DG2 specific stuff
  drm/i915/cdclk: Unify the pcode pre/post notify in bxt_set_cdclk()
  drm/i915/cdclk: Unify pcode related debugs
  drm/i915/cdclk: Extract bdw_cdclk_pcode_{pre,post}_notify()
  drm/i915/cdclk: Extract skl_cdclk_pcode_{pre,post}_notify()
  drm/i915/cdclk: Extract bxt_cdclk_pcode_{pre,post}_notify()
  drm/i915/cdclk: Introduce CDCLK .{pre,post}_notify() vfuncs
  drm/i915/cdclk: Hoist intel_cdclk_{pre,post}_notify() calls upwards

 drivers/gpu/drm/i915/display/intel_cdclk.c | 301 ++++++++++++---------
 1 file changed, 171 insertions(+), 130 deletions(-)

-- 
2.53.0

[PATCH 01/14] drm/i915/cdclk: Don't bail if pcode post nofify fails

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We already changed the actual cdclk frequency by the time we do
the pcode post notify. So skipping the subsequent readout is plain
wrong.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 189ae2d3cfc9..9ca56bab281f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2301,12 +2301,10 @@ static void bxt_set_cdclk(struct intel_display *display,
 						       HSW_PCODE_DE_WRITE_FREQ_REQ,
 						       cdclk_config->voltage_level, 2);
 	}
-	if (ret) {
+	if (ret)
 		drm_err(display->drm,
 			"PCode CDCLK freq set failed, (err %d, freq %d)\n",
 			ret, cdclk);
-		return;
-	}
 
 	intel_update_cdclk(display);
 
-- 
2.53.0

[PATCH 02/14] drm/i915/cdclk: Pass CDCLK in MHz to pcode on DG2

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We are currently trying to pass the CDCLK in kHz to the pcode
on DG2, while the pcode expects a value in MHz units. Adjust
the units appropriately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9ca56bab281f..9718062d8d6c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2703,8 +2703,10 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
 	 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK,
 	 * which basically means we choose the maximum of old and new CDCLK, if we know both
 	 */
-	if (change_cdclk)
+	if (change_cdclk) {
 		cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
+		cdclk = DIV_ROUND_UP(cdclk, 1000);
+	}
 
 	/*
 	 * According to "Sequence For Pipe Count Change",
@@ -2740,8 +2742,10 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
 	 * According to "Sequence After Frequency Change",
 	 * set bits 25:16 to current CDCLK
 	 */
-	if (update_cdclk)
+	if (update_cdclk) {
 		cdclk = new_cdclk_state->actual.cdclk;
+		cdclk = DIV_ROUND_UP(cdclk, 1000);
+	}
 
 	/*
 	 * According to "Sequence For Pipe Count Change",
-- 
2.53.0

[PATCH 03/14] drm/i915/cdclk: Do the DG2 CDCLK/pipe power well notify properly

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The pcode post notufy needs to happen after the CDCLK has been
changed, not before. Also move the pre_notify call a bit for the
sake of symmetry.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9718062d8d6c..d60b3369b4d2 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2796,9 +2796,6 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 				 &new_cdclk_state->actual))
 		return;
 
-	if (display->platform.dg2)
-		intel_cdclk_pcode_pre_notify(state);
-
 	if (new_cdclk_state->disable_pipes) {
 		cdclk_config = new_cdclk_state->actual;
 		pipe = INVALID_PIPE;
@@ -2823,6 +2820,9 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 
 	drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
 
+	if (display->platform.dg2)
+		intel_cdclk_pcode_pre_notify(state);
+
 	intel_set_cdclk(display, &cdclk_config, pipe,
 			"Pre changing CDCLK to");
 }
@@ -2851,9 +2851,6 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 				 &new_cdclk_state->actual))
 		return;
 
-	if (display->platform.dg2)
-		intel_cdclk_pcode_post_notify(state);
-
 	if (!new_cdclk_state->disable_pipes &&
 	    new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)
 		pipe = new_cdclk_state->pipe;
@@ -2864,6 +2861,9 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 
 	intel_set_cdclk(display, &new_cdclk_state->actual, pipe,
 			"Post changing CDCLK to");
+
+	if (display->platform.dg2)
+		intel_cdclk_pcode_post_notify(state);
 }
 
 /* pixels per CDCLK */
-- 
2.53.0

[PATCH 04/14] drm/i915/cdclk: Notify DG2 pcode about pipe power wells regardless of CDCLK

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We're currently skipping the pcode notifies on DG2 if the CDCLK isn't
changing while the power well counts would still need updating.
Do the pcode notifications also for pure pipe power well changes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d60b3369b4d2..7259048361a7 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2793,7 +2793,9 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 		return;
 
 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
-				 &new_cdclk_state->actual))
+				 &new_cdclk_state->actual) &&
+	    dg2_power_well_count(display, old_cdclk_state) ==
+	    dg2_power_well_count(display, new_cdclk_state))
 		return;
 
 	if (new_cdclk_state->disable_pipes) {
@@ -2848,7 +2850,9 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 		return;
 
 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
-				 &new_cdclk_state->actual))
+				 &new_cdclk_state->actual) &&
+	    dg2_power_well_count(display, old_cdclk_state) ==
+	    dg2_power_well_count(display, new_cdclk_state))
 		return;
 
 	if (!new_cdclk_state->disable_pipes &&
-- 
2.53.0

[PATCH 05/14] drm/i915/cdclk: Stop forcing voltage level to 3 all the time on DG2

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

SKL_CDCLK_PREPARE_FOR_CHANGE == DISPLAY_TO_PCODE_VOLTAGE(3) so
we are currently forcing the voltage level to 3 all the time on
DG2. Remove SKL_CDCLK_PREPARE_FOR_CHANGE from the mask to avoid
this.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 7259048361a7..ecb6be3383ca 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2598,7 +2598,6 @@ static void intel_pcode_notify(struct intel_display *display,
 		update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
 
 	ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
-					 SKL_CDCLK_PREPARE_FOR_CHANGE |
 					 update_mask,
 					 SKL_CDCLK_READY_FOR_CHANGE,
 					 SKL_CDCLK_READY_FOR_CHANGE, 3);
-- 
2.53.0

[PATCH 06/14] drm/i915/cdclk: Drop pointless platform check from bxt_set_cdclk()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Overwrite cdclk.hw.voltage_level from intel_update_cdclk() at the
end on bxt_set_cdclk() also on bxt/glk. While this isn't actually
necessary due to bxt/glk not having any extra DDI based voltage
level requirements, it does avoid one less silly 'if' in the code.

On icl+ the value derived by bxt_get_cdclk() may not be correct
if the voltage level was bumped up due to DDI requirements, thus
overwriting the assumed value is crucial there.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ecb6be3383ca..bbf3603f889b 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2308,12 +2308,11 @@ static void bxt_set_cdclk(struct intel_display *display,
 
 	intel_update_cdclk(display);
 
-	if (DISPLAY_VER(display) >= 11)
-		/*
-		 * Can't read out the voltage level :(
-		 * Let's just assume everything is as expected.
-		 */
-		display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
+	/*
+	 * Can't read out the voltage level :(
+	 * Let's just assume everything is as expected.
+	 */
+	display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
 }
 
 static void bxt_sanitize_cdclk(struct intel_display *display)
-- 
2.53.0

[PATCH 07/14] drm/i915/dg2: s/intel_/dg2_/ for DG2 specific stuff

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_pcode_*notify() are all DG2 specific code. Rename them
to have a dg2_ namespace.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 31 ++++++++++------------
 1 file changed, 14 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index bbf3603f889b..659c1c0e3432 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2575,19 +2575,16 @@ void intel_cdclk_dump_config(struct intel_display *display,
 		    cdclk_config->voltage_level);
 }
 
-static void intel_pcode_notify(struct intel_display *display,
-			       u8 voltage_level,
-			       u8 active_pipe_count,
-			       u16 cdclk,
-			       bool cdclk_update_valid,
-			       bool pipe_count_update_valid)
+static void dg2_cdclk_pcode_notify(struct intel_display *display,
+				   u8 voltage_level,
+				   u8 active_pipe_count,
+				   u16 cdclk,
+				   bool cdclk_update_valid,
+				   bool pipe_count_update_valid)
 {
 	int ret;
 	u32 update_mask = 0;
 
-	if (!display->platform.dg2)
-		return;
-
 	update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
 
 	if (cdclk_update_valid)
@@ -2672,7 +2669,7 @@ static bool dg2_power_well_count(struct intel_display *display,
 	return display->platform.dg2 ? hweight8(cdclk_state->active_pipes) : 0;
 }
 
-static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
+static void dg2_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
 {
 	struct intel_display *display = to_intel_display(state);
 	const struct intel_cdclk_state *old_cdclk_state =
@@ -2715,11 +2712,11 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
 	if (update_pipe_count)
 		num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
 
-	intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
-			   change_cdclk, update_pipe_count);
+	dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
+			       change_cdclk, update_pipe_count);
 }
 
-static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
+static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state)
 {
 	struct intel_display *display = to_intel_display(state);
 	const struct intel_cdclk_state *new_cdclk_state =
@@ -2754,8 +2751,8 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
 	if (update_pipe_count)
 		num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
 
-	intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
-			   update_cdclk, update_pipe_count);
+	dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
+			       update_cdclk, update_pipe_count);
 }
 
 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
@@ -2821,7 +2818,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 	drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
 
 	if (display->platform.dg2)
-		intel_cdclk_pcode_pre_notify(state);
+		dg2_cdclk_pcode_pre_notify(state);
 
 	intel_set_cdclk(display, &cdclk_config, pipe,
 			"Pre changing CDCLK to");
@@ -2865,7 +2862,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 			"Post changing CDCLK to");
 
 	if (display->platform.dg2)
-		intel_cdclk_pcode_post_notify(state);
+		dg2_cdclk_pcode_post_notify(state);
 }
 
 /* pixels per CDCLK */
-- 
2.53.0

[PATCH 08/14] drm/i915/cdclk: Unify the pcode pre/post notify in bxt_set_cdclk()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The control flow between the pcode pre and post notifications ibn
bxt_set_cdclk() is written in two different ways, even though
they end up doing the same thing. Unify the code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 659c1c0e3432..09981a112db4 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2237,7 +2237,7 @@ static void bxt_set_cdclk(struct intel_display *display,
 {
 	struct intel_cdclk_config mid_cdclk_config;
 	int cdclk = cdclk_config->cdclk;
-	int ret = 0;
+	int ret;
 
 	/*
 	 * Inform power controller of upcoming frequency change.
@@ -2246,7 +2246,7 @@ static void bxt_set_cdclk(struct intel_display *display,
 	 * this step.
 	 */
 	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
-		; /* NOOP */
+		ret = 0; /* NOOP */
 	else if (DISPLAY_VER(display) >= 11)
 		ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
 						 SKL_CDCLK_PREPARE_FOR_CHANGE,
@@ -2282,15 +2282,12 @@ static void bxt_set_cdclk(struct intel_display *display,
 	if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
 		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
 
-	if (DISPLAY_VER(display) >= 14)
-		/*
-		 * NOOP - No Pcode communication needed for
-		 * Display versions 14 and beyond
-		 */;
-	else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)
+	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
+		ret = 0; /* NOOP */
+	else if (DISPLAY_VER(display) >= 11)
 		ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
 					       cdclk_config->voltage_level);
-	if (DISPLAY_VER(display) < 11) {
+	else
 		/*
 		 * The timeout isn't specified, the 2ms used here is based on
 		 * experiment.
@@ -2300,7 +2297,6 @@ static void bxt_set_cdclk(struct intel_display *display,
 		ret = intel_parent_pcode_write_timeout(display,
 						       HSW_PCODE_DE_WRITE_FREQ_REQ,
 						       cdclk_config->voltage_level, 2);
-	}
 	if (ret)
 		drm_err(display->drm,
 			"PCode CDCLK freq set failed, (err %d, freq %d)\n",
-- 
2.53.0

[PATCH 09/14] drm/i915/cdclk: Unify pcode related debugs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The debug spew for the cdclk pcode per/post notify is very
inconsistent between different platforms. Unify it all to
the same form.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 65 ++++++++++++----------
 1 file changed, 36 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 09981a112db4..542724256d0f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -891,7 +891,7 @@ static void bdw_set_cdclk(struct intel_display *display,
 	ret = intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 	if (ret) {
 		drm_err(display->drm,
-			"failed to inform pcode about cdclk change\n");
+			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
 		return;
 	}
 
@@ -918,8 +918,11 @@ static void bdw_set_cdclk(struct intel_display *display,
 	if (ret)
 		drm_err(display->drm, "Switching back to LCPLL failed\n");
 
-	intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
-				 cdclk_config->voltage_level);
+	ret = intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
+				       cdclk_config->voltage_level);
+	if (ret)
+		drm_err(display->drm,
+			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
 
 	intel_de_write(display, CDCLK_FREQ,
 		       DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
@@ -1181,7 +1184,7 @@ static void skl_set_cdclk(struct intel_display *display,
 					 SKL_CDCLK_READY_FOR_CHANGE, 3);
 	if (ret) {
 		drm_err(display->drm,
-			"Failed to inform PCU about cdclk change (%d)\n", ret);
+			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
 		return;
 	}
 
@@ -1221,8 +1224,11 @@ static void skl_set_cdclk(struct intel_display *display,
 	intel_de_posting_read(display, CDCLK_CTL);
 
 	/* inform PCU of the change */
-	intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
-				 cdclk_config->voltage_level);
+	ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
+				       cdclk_config->voltage_level);
+	if (ret)
+		drm_err(display->drm,
+			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
 
 	intel_update_cdclk(display);
 }
@@ -2263,8 +2269,7 @@ static void bxt_set_cdclk(struct intel_display *display,
 
 	if (ret) {
 		drm_err(display->drm,
-			"Failed to inform PCU about cdclk change (err %d, freq %d)\n",
-			ret, cdclk);
+			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
 		return;
 	}
 
@@ -2299,8 +2304,7 @@ static void bxt_set_cdclk(struct intel_display *display,
 						       cdclk_config->voltage_level, 2);
 	if (ret)
 		drm_err(display->drm,
-			"PCode CDCLK freq set failed, (err %d, freq %d)\n",
-			ret, cdclk);
+			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
 
 	intel_update_cdclk(display);
 
@@ -2571,14 +2575,13 @@ void intel_cdclk_dump_config(struct intel_display *display,
 		    cdclk_config->voltage_level);
 }
 
-static void dg2_cdclk_pcode_notify(struct intel_display *display,
-				   u8 voltage_level,
-				   u8 active_pipe_count,
-				   u16 cdclk,
-				   bool cdclk_update_valid,
-				   bool pipe_count_update_valid)
+static int dg2_cdclk_pcode_notify(struct intel_display *display,
+				  u8 voltage_level,
+				  u8 active_pipe_count,
+				  u16 cdclk,
+				  bool cdclk_update_valid,
+				  bool pipe_count_update_valid)
 {
-	int ret;
 	u32 update_mask = 0;
 
 	update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
@@ -2589,14 +2592,10 @@ static void dg2_cdclk_pcode_notify(struct intel_display *display,
 	if (pipe_count_update_valid)
 		update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
 
-	ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
-					 update_mask,
-					 SKL_CDCLK_READY_FOR_CHANGE,
-					 SKL_CDCLK_READY_FOR_CHANGE, 3);
-	if (ret)
-		drm_err(display->drm,
-			"Failed to inform PCU about display config (err %d)\n",
-			ret);
+	return intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
+					  update_mask,
+					  SKL_CDCLK_READY_FOR_CHANGE,
+					  SKL_CDCLK_READY_FOR_CHANGE, 3);
 }
 
 static void intel_set_cdclk(struct intel_display *display,
@@ -2674,6 +2673,7 @@ static void dg2_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
 		intel_atomic_get_new_cdclk_state(state);
 	unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
 	bool change_cdclk, update_pipe_count;
+	int ret;
 
 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
 				 &new_cdclk_state->actual) &&
@@ -2708,8 +2708,11 @@ static void dg2_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
 	if (update_pipe_count)
 		num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
 
-	dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
-			       change_cdclk, update_pipe_count);
+	ret = dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
+				     change_cdclk, update_pipe_count);
+	if (ret)
+		drm_err(display->drm,
+			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
 }
 
 static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state)
@@ -2721,6 +2724,7 @@ static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state)
 		intel_atomic_get_old_cdclk_state(state);
 	unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
 	bool update_cdclk, update_pipe_count;
+	int ret;
 
 	/* According to "Sequence After Frequency Change", set voltage to used level */
 	voltage_level = new_cdclk_state->actual.voltage_level;
@@ -2747,8 +2751,11 @@ static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state)
 	if (update_pipe_count)
 		num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
 
-	dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
-			       update_cdclk, update_pipe_count);
+	ret = dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
+				     update_cdclk, update_pipe_count);
+	if (ret)
+		drm_err(display->drm,
+			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
 }
 
 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
-- 
2.53.0

[PATCH 10/14] drm/i915/cdclk: Extract bdw_cdclk_pcode_{pre, post}_notify()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the BSW pcode notify stuff to a few small helpers. The
plan is to unify these between all the platforms and turn them
into vfuncs.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 542724256d0f..041b1fc8b3ee 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -872,6 +872,19 @@ static u32 bdw_cdclk_freq_sel(int cdclk)
 	}
 }
 
+static int bdw_cdclk_pcode_pre_notify(struct intel_display *display)
+{
+	return intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ,
+					0x0);
+}
+
+static int bdw_cdclk_pcode_post_notify(struct intel_display *display,
+				       const struct intel_cdclk_config *cdclk_config)
+{
+	return intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
+					cdclk_config->voltage_level);
+}
+
 static void bdw_set_cdclk(struct intel_display *display,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe)
@@ -888,7 +901,7 @@ static void bdw_set_cdclk(struct intel_display *display,
 		     "trying to change cdclk frequency with cdclk not enabled\n"))
 		return;
 
-	ret = intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
+	ret = bdw_cdclk_pcode_pre_notify(display);
 	if (ret) {
 		drm_err(display->drm,
 			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
@@ -918,8 +931,7 @@ static void bdw_set_cdclk(struct intel_display *display,
 	if (ret)
 		drm_err(display->drm, "Switching back to LCPLL failed\n");
 
-	ret = intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
-				       cdclk_config->voltage_level);
+	ret = bdw_cdclk_pcode_post_notify(display, cdclk_config);
 	if (ret)
 		drm_err(display->drm,
 			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
-- 
2.53.0

[PATCH 11/14] drm/i915/cdclk: Extract skl_cdclk_pcode_{pre, post}_notify()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the SKL/ICL+ pcode notify stuff to a few small helpers.
The plan is to unify these between all the platforms and turn
them into vfuncs.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 32 +++++++++++++---------
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 041b1fc8b3ee..bb47fc4c86ee 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1170,6 +1170,21 @@ static u32 skl_cdclk_freq_sel(struct intel_display *display,
 	}
 }
 
+static int skl_cdclk_pcode_pre_notify(struct intel_display *display)
+{
+	return intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
+					  SKL_CDCLK_PREPARE_FOR_CHANGE,
+					  SKL_CDCLK_READY_FOR_CHANGE,
+					  SKL_CDCLK_READY_FOR_CHANGE, 3);
+}
+
+static int skl_cdclk_pcode_post_notify(struct intel_display *display,
+				       const struct intel_cdclk_config *cdclk_config)
+{
+	return intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
+					cdclk_config->voltage_level);
+}
+
 static void skl_set_cdclk(struct intel_display *display,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe)
@@ -1190,10 +1205,7 @@ static void skl_set_cdclk(struct intel_display *display,
 	drm_WARN_ON_ONCE(display->drm,
 			 display->platform.skylake && vco == 8640000);
 
-	ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
-					 SKL_CDCLK_PREPARE_FOR_CHANGE,
-					 SKL_CDCLK_READY_FOR_CHANGE,
-					 SKL_CDCLK_READY_FOR_CHANGE, 3);
+	ret = skl_cdclk_pcode_pre_notify(display);
 	if (ret) {
 		drm_err(display->drm,
 			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
@@ -1235,9 +1247,7 @@ static void skl_set_cdclk(struct intel_display *display,
 	intel_de_write(display, CDCLK_CTL, cdclk_ctl);
 	intel_de_posting_read(display, CDCLK_CTL);
 
-	/* inform PCU of the change */
-	ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
-				       cdclk_config->voltage_level);
+	ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
 	if (ret)
 		drm_err(display->drm,
 			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
@@ -2266,10 +2276,7 @@ static void bxt_set_cdclk(struct intel_display *display,
 	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
 		ret = 0; /* NOOP */
 	else if (DISPLAY_VER(display) >= 11)
-		ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
-						 SKL_CDCLK_PREPARE_FOR_CHANGE,
-						 SKL_CDCLK_READY_FOR_CHANGE,
-						 SKL_CDCLK_READY_FOR_CHANGE, 3);
+		ret = skl_cdclk_pcode_pre_notify(display);
 	else
 		/*
 		 * BSpec requires us to wait up to 150usec, but that leads to
@@ -2302,8 +2309,7 @@ static void bxt_set_cdclk(struct intel_display *display,
 	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
 		ret = 0; /* NOOP */
 	else if (DISPLAY_VER(display) >= 11)
-		ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
-					       cdclk_config->voltage_level);
+		ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
 	else
 		/*
 		 * The timeout isn't specified, the 2ms used here is based on
-- 
2.53.0

[PATCH 12/14] drm/i915/cdclk: Extract bxt_cdclk_pcode_{pre, post}_notify()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the BXT/GLK pcode notify stuff to a few small helpers.
The plan is to unify these between all the platforms and turn
them into vfuncs.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 42 +++++++++++++---------
 1 file changed, 26 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index bb47fc4c86ee..749e366e60ab 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2226,6 +2226,29 @@ static u32 bxt_cdclk_ctl(struct intel_display *display,
 	return val;
 }
 
+static int bxt_cdclk_pcode_pre_notify(struct intel_display *display)
+{
+	/*
+	 * BSpec requires us to wait up to 150usec, but that leads to
+	 * timeouts; the 2ms used here is based on experiment.
+	 */
+	return intel_parent_pcode_write_timeout(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
+						0x80000000, 2);
+}
+
+static int bxt_cdclk_pcode_post_notify(struct intel_display *display,
+				       const struct intel_cdclk_config *cdclk_config)
+{
+	/*
+	 * The timeout isn't specified, the 2ms used here is based on
+	 * experiment.
+	 * FIXME: Waiting for the request completion could be delayed
+	 * until the next PCODE request based on BSpec.
+	 */
+	return intel_parent_pcode_write_timeout(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
+						cdclk_config->voltage_level, 2);
+}
+
 static void _bxt_set_cdclk(struct intel_display *display,
 			   const struct intel_cdclk_config *cdclk_config,
 			   enum pipe pipe)
@@ -2278,13 +2301,7 @@ static void bxt_set_cdclk(struct intel_display *display,
 	else if (DISPLAY_VER(display) >= 11)
 		ret = skl_cdclk_pcode_pre_notify(display);
 	else
-		/*
-		 * BSpec requires us to wait up to 150usec, but that leads to
-		 * timeouts; the 2ms used here is based on experiment.
-		 */
-		ret = intel_parent_pcode_write_timeout(display,
-						       HSW_PCODE_DE_WRITE_FREQ_REQ,
-						       0x80000000, 2);
+		ret = bxt_cdclk_pcode_pre_notify(display);
 
 	if (ret) {
 		drm_err(display->drm,
@@ -2311,15 +2328,8 @@ static void bxt_set_cdclk(struct intel_display *display,
 	else if (DISPLAY_VER(display) >= 11)
 		ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
 	else
-		/*
-		 * The timeout isn't specified, the 2ms used here is based on
-		 * experiment.
-		 * FIXME: Waiting for the request completion could be delayed
-		 * until the next PCODE request based on BSpec.
-		 */
-		ret = intel_parent_pcode_write_timeout(display,
-						       HSW_PCODE_DE_WRITE_FREQ_REQ,
-						       cdclk_config->voltage_level, 2);
+		ret = bxt_cdclk_pcode_post_notify(display, cdclk_config);
+
 	if (ret)
 		drm_err(display->drm,
 			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
-- 
2.53.0

[PATCH 13/14] drm/i915/cdclk: Introduce CDCLK .{pre, post}_notify() vfuncs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Turn the cdclk pcode pre/post notify functiosn into vfuncs.
Mainly to get rid of the hideous if-ladders in bxt_set_cdclk().

DG2 is currently doing its own thing with its pcode notify funcs so
can't be converted yet. And MTL+ go via the pmdemand stuff so this
is all supposedly handled elsewhere.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 122 ++++++++++++---------
 1 file changed, 73 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 749e366e60ab..4154b4888eff 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -163,6 +163,9 @@ struct intel_cdclk_funcs {
 	void (*set_cdclk)(struct intel_display *display,
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe);
+	int (*pre_notify)(struct intel_display *display);
+	int (*post_notify)(struct intel_display *display,
+			   const struct intel_cdclk_config *cdclk_config);
 	int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
 	u8 (*calc_voltage_level)(int cdclk);
 };
@@ -173,6 +176,35 @@ void intel_cdclk_get_cdclk(struct intel_display *display,
 	display->cdclk.funcs->get_cdclk(display, cdclk_config);
 }
 
+static int intel_cdclk_pre_notify(struct intel_display *display)
+{
+	int ret;
+
+	if (!display->cdclk.funcs->pre_notify)
+		return 0;
+
+	ret = display->cdclk.funcs->pre_notify(display);
+	if (ret)
+		drm_err(display->drm,
+			"Failed to inform system about start of CDCLK change (%d)\n", ret);
+
+	return ret;
+}
+
+static void intel_cdclk_post_notify(struct intel_display *display,
+				    const struct intel_cdclk_config *cdclk_config)
+{
+	int ret;
+
+	if (!display->cdclk.funcs->post_notify)
+		return;
+
+	ret = display->cdclk.funcs->post_notify(display, cdclk_config);
+	if (ret)
+		drm_err(display->drm,
+			"Failed to inform system about end of CDCLK change (%d)\n", ret);
+}
+
 static void intel_cdclk_set_cdclk(struct intel_display *display,
 				  const struct intel_cdclk_config *cdclk_config,
 				  enum pipe pipe)
@@ -901,12 +933,9 @@ static void bdw_set_cdclk(struct intel_display *display,
 		     "trying to change cdclk frequency with cdclk not enabled\n"))
 		return;
 
-	ret = bdw_cdclk_pcode_pre_notify(display);
-	if (ret) {
-		drm_err(display->drm,
-			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
+	ret = intel_cdclk_pre_notify(display);
+	if (ret)
 		return;
-	}
 
 	intel_de_rmw(display, LCPLL_CTL,
 		     0, LCPLL_CD_SOURCE_FCLK);
@@ -931,10 +960,7 @@ static void bdw_set_cdclk(struct intel_display *display,
 	if (ret)
 		drm_err(display->drm, "Switching back to LCPLL failed\n");
 
-	ret = bdw_cdclk_pcode_post_notify(display, cdclk_config);
-	if (ret)
-		drm_err(display->drm,
-			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
+	intel_cdclk_post_notify(display, cdclk_config);
 
 	intel_de_write(display, CDCLK_FREQ,
 		       DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
@@ -1205,12 +1231,9 @@ static void skl_set_cdclk(struct intel_display *display,
 	drm_WARN_ON_ONCE(display->drm,
 			 display->platform.skylake && vco == 8640000);
 
-	ret = skl_cdclk_pcode_pre_notify(display);
-	if (ret) {
-		drm_err(display->drm,
-			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
+	ret = intel_cdclk_pre_notify(display);
+	if (ret)
 		return;
-	}
 
 	freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
 
@@ -1247,10 +1270,7 @@ static void skl_set_cdclk(struct intel_display *display,
 	intel_de_write(display, CDCLK_CTL, cdclk_ctl);
 	intel_de_posting_read(display, CDCLK_CTL);
 
-	ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
-	if (ret)
-		drm_err(display->drm,
-			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
+	intel_cdclk_post_notify(display, cdclk_config);
 
 	intel_update_cdclk(display);
 }
@@ -2290,24 +2310,9 @@ static void bxt_set_cdclk(struct intel_display *display,
 	int cdclk = cdclk_config->cdclk;
 	int ret;
 
-	/*
-	 * Inform power controller of upcoming frequency change.
-	 * Display versions 14 and beyond do not follow the PUnit
-	 * mailbox communication, skip
-	 * this step.
-	 */
-	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
-		ret = 0; /* NOOP */
-	else if (DISPLAY_VER(display) >= 11)
-		ret = skl_cdclk_pcode_pre_notify(display);
-	else
-		ret = bxt_cdclk_pcode_pre_notify(display);
-
-	if (ret) {
-		drm_err(display->drm,
-			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
+	ret = intel_cdclk_pre_notify(display);
+	if (ret)
 		return;
-	}
 
 	if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)
 		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
@@ -2323,16 +2328,7 @@ static void bxt_set_cdclk(struct intel_display *display,
 	if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
 		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
 
-	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
-		ret = 0; /* NOOP */
-	else if (DISPLAY_VER(display) >= 11)
-		ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
-	else
-		ret = bxt_cdclk_pcode_post_notify(display, cdclk_config);
-
-	if (ret)
-		drm_err(display->drm,
-			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
+	intel_cdclk_post_notify(display, cdclk_config);
 
 	intel_update_cdclk(display);
 
@@ -3929,9 +3925,25 @@ static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = {
 	.calc_voltage_level = xe3lpd_calc_voltage_level,
 };
 
+static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
+	.get_cdclk = bxt_get_cdclk,
+	.set_cdclk = bxt_set_cdclk,
+	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+	.calc_voltage_level = rplu_calc_voltage_level,
+};
+
+static const struct intel_cdclk_funcs dg2_cdclk_funcs = {
+	.get_cdclk = bxt_get_cdclk,
+	.set_cdclk = bxt_set_cdclk,
+	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+	.calc_voltage_level = tgl_calc_voltage_level,
+};
+
 static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
 	.get_cdclk = bxt_get_cdclk,
 	.set_cdclk = bxt_set_cdclk,
+	.pre_notify = skl_cdclk_pcode_pre_notify,
+	.post_notify = skl_cdclk_pcode_post_notify,
 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
 	.calc_voltage_level = rplu_calc_voltage_level,
 };
@@ -3939,6 +3951,8 @@ static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
 static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
 	.get_cdclk = bxt_get_cdclk,
 	.set_cdclk = bxt_set_cdclk,
+	.pre_notify = skl_cdclk_pcode_pre_notify,
+	.post_notify = skl_cdclk_pcode_post_notify,
 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
 	.calc_voltage_level = tgl_calc_voltage_level,
 };
@@ -3946,6 +3960,8 @@ static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
 static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
 	.get_cdclk = bxt_get_cdclk,
 	.set_cdclk = bxt_set_cdclk,
+	.pre_notify = skl_cdclk_pcode_pre_notify,
+	.post_notify = skl_cdclk_pcode_post_notify,
 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
 	.calc_voltage_level = ehl_calc_voltage_level,
 };
@@ -3953,6 +3969,8 @@ static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
 static const struct intel_cdclk_funcs icl_cdclk_funcs = {
 	.get_cdclk = bxt_get_cdclk,
 	.set_cdclk = bxt_set_cdclk,
+	.pre_notify = skl_cdclk_pcode_pre_notify,
+	.post_notify = skl_cdclk_pcode_post_notify,
 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
 	.calc_voltage_level = icl_calc_voltage_level,
 };
@@ -3960,6 +3978,8 @@ static const struct intel_cdclk_funcs icl_cdclk_funcs = {
 static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
 	.get_cdclk = bxt_get_cdclk,
 	.set_cdclk = bxt_set_cdclk,
+	.pre_notify = bxt_cdclk_pcode_pre_notify,
+	.post_notify = bxt_cdclk_pcode_post_notify,
 	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
 	.calc_voltage_level = bxt_calc_voltage_level,
 };
@@ -3967,12 +3987,16 @@ static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
 static const struct intel_cdclk_funcs skl_cdclk_funcs = {
 	.get_cdclk = skl_get_cdclk,
 	.set_cdclk = skl_set_cdclk,
+	.pre_notify = skl_cdclk_pcode_pre_notify,
+	.post_notify = skl_cdclk_pcode_post_notify,
 	.modeset_calc_cdclk = skl_modeset_calc_cdclk,
 };
 
 static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
 	.get_cdclk = bdw_get_cdclk,
 	.set_cdclk = bdw_set_cdclk,
+	.pre_notify = bdw_cdclk_pcode_pre_notify,
+	.post_notify = bdw_cdclk_pcode_post_notify,
 	.modeset_calc_cdclk = bdw_modeset_calc_cdclk,
 };
 
@@ -4078,16 +4102,16 @@ void intel_init_cdclk_hooks(struct intel_display *display)
 		display->cdclk.funcs = &xe3lpd_cdclk_funcs;
 		display->cdclk.table = xe3lpd_cdclk_table;
 	} else if (DISPLAY_VER(display) >= 20) {
-		display->cdclk.funcs = &rplu_cdclk_funcs;
+		display->cdclk.funcs = &mtl_cdclk_funcs;
 		display->cdclk.table = xe2lpd_cdclk_table;
 	} else if (DISPLAY_VERx100(display) >= 1401) {
-		display->cdclk.funcs = &rplu_cdclk_funcs;
+		display->cdclk.funcs = &mtl_cdclk_funcs;
 		display->cdclk.table = xe2hpd_cdclk_table;
 	} else if (DISPLAY_VER(display) >= 14) {
-		display->cdclk.funcs = &rplu_cdclk_funcs;
+		display->cdclk.funcs = &mtl_cdclk_funcs;
 		display->cdclk.table = mtl_cdclk_table;
 	} else if (display->platform.dg2) {
-		display->cdclk.funcs = &tgl_cdclk_funcs;
+		display->cdclk.funcs = &dg2_cdclk_funcs;
 		display->cdclk.table = dg2_cdclk_table;
 	} else if (display->platform.alderlake_p) {
 		/* Wa_22011320316:adl-p[a0] */
-- 
2.53.0

[PATCH 14/14] drm/i915/cdclk: Hoist intel_cdclk_{pre, post}_notify() calls upwards

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that intel_cdclk_{pre,post}_notify() are implemented via vfuncs
there is no need to keep them inside the .set_cdclk() hooks. Move
the calls one level up to intel_cdclk_set_cdclk().

We do need to adjust {skl,bxt}_cdclk_(un)init_hw() to call the wrapper
rather than the low level implementation directly, or else they would
not do the pcode notification anymore.

The two slight functions changes here are:
- bdw_set_cdclk() might theoretically bail out after doing the
  pre notification, but that codepath would only come into play
  if the hardware is seriously misprogrammed, so should never happen
- cdclk hw readout is still done from .set_cdclk(), so that now
  happens before the post notify vs. previously the readout happened
  before it. This should not matter as the readout is not affected
  by the post notify (since we can't actually read out anything from
  pcode).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 33 ++++++----------------
 1 file changed, 9 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4154b4888eff..617ad154505c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -209,7 +209,12 @@ static void intel_cdclk_set_cdclk(struct intel_display *display,
 				  const struct intel_cdclk_config *cdclk_config,
 				  enum pipe pipe)
 {
+	if (intel_cdclk_pre_notify(display))
+		return;
+
 	display->cdclk.funcs->set_cdclk(display, cdclk_config, pipe);
+
+	intel_cdclk_post_notify(display, cdclk_config);
 }
 
 static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state)
@@ -933,10 +938,6 @@ static void bdw_set_cdclk(struct intel_display *display,
 		     "trying to change cdclk frequency with cdclk not enabled\n"))
 		return;
 
-	ret = intel_cdclk_pre_notify(display);
-	if (ret)
-		return;
-
 	intel_de_rmw(display, LCPLL_CTL,
 		     0, LCPLL_CD_SOURCE_FCLK);
 
@@ -960,8 +961,6 @@ static void bdw_set_cdclk(struct intel_display *display,
 	if (ret)
 		drm_err(display->drm, "Switching back to LCPLL failed\n");
 
-	intel_cdclk_post_notify(display, cdclk_config);
-
 	intel_de_write(display, CDCLK_FREQ,
 		       DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 
@@ -1218,7 +1217,6 @@ static void skl_set_cdclk(struct intel_display *display,
 	int cdclk = cdclk_config->cdclk;
 	int vco = cdclk_config->vco;
 	u32 freq_select, cdclk_ctl;
-	int ret;
 
 	/*
 	 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
@@ -1231,10 +1229,6 @@ static void skl_set_cdclk(struct intel_display *display,
 	drm_WARN_ON_ONCE(display->drm,
 			 display->platform.skylake && vco == 8640000);
 
-	ret = intel_cdclk_pre_notify(display);
-	if (ret)
-		return;
-
 	freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
 
 	if (display->cdclk.hw.vco != 0 &&
@@ -1270,8 +1264,6 @@ static void skl_set_cdclk(struct intel_display *display,
 	intel_de_write(display, CDCLK_CTL, cdclk_ctl);
 	intel_de_posting_read(display, CDCLK_CTL);
 
-	intel_cdclk_post_notify(display, cdclk_config);
-
 	intel_update_cdclk(display);
 }
 
@@ -1343,7 +1335,7 @@ static void skl_cdclk_init_hw(struct intel_display *display)
 	cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
 	cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
 
-	skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
+	intel_cdclk_set_cdclk(display, &cdclk_config, INVALID_PIPE);
 }
 
 static void skl_cdclk_uninit_hw(struct intel_display *display)
@@ -1354,7 +1346,7 @@ static void skl_cdclk_uninit_hw(struct intel_display *display)
 	cdclk_config.vco = 0;
 	cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
 
-	skl_set_cdclk(display, &cdclk_config, INVALID_PIPE);
+	intel_cdclk_set_cdclk(display, &cdclk_config, INVALID_PIPE);
 }
 
 struct intel_cdclk_vals {
@@ -2308,11 +2300,6 @@ static void bxt_set_cdclk(struct intel_display *display,
 {
 	struct intel_cdclk_config mid_cdclk_config;
 	int cdclk = cdclk_config->cdclk;
-	int ret;
-
-	ret = intel_cdclk_pre_notify(display);
-	if (ret)
-		return;
 
 	if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)
 		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
@@ -2328,8 +2315,6 @@ static void bxt_set_cdclk(struct intel_display *display,
 	if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
 		xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
 
-	intel_cdclk_post_notify(display, cdclk_config);
-
 	intel_update_cdclk(display);
 
 	/*
@@ -2413,7 +2398,7 @@ static void bxt_cdclk_init_hw(struct intel_display *display)
 	cdclk_config.voltage_level =
 		intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
 
-	bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
+	intel_cdclk_set_cdclk(display, &cdclk_config, INVALID_PIPE);
 }
 
 static void bxt_cdclk_uninit_hw(struct intel_display *display)
@@ -2425,7 +2410,7 @@ static void bxt_cdclk_uninit_hw(struct intel_display *display)
 	cdclk_config.voltage_level =
 		intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk);
 
-	bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE);
+	intel_cdclk_set_cdclk(display, &cdclk_config, INVALID_PIPE);
 }
 
 /**
-- 
2.53.0

✓ CI.KUnit: success for drm/i915/cdclk: cdclk pcode related fixes and refactoring

[Patchwork]

== Series Details ==

Series: drm/i915/cdclk: cdclk pcode related fixes and refactoring
URL   : https://patchwork.freedesktop.org/series/168273/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[17:14:47] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:14:54] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:15:56] Starting KUnit Kernel (1/1)...
[17:15:56] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:15:56] ================== guc_buf (11 subtests) ===================
[17:15:56] [PASSED] test_smallest
[17:15:56] [PASSED] test_largest
[17:15:56] [PASSED] test_granular
[17:15:56] [PASSED] test_unique
[17:15:56] [PASSED] test_overlap
[17:15:56] [PASSED] test_reusable
[17:15:56] [PASSED] test_too_big
[17:15:56] [PASSED] test_flush
[17:15:56] [PASSED] test_lookup
[17:15:56] [PASSED] test_data
[17:15:56] [PASSED] test_class
[17:15:56] ===================== [PASSED] guc_buf =====================
[17:15:56] =================== guc_dbm (7 subtests) ===================
[17:15:56] [PASSED] test_empty
[17:15:56] [PASSED] test_default
[17:15:56] ======================== test_size  ========================
[17:15:56] [PASSED] 4
[17:15:56] [PASSED] 8
[17:15:56] [PASSED] 32
[17:15:56] [PASSED] 256
[17:15:56] ==================== [PASSED] test_size ====================
[17:15:56] ======================= test_reuse  ========================
[17:15:56] [PASSED] 4
[17:15:56] [PASSED] 8
[17:15:56] [PASSED] 32
[17:15:56] [PASSED] 256
[17:15:56] =================== [PASSED] test_reuse ====================
[17:15:56] =================== test_range_overlap  ====================
[17:15:56] [PASSED] 4
[17:15:56] [PASSED] 8
[17:15:56] [PASSED] 32
[17:15:56] [PASSED] 256
[17:15:56] =============== [PASSED] test_range_overlap ================
[17:15:56] =================== test_range_compact  ====================
[17:15:56] [PASSED] 4
[17:15:56] [PASSED] 8
[17:15:56] [PASSED] 32
[17:15:56] [PASSED] 256
[17:15:56] =============== [PASSED] test_range_compact ================
[17:15:56] ==================== test_range_spare  =====================
[17:15:56] [PASSED] 4
[17:15:56] [PASSED] 8
[17:15:56] [PASSED] 32
[17:15:56] [PASSED] 256
[17:15:56] ================ [PASSED] test_range_spare =================
[17:15:56] ===================== [PASSED] guc_dbm =====================
[17:15:56] =================== guc_idm (6 subtests) ===================
[17:15:56] [PASSED] bad_init
[17:15:56] [PASSED] no_init
[17:15:56] [PASSED] init_fini
[17:15:56] [PASSED] check_used
[17:15:56] [PASSED] check_quota
[17:15:56] [PASSED] check_all
[17:15:56] ===================== [PASSED] guc_idm =====================
[17:15:56] ================== no_relay (3 subtests) ===================
[17:15:56] [PASSED] xe_drops_guc2pf_if_not_ready
[17:15:56] [PASSED] xe_drops_guc2vf_if_not_ready
[17:15:56] [PASSED] xe_rejects_send_if_not_ready
[17:15:56] ==================== [PASSED] no_relay =====================
[17:15:56] ================== pf_relay (14 subtests) ==================
[17:15:56] [PASSED] pf_rejects_guc2pf_too_short
[17:15:56] [PASSED] pf_rejects_guc2pf_too_long
[17:15:56] [PASSED] pf_rejects_guc2pf_no_payload
[17:15:56] [PASSED] pf_fails_no_payload
[17:15:56] [PASSED] pf_fails_bad_origin
[17:15:56] [PASSED] pf_fails_bad_type
[17:15:56] [PASSED] pf_txn_reports_error
[17:15:56] [PASSED] pf_txn_sends_pf2guc
[17:15:56] [PASSED] pf_sends_pf2guc
[17:15:56] [SKIPPED] pf_loopback_nop
[17:15:56] [SKIPPED] pf_loopback_echo
[17:15:56] [SKIPPED] pf_loopback_fail
[17:15:56] [SKIPPED] pf_loopback_busy
[17:15:56] [SKIPPED] pf_loopback_retry
[17:15:56] ==================== [PASSED] pf_relay =====================
[17:15:56] ================== vf_relay (3 subtests) ===================
[17:15:56] [PASSED] vf_rejects_guc2vf_too_short
[17:15:56] [PASSED] vf_rejects_guc2vf_too_long
[17:15:56] [PASSED] vf_rejects_guc2vf_no_payload
[17:15:56] ==================== [PASSED] vf_relay =====================
[17:15:56] ================ pf_gt_config (9 subtests) =================
[17:15:56] [PASSED] fair_contexts_1vf
[17:15:56] [PASSED] fair_doorbells_1vf
[17:15:56] [PASSED] fair_ggtt_1vf
[17:15:56] ====================== fair_vram_1vf  ======================
[17:15:56] [PASSED] 3.50 GiB
[17:15:56] [PASSED] 11.5 GiB
[17:15:56] [PASSED] 15.5 GiB
[17:15:56] [PASSED] 31.5 GiB
[17:15:56] [PASSED] 63.5 GiB
[17:15:56] [PASSED] 1.91 GiB
[17:15:56] ================== [PASSED] fair_vram_1vf ==================
[17:15:56] ================ fair_vram_1vf_admin_only  =================
[17:15:56] [PASSED] 3.50 GiB
[17:15:56] [PASSED] 11.5 GiB
[17:15:56] [PASSED] 15.5 GiB
[17:15:56] [PASSED] 31.5 GiB
[17:15:56] [PASSED] 63.5 GiB
[17:15:56] [PASSED] 1.91 GiB
[17:15:56] ============ [PASSED] fair_vram_1vf_admin_only =============
[17:15:56] ====================== fair_contexts  ======================
[17:15:56] [PASSED] 1 VF
[17:15:56] [PASSED] 2 VFs
[17:15:56] [PASSED] 3 VFs
[17:15:56] [PASSED] 4 VFs
[17:15:56] [PASSED] 5 VFs
[17:15:56] [PASSED] 6 VFs
[17:15:56] [PASSED] 7 VFs
[17:15:56] [PASSED] 8 VFs
[17:15:56] [PASSED] 9 VFs
[17:15:56] [PASSED] 10 VFs
[17:15:56] [PASSED] 11 VFs
[17:15:56] [PASSED] 12 VFs
[17:15:56] [PASSED] 13 VFs
[17:15:56] [PASSED] 14 VFs
[17:15:56] [PASSED] 15 VFs
[17:15:56] [PASSED] 16 VFs
[17:15:56] [PASSED] 17 VFs
[17:15:56] [PASSED] 18 VFs
[17:15:56] [PASSED] 19 VFs
[17:15:56] [PASSED] 20 VFs
[17:15:56] [PASSED] 21 VFs
[17:15:56] [PASSED] 22 VFs
[17:15:56] [PASSED] 23 VFs
[17:15:56] [PASSED] 24 VFs
[17:15:56] [PASSED] 25 VFs
[17:15:56] [PASSED] 26 VFs
[17:15:56] [PASSED] 27 VFs
[17:15:56] [PASSED] 28 VFs
[17:15:56] [PASSED] 29 VFs
[17:15:56] [PASSED] 30 VFs
[17:15:56] [PASSED] 31 VFs
[17:15:56] [PASSED] 32 VFs
[17:15:56] [PASSED] 33 VFs
[17:15:56] [PASSED] 34 VFs
[17:15:56] [PASSED] 35 VFs
[17:15:56] [PASSED] 36 VFs
[17:15:56] [PASSED] 37 VFs
[17:15:56] [PASSED] 38 VFs
[17:15:56] [PASSED] 39 VFs
[17:15:56] [PASSED] 40 VFs
[17:15:56] [PASSED] 41 VFs
[17:15:56] [PASSED] 42 VFs
[17:15:56] [PASSED] 43 VFs
[17:15:56] [PASSED] 44 VFs
[17:15:56] [PASSED] 45 VFs
[17:15:56] [PASSED] 46 VFs
[17:15:56] [PASSED] 47 VFs
[17:15:56] [PASSED] 48 VFs
[17:15:56] [PASSED] 49 VFs
[17:15:56] [PASSED] 50 VFs
[17:15:56] [PASSED] 51 VFs
[17:15:56] [PASSED] 52 VFs
[17:15:56] [PASSED] 53 VFs
[17:15:56] [PASSED] 54 VFs
[17:15:56] [PASSED] 55 VFs
[17:15:56] [PASSED] 56 VFs
[17:15:56] [PASSED] 57 VFs
[17:15:56] [PASSED] 58 VFs
[17:15:56] [PASSED] 59 VFs
[17:15:56] [PASSED] 60 VFs
[17:15:56] [PASSED] 61 VFs
[17:15:56] [PASSED] 62 VFs
[17:15:56] [PASSED] 63 VFs
[17:15:56] ================== [PASSED] fair_contexts ==================
[17:15:56] ===================== fair_doorbells  ======================
[17:15:56] [PASSED] 1 VF
[17:15:56] [PASSED] 2 VFs
[17:15:56] [PASSED] 3 VFs
[17:15:56] [PASSED] 4 VFs
[17:15:56] [PASSED] 5 VFs
[17:15:56] [PASSED] 6 VFs
[17:15:56] [PASSED] 7 VFs
[17:15:56] [PASSED] 8 VFs
[17:15:56] [PASSED] 9 VFs
[17:15:56] [PASSED] 10 VFs
[17:15:56] [PASSED] 11 VFs
[17:15:56] [PASSED] 12 VFs
[17:15:56] [PASSED] 13 VFs
[17:15:56] [PASSED] 14 VFs
[17:15:56] [PASSED] 15 VFs
[17:15:56] [PASSED] 16 VFs
[17:15:56] [PASSED] 17 VFs
[17:15:56] [PASSED] 18 VFs
[17:15:56] [PASSED] 19 VFs
[17:15:56] [PASSED] 20 VFs
[17:15:56] [PASSED] 21 VFs
[17:15:56] [PASSED] 22 VFs
[17:15:56] [PASSED] 23 VFs
[17:15:56] [PASSED] 24 VFs
[17:15:56] [PASSED] 25 VFs
[17:15:56] [PASSED] 26 VFs
[17:15:56] [PASSED] 27 VFs
[17:15:56] [PASSED] 28 VFs
[17:15:56] [PASSED] 29 VFs
[17:15:56] [PASSED] 30 VFs
[17:15:56] [PASSED] 31 VFs
[17:15:56] [PASSED] 32 VFs
[17:15:56] [PASSED] 33 VFs
[17:15:56] [PASSED] 34 VFs
[17:15:56] [PASSED] 35 VFs
[17:15:56] [PASSED] 36 VFs
[17:15:56] [PASSED] 37 VFs
[17:15:56] [PASSED] 38 VFs
[17:15:56] [PASSED] 39 VFs
[17:15:56] [PASSED] 40 VFs
[17:15:56] [PASSED] 41 VFs
[17:15:56] [PASSED] 42 VFs
[17:15:56] [PASSED] 43 VFs
[17:15:56] [PASSED] 44 VFs
[17:15:56] [PASSED] 45 VFs
[17:15:56] [PASSED] 46 VFs
[17:15:56] [PASSED] 47 VFs
[17:15:56] [PASSED] 48 VFs
[17:15:56] [PASSED] 49 VFs
[17:15:56] [PASSED] 50 VFs
[17:15:56] [PASSED] 51 VFs
[17:15:56] [PASSED] 52 VFs
[17:15:56] [PASSED] 53 VFs
[17:15:56] [PASSED] 54 VFs
[17:15:56] [PASSED] 55 VFs
[17:15:56] [PASSED] 56 VFs
[17:15:56] [PASSED] 57 VFs
[17:15:56] [PASSED] 58 VFs
[17:15:56] [PASSED] 59 VFs
[17:15:56] [PASSED] 60 VFs
[17:15:56] [PASSED] 61 VFs
[17:15:56] [PASSED] 62 VFs
[17:15:56] [PASSED] 63 VFs
[17:15:56] ================= [PASSED] fair_doorbells ==================
[17:15:56] ======================== fair_ggtt  ========================
[17:15:56] [PASSED] 1 VF
[17:15:56] [PASSED] 2 VFs
[17:15:56] [PASSED] 3 VFs
[17:15:56] [PASSED] 4 VFs
[17:15:56] [PASSED] 5 VFs
[17:15:56] [PASSED] 6 VFs
[17:15:56] [PASSED] 7 VFs
[17:15:56] [PASSED] 8 VFs
[17:15:56] [PASSED] 9 VFs
[17:15:56] [PASSED] 10 VFs
[17:15:56] [PASSED] 11 VFs
[17:15:56] [PASSED] 12 VFs
[17:15:56] [PASSED] 13 VFs
[17:15:56] [PASSED] 14 VFs
[17:15:56] [PASSED] 15 VFs
[17:15:56] [PASSED] 16 VFs
[17:15:56] [PASSED] 17 VFs
[17:15:56] [PASSED] 18 VFs
[17:15:56] [PASSED] 19 VFs
[17:15:56] [PASSED] 20 VFs
[17:15:56] [PASSED] 21 VFs
[17:15:56] [PASSED] 22 VFs
[17:15:56] [PASSED] 23 VFs
[17:15:56] [PASSED] 24 VFs
[17:15:56] [PASSED] 25 VFs
[17:15:56] [PASSED] 26 VFs
[17:15:56] [PASSED] 27 VFs
[17:15:56] [PASSED] 28 VFs
[17:15:56] [PASSED] 29 VFs
[17:15:56] [PASSED] 30 VFs
[17:15:56] [PASSED] 31 VFs
[17:15:56] [PASSED] 32 VFs
[17:15:56] [PASSED] 33 VFs
[17:15:56] [PASSED] 34 VFs
[17:15:56] [PASSED] 35 VFs
[17:15:56] [PASSED] 36 VFs
[17:15:56] [PASSED] 37 VFs
[17:15:56] [PASSED] 38 VFs
[17:15:56] [PASSED] 39 VFs
[17:15:56] [PASSED] 40 VFs
[17:15:56] [PASSED] 41 VFs
[17:15:56] [PASSED] 42 VFs
[17:15:56] [PASSED] 43 VFs
[17:15:56] [PASSED] 44 VFs
[17:15:56] [PASSED] 45 VFs
[17:15:56] [PASSED] 46 VFs
[17:15:56] [PASSED] 47 VFs
[17:15:56] [PASSED] 48 VFs
[17:15:56] [PASSED] 49 VFs
[17:15:56] [PASSED] 50 VFs
[17:15:56] [PASSED] 51 VFs
[17:15:56] [PASSED] 52 VFs
[17:15:56] [PASSED] 53 VFs
[17:15:56] [PASSED] 54 VFs
[17:15:56] [PASSED] 55 VFs
[17:15:56] [PASSED] 56 VFs
[17:15:56] [PASSED] 57 VFs
[17:15:56] [PASSED] 58 VFs
[17:15:56] [PASSED] 59 VFs
[17:15:56] [PASSED] 60 VFs
[17:15:56] [PASSED] 61 VFs
[17:15:56] [PASSED] 62 VFs
[17:15:56] [PASSED] 63 VFs
[17:15:56] ==================== [PASSED] fair_ggtt ====================
[17:15:56] ======================== fair_vram  ========================
[17:15:56] [PASSED] 1 VF
[17:15:56] [PASSED] 2 VFs
[17:15:56] [PASSED] 3 VFs
[17:15:56] [PASSED] 4 VFs
[17:15:56] [PASSED] 5 VFs
[17:15:56] [PASSED] 6 VFs
[17:15:56] [PASSED] 7 VFs
[17:15:56] [PASSED] 8 VFs
[17:15:56] [PASSED] 9 VFs
[17:15:56] [PASSED] 10 VFs
[17:15:56] [PASSED] 11 VFs
[17:15:56] [PASSED] 12 VFs
[17:15:56] [PASSED] 13 VFs
[17:15:56] [PASSED] 14 VFs
[17:15:56] [PASSED] 15 VFs
[17:15:56] [PASSED] 16 VFs
[17:15:56] [PASSED] 17 VFs
[17:15:56] [PASSED] 18 VFs
[17:15:56] [PASSED] 19 VFs
[17:15:56] [PASSED] 20 VFs
[17:15:56] [PASSED] 21 VFs
[17:15:56] [PASSED] 22 VFs
[17:15:56] [PASSED] 23 VFs
[17:15:56] [PASSED] 24 VFs
[17:15:56] [PASSED] 25 VFs
[17:15:56] [PASSED] 26 VFs
[17:15:56] [PASSED] 27 VFs
[17:15:56] [PASSED] 28 VFs
[17:15:56] [PASSED] 29 VFs
[17:15:56] [PASSED] 30 VFs
[17:15:56] [PASSED] 31 VFs
[17:15:56] [PASSED] 32 VFs
[17:15:56] [PASSED] 33 VFs
[17:15:56] [PASSED] 34 VFs
[17:15:56] [PASSED] 35 VFs
[17:15:56] [PASSED] 36 VFs
[17:15:56] [PASSED] 37 VFs
[17:15:56] [PASSED] 38 VFs
[17:15:56] [PASSED] 39 VFs
[17:15:56] [PASSED] 40 VFs
[17:15:56] [PASSED] 41 VFs
[17:15:56] [PASSED] 42 VFs
[17:15:56] [PASSED] 43 VFs
[17:15:56] [PASSED] 44 VFs
[17:15:56] [PASSED] 45 VFs
[17:15:56] [PASSED] 46 VFs
[17:15:56] [PASSED] 47 VFs
[17:15:56] [PASSED] 48 VFs
[17:15:56] [PASSED] 49 VFs
[17:15:56] [PASSED] 50 VFs
[17:15:56] [PASSED] 51 VFs
[17:15:56] [PASSED] 52 VFs
[17:15:57] [PASSED] 53 VFs
[17:15:57] [PASSED] 54 VFs
[17:15:57] [PASSED] 55 VFs
[17:15:57] [PASSED] 56 VFs
[17:15:57] [PASSED] 57 VFs
[17:15:57] [PASSED] 58 VFs
[17:15:57] [PASSED] 59 VFs
[17:15:57] [PASSED] 60 VFs
[17:15:57] [PASSED] 61 VFs
[17:15:57] [PASSED] 62 VFs
[17:15:57] [PASSED] 63 VFs
[17:15:57] ==================== [PASSED] fair_vram ====================
[17:15:57] ================== [PASSED] pf_gt_config ===================
[17:15:57] ===================== lmtt (1 subtest) =====================
[17:15:57] ======================== test_ops  =========================
[17:15:57] [PASSED] 2-level
[17:15:57] [PASSED] multi-level
[17:15:57] ==================== [PASSED] test_ops =====================
[17:15:57] ====================== [PASSED] lmtt =======================
[17:15:57] ================= pf_service (11 subtests) =================
[17:15:57] [PASSED] pf_negotiate_any
[17:15:57] [PASSED] pf_negotiate_base_match
[17:15:57] [PASSED] pf_negotiate_base_newer
[17:15:57] [PASSED] pf_negotiate_base_next
[17:15:57] [SKIPPED] pf_negotiate_base_older
[17:15:57] [PASSED] pf_negotiate_base_prev
[17:15:57] [PASSED] pf_negotiate_latest_match
[17:15:57] [PASSED] pf_negotiate_latest_newer
[17:15:57] [PASSED] pf_negotiate_latest_next
[17:15:57] [SKIPPED] pf_negotiate_latest_older
[17:15:57] [SKIPPED] pf_negotiate_latest_prev
[17:15:57] =================== [PASSED] pf_service ====================
[17:15:57] ================= xe_guc_g2g (2 subtests) ==================
[17:15:57] ============== xe_live_guc_g2g_kunit_default  ==============
[17:15:57] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[17:15:57] ============== xe_live_guc_g2g_kunit_allmem  ===============
[17:15:57] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[17:15:57] =================== [SKIPPED] xe_guc_g2g ===================
[17:15:57] =================== xe_mocs (2 subtests) ===================
[17:15:57] ================ xe_live_mocs_kernel_kunit  ================
[17:15:57] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[17:15:57] ================ xe_live_mocs_reset_kunit  =================
[17:15:57] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[17:15:57] ==================== [SKIPPED] xe_mocs =====================
[17:15:57] ================= xe_migrate (2 subtests) ==================
[17:15:57] ================= xe_migrate_sanity_kunit  =================
[17:15:57] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[17:15:57] ================== xe_validate_ccs_kunit  ==================
[17:15:57] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[17:15:57] =================== [SKIPPED] xe_migrate ===================
[17:15:57] ================== xe_dma_buf (1 subtest) ==================
[17:15:57] ==================== xe_dma_buf_kunit  =====================
[17:15:57] ================ [SKIPPED] xe_dma_buf_kunit ================
[17:15:57] =================== [SKIPPED] xe_dma_buf ===================
[17:15:57] ================= xe_bo_shrink (1 subtest) =================
[17:15:57] =================== xe_bo_shrink_kunit  ====================
[17:15:57] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[17:15:57] ================== [SKIPPED] xe_bo_shrink ==================
[17:15:57] ==================== xe_bo (2 subtests) ====================
[17:15:57] ================== xe_ccs_migrate_kunit  ===================
[17:15:57] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[17:15:57] ==================== xe_bo_evict_kunit  ====================
[17:15:57] =============== [SKIPPED] xe_bo_evict_kunit ================
[17:15:57] ===================== [SKIPPED] xe_bo ======================
[17:15:57] ==================== args (13 subtests) ====================
[17:15:57] [PASSED] count_args_test
[17:15:57] [PASSED] call_args_example
[17:15:57] [PASSED] call_args_test
[17:15:57] [PASSED] drop_first_arg_example
[17:15:57] [PASSED] drop_first_arg_test
[17:15:57] [PASSED] first_arg_example
[17:15:57] [PASSED] first_arg_test
[17:15:57] [PASSED] last_arg_example
[17:15:57] [PASSED] last_arg_test
[17:15:57] [PASSED] pick_arg_example
[17:15:57] [PASSED] if_args_example
[17:15:57] [PASSED] if_args_test
[17:15:57] [PASSED] sep_comma_example
[17:15:57] ====================== [PASSED] args =======================
[17:15:57] =================== xe_pci (3 subtests) ====================
[17:15:57] ==================== check_graphics_ip  ====================
[17:15:57] [PASSED] 12.00 Xe_LP
[17:15:57] [PASSED] 12.10 Xe_LP+
[17:15:57] [PASSED] 12.55 Xe_HPG
[17:15:57] [PASSED] 12.60 Xe_HPC
[17:15:57] [PASSED] 12.70 Xe_LPG
[17:15:57] [PASSED] 12.71 Xe_LPG
[17:15:57] [PASSED] 12.74 Xe_LPG+
[17:15:57] [PASSED] 20.01 Xe2_HPG
[17:15:57] [PASSED] 20.02 Xe2_HPG
[17:15:57] [PASSED] 20.04 Xe2_LPG
[17:15:57] [PASSED] 30.00 Xe3_LPG
[17:15:57] [PASSED] 30.01 Xe3_LPG
[17:15:57] [PASSED] 30.03 Xe3_LPG
[17:15:57] [PASSED] 30.04 Xe3_LPG
[17:15:57] [PASSED] 30.05 Xe3_LPG
[17:15:57] [PASSED] 35.10 Xe3p_LPG
[17:15:57] [PASSED] 35.11 Xe3p_XPC
[17:15:57] ================ [PASSED] check_graphics_ip ================
[17:15:57] ===================== check_media_ip  ======================
[17:15:57] [PASSED] 12.00 Xe_M
[17:15:57] [PASSED] 12.55 Xe_HPM
[17:15:57] [PASSED] 13.00 Xe_LPM+
[17:15:57] [PASSED] 13.01 Xe2_HPM
[17:15:57] [PASSED] 20.00 Xe2_LPM
[17:15:57] [PASSED] 30.00 Xe3_LPM
[17:15:57] [PASSED] 30.02 Xe3_LPM
[17:15:57] [PASSED] 35.00 Xe3p_LPM
[17:15:57] [PASSED] 35.03 Xe3p_HPM
[17:15:57] ================= [PASSED] check_media_ip ==================
[17:15:57] =================== check_platform_desc  ===================
[17:15:57] [PASSED] 0x9A60 (TIGERLAKE)
[17:15:57] [PASSED] 0x9A68 (TIGERLAKE)
[17:15:57] [PASSED] 0x9A70 (TIGERLAKE)
[17:15:57] [PASSED] 0x9A40 (TIGERLAKE)
[17:15:57] [PASSED] 0x9A49 (TIGERLAKE)
[17:15:57] [PASSED] 0x9A59 (TIGERLAKE)
[17:15:57] [PASSED] 0x9A78 (TIGERLAKE)
[17:15:57] [PASSED] 0x9AC0 (TIGERLAKE)
[17:15:57] [PASSED] 0x9AC9 (TIGERLAKE)
[17:15:57] [PASSED] 0x9AD9 (TIGERLAKE)
[17:15:57] [PASSED] 0x9AF8 (TIGERLAKE)
[17:15:57] [PASSED] 0x4C80 (ROCKETLAKE)
[17:15:57] [PASSED] 0x4C8A (ROCKETLAKE)
[17:15:57] [PASSED] 0x4C8B (ROCKETLAKE)
[17:15:57] [PASSED] 0x4C8C (ROCKETLAKE)
[17:15:57] [PASSED] 0x4C90 (ROCKETLAKE)
[17:15:57] [PASSED] 0x4C9A (ROCKETLAKE)
[17:15:57] [PASSED] 0x4680 (ALDERLAKE_S)
[17:15:57] [PASSED] 0x4682 (ALDERLAKE_S)
[17:15:57] [PASSED] 0x4688 (ALDERLAKE_S)
[17:15:57] [PASSED] 0x468A (ALDERLAKE_S)
[17:15:57] [PASSED] 0x468B (ALDERLAKE_S)
[17:15:57] [PASSED] 0x4690 (ALDERLAKE_S)
[17:15:57] [PASSED] 0x4692 (ALDERLAKE_S)
[17:15:57] [PASSED] 0x4693 (ALDERLAKE_S)
[17:15:57] [PASSED] 0x46A0 (ALDERLAKE_P)
[17:15:57] [PASSED] 0x46A1 (ALDERLAKE_P)
[17:15:57] [PASSED] 0x46A2 (ALDERLAKE_P)
[17:15:57] [PASSED] 0x46A3 (ALDERLAKE_P)
[17:15:57] [PASSED] 0x46A6 (ALDERLAKE_P)
[17:15:57] [PASSED] 0x46A8 (ALDERLAKE_P)
[17:15:57] [PASSED] 0x46AA (ALDERLAKE_P)
[17:15:57] [PASSED] 0x462A (ALDERLAKE_P)
[17:15:57] [PASSED] 0x4626 (ALDERLAKE_P)
[17:15:57] [PASSED] 0x4628 (ALDERLAKE_P)
[17:15:57] [PASSED] 0x46B0 (ALDERLAKE_P)
[17:15:57] [PASSED] 0x46B1 (ALDERLAKE_P)
[17:15:57] [PASSED] 0x46B2 (ALDERLAKE_P)
[17:15:57] [PASSED] 0x46B3 (ALDERLAKE_P)
[17:15:57] [PASSED] 0x46C0 (ALDERLAKE_P)
[17:15:57] [PASSED] 0x46C1 (ALDERLAKE_P)
[17:15:57] [PASSED] 0x46C2 (ALDERLAKE_P)
[17:15:57] [PASSED] 0x46C3 (ALDERLAKE_P)
[17:15:57] [PASSED] 0x46D0 (ALDERLAKE_N)
[17:15:57] [PASSED] 0x46D1 (ALDERLAKE_N)
[17:15:57] [PASSED] 0x46D2 (ALDERLAKE_N)
[17:15:57] [PASSED] 0x46D3 (ALDERLAKE_N)
[17:15:57] [PASSED] 0x46D4 (ALDERLAKE_N)
[17:15:57] [PASSED] 0xA721 (ALDERLAKE_P)
[17:15:57] [PASSED] 0xA7A1 (ALDERLAKE_P)
[17:15:57] [PASSED] 0xA7A9 (ALDERLAKE_P)
[17:15:57] [PASSED] 0xA7AC (ALDERLAKE_P)
[17:15:57] [PASSED] 0xA7AD (ALDERLAKE_P)
[17:15:57] [PASSED] 0xA720 (ALDERLAKE_P)
[17:15:57] [PASSED] 0xA7A0 (ALDERLAKE_P)
[17:15:57] [PASSED] 0xA7A8 (ALDERLAKE_P)
[17:15:57] [PASSED] 0xA7AA (ALDERLAKE_P)
[17:15:57] [PASSED] 0xA7AB (ALDERLAKE_P)
[17:15:57] [PASSED] 0xA780 (ALDERLAKE_S)
[17:15:57] [PASSED] 0xA781 (ALDERLAKE_S)
[17:15:57] [PASSED] 0xA782 (ALDERLAKE_S)
[17:15:57] [PASSED] 0xA783 (ALDERLAKE_S)
[17:15:57] [PASSED] 0xA788 (ALDERLAKE_S)
[17:15:57] [PASSED] 0xA789 (ALDERLAKE_S)
[17:15:57] [PASSED] 0xA78A (ALDERLAKE_S)
[17:15:57] [PASSED] 0xA78B (ALDERLAKE_S)
[17:15:57] [PASSED] 0x4905 (DG1)
[17:15:57] [PASSED] 0x4906 (DG1)
[17:15:57] [PASSED] 0x4907 (DG1)
[17:15:57] [PASSED] 0x4908 (DG1)
[17:15:57] [PASSED] 0x4909 (DG1)
[17:15:57] [PASSED] 0x56C0 (DG2)
[17:15:57] [PASSED] 0x56C2 (DG2)
[17:15:57] [PASSED] 0x56C1 (DG2)
[17:15:57] [PASSED] 0x7D51 (METEORLAKE)
[17:15:57] [PASSED] 0x7DD1 (METEORLAKE)
[17:15:57] [PASSED] 0x7D41 (METEORLAKE)
[17:15:57] [PASSED] 0x7D67 (METEORLAKE)
[17:15:57] [PASSED] 0xB640 (METEORLAKE)
[17:15:57] [PASSED] 0x56A0 (DG2)
[17:15:57] [PASSED] 0x56A1 (DG2)
[17:15:57] [PASSED] 0x56A2 (DG2)
[17:15:57] [PASSED] 0x56BE (DG2)
[17:15:57] [PASSED] 0x56BF (DG2)
[17:15:57] [PASSED] 0x5690 (DG2)
[17:15:57] [PASSED] 0x5691 (DG2)
[17:15:57] [PASSED] 0x5692 (DG2)
[17:15:57] [PASSED] 0x56A5 (DG2)
[17:15:57] [PASSED] 0x56A6 (DG2)
[17:15:57] [PASSED] 0x56B0 (DG2)
[17:15:57] [PASSED] 0x56B1 (DG2)
[17:15:57] [PASSED] 0x56BA (DG2)
[17:15:57] [PASSED] 0x56BB (DG2)
[17:15:57] [PASSED] 0x56BC (DG2)
[17:15:57] [PASSED] 0x56BD (DG2)
[17:15:57] [PASSED] 0x5693 (DG2)
[17:15:57] [PASSED] 0x5694 (DG2)
[17:15:57] [PASSED] 0x5695 (DG2)
[17:15:57] [PASSED] 0x56A3 (DG2)
[17:15:57] [PASSED] 0x56A4 (DG2)
[17:15:57] [PASSED] 0x56B2 (DG2)
[17:15:57] [PASSED] 0x56B3 (DG2)
[17:15:57] [PASSED] 0x5696 (DG2)
[17:15:57] [PASSED] 0x5697 (DG2)
[17:15:57] [PASSED] 0xB69 (PVC)
[17:15:57] [PASSED] 0xB6E (PVC)
[17:15:57] [PASSED] 0xBD4 (PVC)
[17:15:57] [PASSED] 0xBD5 (PVC)
[17:15:57] [PASSED] 0xBD6 (PVC)
[17:15:57] [PASSED] 0xBD7 (PVC)
[17:15:57] [PASSED] 0xBD8 (PVC)
[17:15:57] [PASSED] 0xBD9 (PVC)
[17:15:57] [PASSED] 0xBDA (PVC)
[17:15:57] [PASSED] 0xBDB (PVC)
[17:15:57] [PASSED] 0xBE0 (PVC)
[17:15:57] [PASSED] 0xBE1 (PVC)
[17:15:57] [PASSED] 0xBE5 (PVC)
[17:15:57] [PASSED] 0x7D40 (METEORLAKE)
[17:15:57] [PASSED] 0x7D45 (METEORLAKE)
[17:15:57] [PASSED] 0x7D55 (METEORLAKE)
[17:15:57] [PASSED] 0x7D60 (METEORLAKE)
[17:15:57] [PASSED] 0x7DD5 (METEORLAKE)
[17:15:57] [PASSED] 0x6420 (LUNARLAKE)
[17:15:57] [PASSED] 0x64A0 (LUNARLAKE)
[17:15:57] [PASSED] 0x64B0 (LUNARLAKE)
[17:15:57] [PASSED] 0xE202 (BATTLEMAGE)
[17:15:57] [PASSED] 0xE209 (BATTLEMAGE)
[17:15:57] [PASSED] 0xE20B (BATTLEMAGE)
[17:15:57] [PASSED] 0xE20C (BATTLEMAGE)
[17:15:57] [PASSED] 0xE20D (BATTLEMAGE)
[17:15:57] [PASSED] 0xE210 (BATTLEMAGE)
[17:15:57] [PASSED] 0xE211 (BATTLEMAGE)
[17:15:57] [PASSED] 0xE212 (BATTLEMAGE)
[17:15:57] [PASSED] 0xE216 (BATTLEMAGE)
[17:15:57] [PASSED] 0xE220 (BATTLEMAGE)
[17:15:57] [PASSED] 0xE221 (BATTLEMAGE)
[17:15:57] [PASSED] 0xE222 (BATTLEMAGE)
[17:15:57] [PASSED] 0xE223 (BATTLEMAGE)
[17:15:57] [PASSED] 0xB080 (PANTHERLAKE)
[17:15:57] [PASSED] 0xB081 (PANTHERLAKE)
[17:15:57] [PASSED] 0xB082 (PANTHERLAKE)
[17:15:57] [PASSED] 0xB083 (PANTHERLAKE)
[17:15:57] [PASSED] 0xB084 (PANTHERLAKE)
[17:15:57] [PASSED] 0xB085 (PANTHERLAKE)
[17:15:57] [PASSED] 0xB086 (PANTHERLAKE)
[17:15:57] [PASSED] 0xB087 (PANTHERLAKE)
[17:15:57] [PASSED] 0xB08F (PANTHERLAKE)
[17:15:57] [PASSED] 0xB090 (PANTHERLAKE)
[17:15:57] [PASSED] 0xB0A0 (PANTHERLAKE)
[17:15:57] [PASSED] 0xB0B0 (PANTHERLAKE)
[17:15:57] [PASSED] 0xFD80 (PANTHERLAKE)
[17:15:57] [PASSED] 0xFD81 (PANTHERLAKE)
[17:15:57] [PASSED] 0xD740 (NOVALAKE_S)
[17:15:57] [PASSED] 0xD741 (NOVALAKE_S)
[17:15:57] [PASSED] 0xD742 (NOVALAKE_S)
[17:15:57] [PASSED] 0xD743 (NOVALAKE_S)
[17:15:57] [PASSED] 0xD745 (NOVALAKE_S)
[17:15:57] [PASSED] 0xD74A (NOVALAKE_S)
[17:15:57] [PASSED] 0xD74B (NOVALAKE_S)
[17:15:57] [PASSED] 0x674C (CRESCENTISLAND)
[17:15:57] [PASSED] 0x674D (CRESCENTISLAND)
[17:15:57] [PASSED] 0x674E (CRESCENTISLAND)
[17:15:57] [PASSED] 0x674F (CRESCENTISLAND)
[17:15:57] [PASSED] 0x6750 (CRESCENTISLAND)
[17:15:57] [PASSED] 0xD750 (NOVALAKE_P)
[17:15:57] [PASSED] 0xD751 (NOVALAKE_P)
[17:15:57] [PASSED] 0xD752 (NOVALAKE_P)
[17:15:57] [PASSED] 0xD753 (NOVALAKE_P)
[17:15:57] [PASSED] 0xD754 (NOVALAKE_P)
[17:15:57] [PASSED] 0xD755 (NOVALAKE_P)
[17:15:57] [PASSED] 0xD756 (NOVALAKE_P)
[17:15:57] [PASSED] 0xD757 (NOVALAKE_P)
[17:15:57] [PASSED] 0xD75F (NOVALAKE_P)
[17:15:57] =============== [PASSED] check_platform_desc ===============
[17:15:57] ===================== [PASSED] xe_pci ======================
[17:15:57] ============= xe_rtp_tables_test (4 subtests) ==============
[17:15:57] ================== xe_rtp_table_gt_test  ===================
[17:15:57] [PASSED] gt_was/14011060649
[17:15:57] [PASSED] gt_was/14011059788
[17:15:57] [PASSED] gt_was/14015795083
[17:15:57] [PASSED] gt_was/16021867713
[17:15:57] [PASSED] gt_was/14019449301
[17:15:57] [PASSED] gt_was/16028005424
[17:15:57] [PASSED] gt_was/14026578760
[17:15:57] [PASSED] gt_was/1409420604
[17:15:57] [PASSED] gt_was/1408615072
[17:15:57] [PASSED] gt_was/22010523718
[17:15:57] [PASSED] gt_was/14011006942
[17:15:57] [PASSED] gt_was/14014830051
[17:15:57] [PASSED] gt_was/18018781329
[17:15:57] [PASSED] gt_was/1509235366
[17:15:57] [PASSED] gt_was/18018781329
[17:15:57] [PASSED] gt_was/16016694945
[17:15:57] [PASSED] gt_was/14018575942
[17:15:57] [PASSED] gt_was/22016670082
[17:15:57] [PASSED] gt_was/22016670082
[17:15:57] [PASSED] gt_was/14017421178
[17:15:57] [PASSED] gt_was/16025250150
[17:15:57] [PASSED] gt_was/14021871409
[17:15:57] [PASSED] gt_was/16021865536
[17:15:57] [PASSED] gt_was/14021486841
[17:15:57] [PASSED] gt_was/14025160223
[17:15:57] [PASSED] gt_was/14026144927, 16029437861
[17:15:57] [PASSED] gt_was/14025635424
[17:15:57] [PASSED] gt_was/16028005424
[17:15:57] ============== [PASSED] xe_rtp_table_gt_test ===============
[17:15:57] ================== xe_rtp_table_gt_test  ===================
[17:15:57] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[17:15:57] [PASSED] gt_tunings/Tuning: 32B Access Enable
[17:15:57] [PASSED] gt_tunings/Tuning: L3 cache
[17:15:57] [PASSED] gt_tunings/Tuning: L3 cache - media
[17:15:57] [PASSED] gt_tunings/Tuning: Compression Overfetch
[17:15:57] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[17:15:57] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[17:15:57] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[17:15:57] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[17:15:57] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[17:15:57] [PASSED] gt_tunings/Tuning: Stateless compression control
[17:15:57] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[17:15:57] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[17:15:57] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[17:15:57] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[17:15:57] ============== [PASSED] xe_rtp_table_gt_test ===============
[17:15:57] ================== xe_rtp_table_oob_test  ==================
[17:15:57] [PASSED] oob_was/1607983814
[17:15:57] [PASSED] oob_was/16010904313
[17:15:57] [PASSED] oob_was/18022495364
[17:15:57] [PASSED] oob_was/22012773006
[17:15:57] [PASSED] oob_was/14014475959
[17:15:57] [PASSED] oob_was/22011391025
[17:15:57] [PASSED] oob_was/22012727170
[17:15:57] [PASSED] oob_was/22012727685
[17:15:57] [PASSED] oob_was/22016596838
[17:15:57] [PASSED] oob_was/18020744125
[17:15:57] [PASSED] oob_was/1409600907
[17:15:57] [PASSED] oob_was/22014953428
[17:15:57] [PASSED] oob_was/16017236439
[17:15:57] [PASSED] oob_was/14019821291
[17:15:57] [PASSED] oob_was/14015076503
[17:15:57] [PASSED] oob_was/14018913170
[17:15:57] [PASSED] oob_was/14018094691
[17:15:57] [PASSED] oob_was/18024947630
[17:15:57] [PASSED] oob_was/16022287689
[17:15:57] [PASSED] oob_was/13011645652
[17:15:57] [PASSED] oob_was/14022293748
[17:15:57] [PASSED] oob_was/22019794406
[17:15:57] [PASSED] oob_was/22019338487
[17:15:57] [PASSED] oob_was/16023588340
[17:15:57] [PASSED] oob_was/14019789679
[17:15:57] [PASSED] oob_was/14022866841
[17:15:57] [PASSED] oob_was/16021333562
[17:15:57] [PASSED] oob_was/14016712196
[17:15:57] [PASSED] oob_was/14015568240
[17:15:57] [PASSED] oob_was/18013179988
[17:15:57] [PASSED] oob_was/1508761755
[17:15:57] [PASSED] oob_was/16023105232
[17:15:57] [PASSED] oob_was/16026508708
[17:15:57] [PASSED] oob_was/14020001231
[17:15:57] [PASSED] oob_was/16023683509
[17:15:57] [PASSED] oob_was/14025515070
[17:15:57] [PASSED] oob_was/15015404425_disable
[17:15:57] [PASSED] oob_was/16026007364
[17:15:57] [PASSED] oob_was/14020316580
[17:15:57] [PASSED] oob_was/14025883347
[17:15:57] ============== [PASSED] xe_rtp_table_oob_test ==============
[17:15:57] ================ xe_rtp_table_dev_oob_test  ================
[17:15:57] [PASSED] device_oob_was/22010954014
[17:15:57] [PASSED] device_oob_was/15015404425
[17:15:57] [PASSED] device_oob_was/22019338487_display
[17:15:57] [PASSED] device_oob_was/14022085890
[17:15:57] [PASSED] device_oob_was/14026539277
[17:15:57] [PASSED] device_oob_was/14026633728
[17:15:57] [PASSED] device_oob_was/14026746987
[17:15:57] [PASSED] device_oob_was/14026779378
[17:15:57] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[17:15:57] =============== [PASSED] xe_rtp_tables_test ================
[17:15:57] =================== xe_rtp (3 subtests) ====================
[17:15:57] =================== xe_rtp_rules_tests  ====================
[17:15:57] [PASSED] no
[17:15:57] [PASSED] yes
[17:15:57] [PASSED] no-and-no
[17:15:57] [PASSED] no-and-yes
[17:15:57] [PASSED] yes-and-no
[17:15:57] [PASSED] yes-and-yes
[17:15:57] [PASSED] no-or-no
[17:15:57] [PASSED] no-or-yes
[17:15:57] [PASSED] yes-or-no
[17:15:57] [PASSED] yes-or-yes
[17:15:57] [PASSED] no-yes-or-yes-no
[17:15:57] [PASSED] no-yes-or-yes-yes
[17:15:57] [PASSED] yes-yes-or-no-yes
[17:15:57] [PASSED] yes-yes-or-yes-yes
[17:15:57] [PASSED] no-no-or-yes-or-no
[17:15:57] [PASSED] or
[17:15:57] [PASSED] or-yes
[17:15:57] [PASSED] or-no
[17:15:57] [PASSED] yes-or
[17:15:57] [PASSED] no-or
[17:15:57] [PASSED] no-or-or-yes
[17:15:57] [PASSED] yes-or-or-no
[17:15:57] [PASSED] no-or-or-no
[17:15:57] [PASSED] missing-context-engine-class
[17:15:57] [PASSED] missing-context-engine-class-or-yes
[17:15:57] [PASSED] missing-context-engine-class-or-or-yes
[17:15:57] =============== [PASSED] xe_rtp_rules_tests ================
[17:15:57] =============== xe_rtp_process_to_sr_tests  ================
[17:15:57] [PASSED] coalesce-same-reg
[17:15:57] [PASSED] no-match-no-add
[17:15:57] [PASSED] two-regs-two-entries
[17:15:57] [PASSED] clr-one-set-other
[17:15:57] [PASSED] set-field
[17:15:57] [PASSED] conflict-duplicate
[17:15:57] [PASSED] conflict-not-disjoint
[17:15:57] [PASSED] conflict-reg-type
[17:15:57] [PASSED] bad-mcr-reg-forced-to-regular
[17:15:57] [PASSED] bad-regular-reg-forced-to-mcr
[17:15:57] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[17:15:57] ================== xe_rtp_process_tests  ===================
[17:15:57] [PASSED] active1
[17:15:57] [PASSED] active2
[17:15:57] [PASSED] active-inactive
[17:15:57] [PASSED] inactive-active
[17:15:57] [PASSED] inactive-active-inactive
[17:15:57] [PASSED] inactive-inactive-inactive
[17:15:57] ============== [PASSED] xe_rtp_process_tests ===============
[17:15:57] ===================== [PASSED] xe_rtp ======================
[17:15:57] ==================== xe_wa (1 subtest) =====================
[17:15:57] ======================== xe_wa_gt  =========================
[17:15:57] [PASSED] TIGERLAKE B0
[17:15:57] [PASSED] DG1 A0
[17:15:57] [PASSED] DG1 B0
[17:15:57] [PASSED] ALDERLAKE_S A0
[17:15:57] [PASSED] ALDERLAKE_S B0
[17:15:57] [PASSED] ALDERLAKE_S C0
[17:15:57] [PASSED] ALDERLAKE_S D0
[17:15:57] [PASSED] ALDERLAKE_P A0
[17:15:57] [PASSED] ALDERLAKE_P B0
[17:15:57] [PASSED] ALDERLAKE_P C0
[17:15:57] [PASSED] ALDERLAKE_S RPLS D0
[17:15:57] [PASSED] ALDERLAKE_P RPLU E0
[17:15:57] [PASSED] DG2 G10 C0
[17:15:57] [PASSED] DG2 G11 B1
[17:15:57] [PASSED] DG2 G12 A1
[17:15:57] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:15:57] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:15:57] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[17:15:57] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[17:15:57] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[17:15:57] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[17:15:57] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[17:15:57] ==================== [PASSED] xe_wa_gt =====================
[17:15:57] ====================== [PASSED] xe_wa ======================
[17:15:57] ============================================================
[17:15:57] Testing complete. Ran 716 tests: passed: 698, skipped: 18
[17:15:57] Elapsed time: 69.780s total, 7.230s configuring, 61.280s building, 1.209s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[17:15:57] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:16:00] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
In file included from ../drivers/gpu/drm/tests/drm_bridge_test.c:21:
../drivers/gpu/drm/tests/drm_kunit_edid.h:958:28: warning: ‘test_edid_hdmi_4k_rgb_yuv420_dc_max_340mhz’ defined but not used [-Wunused-const-variable=]
  958 | static const unsigned char test_edid_hdmi_4k_rgb_yuv420_dc_max_340mhz[] = {
      |                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/tests/drm_kunit_edid.h:726:28: warning: ‘test_edid_hdmi_1080p_rgb_yuv_dc_max_340mhz’ defined but not used [-Wunused-const-variable=]
  726 | static const unsigned char test_edid_hdmi_1080p_rgb_yuv_dc_max_340mhz[] = {
      |                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/tests/drm_kunit_edid.h:612:28: warning: ‘test_edid_hdmi_1080p_rgb_yuv_dc_max_200mhz’ defined but not used [-Wunused-const-variable=]
  612 | static const unsigned char test_edid_hdmi_1080p_rgb_yuv_dc_max_200mhz[] = {
      |                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/tests/drm_kunit_edid.h:498:28: warning: ‘test_edid_hdmi_1080p_rgb_max_340mhz’ defined but not used [-Wunused-const-variable=]
  498 | static const unsigned char test_edid_hdmi_1080p_rgb_max_340mhz[] = {
      |                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/tests/drm_kunit_edid.h:390:28: warning: ‘test_edid_hdmi_1080p_rgb_max_200mhz_hdr’ defined but not used [-Wunused-const-variable=]
  390 | static const unsigned char test_edid_hdmi_1080p_rgb_max_200mhz_hdr[] = {
      |                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/tests/drm_kunit_edid.h:271:28: warning: ‘test_edid_hdmi_1080p_rgb_max_200mhz’ defined but not used [-Wunused-const-variable=]
  271 | static const unsigned char test_edid_hdmi_1080p_rgb_max_200mhz[] = {
      |                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/tests/drm_kunit_edid.h:163:28: warning: ‘test_edid_hdmi_1080p_rgb_max_100mhz’ defined but not used [-Wunused-const-variable=]
  163 | static const unsigned char test_edid_hdmi_1080p_rgb_max_100mhz[] = {
      |                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/tests/drm_kunit_edid.h:57:28: warning: ‘test_edid_dvi_1080p’ defined but not used [-Wunused-const-variable=]
   57 | static const unsigned char test_edid_dvi_1080p[] = {
      |                            ^~~~~~~~~~~~~~~~~~~

[17:16:47] Starting KUnit Kernel (1/1)...
[17:16:47] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:16:47] ============ drm_test_pick_cmdline (2 subtests) ============
[17:16:47] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[17:16:47] =============== drm_test_pick_cmdline_named  ===============
[17:16:47] [PASSED] NTSC
[17:16:47] [PASSED] NTSC-J
[17:16:47] [PASSED] PAL
[17:16:47] [PASSED] PAL-M
[17:16:47] =========== [PASSED] drm_test_pick_cmdline_named ===========
[17:16:47] ============== [PASSED] drm_test_pick_cmdline ==============
[17:16:47] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[17:16:47] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[17:16:47] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[17:16:47] =========== drm_validate_clone_mode (2 subtests) ===========
[17:16:47] ============== drm_test_check_in_clone_mode  ===============
[17:16:47] [PASSED] in_clone_mode
[17:16:47] [PASSED] not_in_clone_mode
[17:16:47] ========== [PASSED] drm_test_check_in_clone_mode ===========
[17:16:47] =============== drm_test_check_valid_clones  ===============
[17:16:47] [PASSED] not_in_clone_mode
[17:16:47] [PASSED] valid_clone
[17:16:47] [PASSED] invalid_clone
[17:16:47] =========== [PASSED] drm_test_check_valid_clones ===========
[17:16:47] ============= [PASSED] drm_validate_clone_mode =============
[17:16:47] ============= drm_validate_modeset (1 subtest) =============
[17:16:47] [PASSED] drm_test_check_connector_changed_modeset
[17:16:47] ============== [PASSED] drm_validate_modeset ===============
[17:16:47] ====== drm_test_bridge_get_current_state (2 subtests) ======
[17:16:47] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[17:16:47] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[17:16:47] ======== [PASSED] drm_test_bridge_get_current_state ========
[17:16:47] ====== drm_test_bridge_helper_reset_crtc (4 subtests) ======
[17:16:47] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[17:16:47] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[17:16:47] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[17:16:47] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[17:16:47] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[17:16:47] ============== drm_bridge_alloc (2 subtests) ===============
[17:16:47] [PASSED] drm_test_drm_bridge_alloc_basic
[17:16:47] [PASSED] drm_test_drm_bridge_alloc_get_put
[17:16:47] ================ [PASSED] drm_bridge_alloc =================
[17:16:47] ============= drm_bridge_bus_fmt (5 subtests) ==============
[17:16:47] [PASSED] drm_test_bridge_rgb_yuv_rgb
[17:16:47] [PASSED] drm_test_bridge_must_convert_to_yuv444
[17:16:47] [PASSED] drm_test_bridge_hdmi_auto_rgb
[17:16:47] [PASSED] drm_test_bridge_auto_first
[17:16:47] [PASSED] drm_test_bridge_rgb_yuv_no_path
[17:16:47] =============== [PASSED] drm_bridge_bus_fmt ================
[17:16:47] ============= drm_cmdline_parser (40 subtests) =============
[17:16:47] [PASSED] drm_test_cmdline_force_d_only
[17:16:47] [PASSED] drm_test_cmdline_force_D_only_dvi
[17:16:47] [PASSED] drm_test_cmdline_force_D_only_hdmi
[17:16:47] [PASSED] drm_test_cmdline_force_D_only_not_digital
[17:16:47] [PASSED] drm_test_cmdline_force_e_only
[17:16:47] [PASSED] drm_test_cmdline_res
[17:16:47] [PASSED] drm_test_cmdline_res_vesa
[17:16:47] [PASSED] drm_test_cmdline_res_vesa_rblank
[17:16:47] [PASSED] drm_test_cmdline_res_rblank
[17:16:47] [PASSED] drm_test_cmdline_res_bpp
[17:16:47] [PASSED] drm_test_cmdline_res_refresh
[17:16:47] [PASSED] drm_test_cmdline_res_bpp_refresh
[17:16:47] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[17:16:47] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[17:16:47] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[17:16:47] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[17:16:47] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[17:16:47] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[17:16:47] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[17:16:47] [PASSED] drm_test_cmdline_res_margins_force_on
[17:16:47] [PASSED] drm_test_cmdline_res_vesa_margins
[17:16:47] [PASSED] drm_test_cmdline_name
[17:16:47] [PASSED] drm_test_cmdline_name_bpp
[17:16:47] [PASSED] drm_test_cmdline_name_option
[17:16:47] [PASSED] drm_test_cmdline_name_bpp_option
[17:16:47] [PASSED] drm_test_cmdline_rotate_0
[17:16:47] [PASSED] drm_test_cmdline_rotate_90
[17:16:47] [PASSED] drm_test_cmdline_rotate_180
[17:16:47] [PASSED] drm_test_cmdline_rotate_270
[17:16:47] [PASSED] drm_test_cmdline_hmirror
[17:16:47] [PASSED] drm_test_cmdline_vmirror
[17:16:47] [PASSED] drm_test_cmdline_margin_options
[17:16:47] [PASSED] drm_test_cmdline_multiple_options
[17:16:47] [PASSED] drm_test_cmdline_bpp_extra_and_option
[17:16:47] [PASSED] drm_test_cmdline_extra_and_option
[17:16:47] [PASSED] drm_test_cmdline_freestanding_options
[17:16:47] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[17:16:47] [PASSED] drm_test_cmdline_panel_orientation
[17:16:47] ================ drm_test_cmdline_invalid  =================
[17:16:47] [PASSED] margin_only
[17:16:47] [PASSED] interlace_only
[17:16:47] [PASSED] res_missing_x
[17:16:47] [PASSED] res_missing_y
[17:16:47] [PASSED] res_bad_y
[17:16:47] [PASSED] res_missing_y_bpp
[17:16:47] [PASSED] res_bad_bpp
[17:16:47] [PASSED] res_bad_refresh
[17:16:47] [PASSED] res_bpp_refresh_force_on_off
[17:16:47] [PASSED] res_invalid_mode
[17:16:47] [PASSED] res_bpp_wrong_place_mode
[17:16:47] [PASSED] name_bpp_refresh
[17:16:47] [PASSED] name_refresh
[17:16:47] [PASSED] name_refresh_wrong_mode
[17:16:47] [PASSED] name_refresh_invalid_mode
[17:16:47] [PASSED] rotate_multiple
[17:16:47] [PASSED] rotate_invalid_val
[17:16:47] [PASSED] rotate_truncated
[17:16:47] [PASSED] invalid_option
[17:16:47] [PASSED] invalid_tv_option
[17:16:47] [PASSED] truncated_tv_option
[17:16:47] ============ [PASSED] drm_test_cmdline_invalid =============
[17:16:47] =============== drm_test_cmdline_tv_options  ===============
[17:16:47] [PASSED] NTSC
[17:16:47] [PASSED] NTSC_443
[17:16:47] [PASSED] NTSC_J
[17:16:47] [PASSED] PAL
[17:16:47] [PASSED] PAL_M
[17:16:47] [PASSED] PAL_N
[17:16:47] [PASSED] SECAM
[17:16:47] [PASSED] MONO_525
[17:16:47] [PASSED] MONO_625
[17:16:47] =========== [PASSED] drm_test_cmdline_tv_options ===========
[17:16:47] =============== [PASSED] drm_cmdline_parser ================
[17:16:47] ========== drmm_connector_hdmi_init (20 subtests) ==========
[17:16:47] [PASSED] drm_test_connector_hdmi_init_valid
[17:16:47] [PASSED] drm_test_connector_hdmi_init_bpc_8
[17:16:47] [PASSED] drm_test_connector_hdmi_init_bpc_10
[17:16:47] [PASSED] drm_test_connector_hdmi_init_bpc_12
[17:16:47] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[17:16:47] [PASSED] drm_test_connector_hdmi_init_bpc_null
[17:16:47] [PASSED] drm_test_connector_hdmi_init_formats_empty
[17:16:47] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[17:16:47] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[17:16:47] [PASSED] supported_formats=0x9 yuv420_allowed=1
[17:16:47] [PASSED] supported_formats=0x9 yuv420_allowed=0
[17:16:47] [PASSED] supported_formats=0x5 yuv420_allowed=1
[17:16:47] [PASSED] supported_formats=0x5 yuv420_allowed=0
[17:16:47] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[17:16:47] [PASSED] drm_test_connector_hdmi_init_null_ddc
[17:16:47] [PASSED] drm_test_connector_hdmi_init_null_product
[17:16:47] [PASSED] drm_test_connector_hdmi_init_null_vendor
[17:16:47] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[17:16:47] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[17:16:47] [PASSED] drm_test_connector_hdmi_init_product_valid
[17:16:47] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[17:16:47] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[17:16:47] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[17:16:47] ========= drm_test_connector_hdmi_init_type_valid  =========
[17:16:47] [PASSED] HDMI-A
[17:16:47] [PASSED] HDMI-B
[17:16:47] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[17:16:47] ======== drm_test_connector_hdmi_init_type_invalid  ========
[17:16:47] [PASSED] Unknown
[17:16:47] [PASSED] VGA
[17:16:47] [PASSED] DVI-I
[17:16:47] [PASSED] DVI-D
[17:16:47] [PASSED] DVI-A
[17:16:47] [PASSED] Composite
[17:16:47] [PASSED] SVIDEO
[17:16:47] [PASSED] LVDS
[17:16:47] [PASSED] Component
[17:16:47] [PASSED] DIN
[17:16:47] [PASSED] DP
[17:16:47] [PASSED] TV
[17:16:47] [PASSED] eDP
[17:16:47] [PASSED] Virtual
[17:16:47] [PASSED] DSI
[17:16:47] [PASSED] DPI
[17:16:47] [PASSED] Writeback
[17:16:47] [PASSED] SPI
[17:16:47] [PASSED] USB
[17:16:47] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[17:16:47] ============ [PASSED] drmm_connector_hdmi_init =============
[17:16:47] ============= drmm_connector_init (3 subtests) =============
[17:16:47] [PASSED] drm_test_drmm_connector_init
[17:16:47] [PASSED] drm_test_drmm_connector_init_null_ddc
[17:16:47] ========= drm_test_drmm_connector_init_type_valid  =========
[17:16:47] [PASSED] Unknown
[17:16:47] [PASSED] VGA
[17:16:47] [PASSED] DVI-I
[17:16:47] [PASSED] DVI-D
[17:16:47] [PASSED] DVI-A
[17:16:47] [PASSED] Composite
[17:16:47] [PASSED] SVIDEO
[17:16:47] [PASSED] LVDS
[17:16:47] [PASSED] Component
[17:16:47] [PASSED] DIN
[17:16:47] [PASSED] DP
[17:16:47] [PASSED] HDMI-A
[17:16:47] [PASSED] HDMI-B
[17:16:47] [PASSED] TV
[17:16:47] [PASSED] eDP
[17:16:47] [PASSED] Virtual
[17:16:47] [PASSED] DSI
[17:16:47] [PASSED] DPI
[17:16:47] [PASSED] Writeback
[17:16:47] [PASSED] SPI
[17:16:47] [PASSED] USB
[17:16:47] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[17:16:47] =============== [PASSED] drmm_connector_init ===============
[17:16:47] ========= drm_connector_dynamic_init (6 subtests) ==========
[17:16:47] [PASSED] drm_test_drm_connector_dynamic_init
[17:16:47] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[17:16:47] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[17:16:47] [PASSED] drm_test_drm_connector_dynamic_init_properties
[17:16:47] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[17:16:47] [PASSED] Unknown
[17:16:47] [PASSED] VGA
[17:16:47] [PASSED] DVI-I
[17:16:47] [PASSED] DVI-D
[17:16:47] [PASSED] DVI-A
[17:16:47] [PASSED] Composite
[17:16:47] [PASSED] SVIDEO
[17:16:47] [PASSED] LVDS
[17:16:47] [PASSED] Component
[17:16:47] [PASSED] DIN
[17:16:47] [PASSED] DP
[17:16:47] [PASSED] HDMI-A
[17:16:47] [PASSED] HDMI-B
[17:16:47] [PASSED] TV
[17:16:47] [PASSED] eDP
[17:16:47] [PASSED] Virtual
[17:16:47] [PASSED] DSI
[17:16:47] [PASSED] DPI
[17:16:47] [PASSED] Writeback
[17:16:47] [PASSED] SPI
[17:16:47] [PASSED] USB
[17:16:47] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[17:16:47] ======== drm_test_drm_connector_dynamic_init_name  =========
[17:16:47] [PASSED] Unknown
[17:16:47] [PASSED] VGA
[17:16:47] [PASSED] DVI-I
[17:16:47] [PASSED] DVI-D
[17:16:47] [PASSED] DVI-A
[17:16:47] [PASSED] Composite
[17:16:47] [PASSED] SVIDEO
[17:16:47] [PASSED] LVDS
[17:16:47] [PASSED] Component
[17:16:47] [PASSED] DIN
[17:16:47] [PASSED] DP
[17:16:47] [PASSED] HDMI-A
[17:16:47] [PASSED] HDMI-B
[17:16:47] [PASSED] TV
[17:16:47] [PASSED] eDP
[17:16:47] [PASSED] Virtual
[17:16:47] [PASSED] DSI
[17:16:47] [PASSED] DPI
[17:16:47] [PASSED] Writeback
[17:16:47] [PASSED] SPI
[17:16:47] [PASSED] USB
[17:16:47] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[17:16:47] =========== [PASSED] drm_connector_dynamic_init ============
[17:16:47] ==== drm_connector_dynamic_register_early (4 subtests) =====
[17:16:47] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[17:16:47] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[17:16:47] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[17:16:47] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[17:16:47] ====== [PASSED] drm_connector_dynamic_register_early =======
[17:16:47] ======= drm_connector_dynamic_register (7 subtests) ========
[17:16:47] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[17:16:47] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[17:16:47] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[17:16:47] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[17:16:47] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[17:16:47] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[17:16:47] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[17:16:47] ========= [PASSED] drm_connector_dynamic_register ==========
[17:16:47] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[17:16:47] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[17:16:47] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[17:16:47] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[17:16:47] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[17:16:47] ========== drm_test_get_tv_mode_from_name_valid  ===========
[17:16:47] [PASSED] NTSC
[17:16:47] [PASSED] NTSC-443
[17:16:47] [PASSED] NTSC-J
[17:16:47] [PASSED] PAL
[17:16:47] [PASSED] PAL-M
[17:16:47] [PASSED] PAL-N
[17:16:47] [PASSED] SECAM
[17:16:47] [PASSED] Mono
[17:16:47] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[17:16:47] [PASSED] drm_test_get_tv_mode_from_name_truncated
[17:16:47] ============ [PASSED] drm_get_tv_mode_from_name ============
[17:16:47] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[17:16:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[17:16:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[17:16:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[17:16:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[17:16:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[17:16:47] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[17:16:47] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[17:16:47] [PASSED] VIC 96
[17:16:47] [PASSED] VIC 97
[17:16:47] [PASSED] VIC 101
[17:16:47] [PASSED] VIC 102
[17:16:47] [PASSED] VIC 106
[17:16:47] [PASSED] VIC 107
[17:16:47] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[17:16:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[17:16:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[17:16:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[17:16:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[17:16:47] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[17:16:47] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[17:16:47] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[17:16:47] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[17:16:47] [PASSED] Automatic
[17:16:47] [PASSED] Full
[17:16:47] [PASSED] Limited 16:235
[17:16:47] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[17:16:47] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[17:16:47] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[17:16:47] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[17:16:47] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[17:16:47] [PASSED] RGB
[17:16:47] [PASSED] YUV 4:2:0
[17:16:47] [PASSED] YUV 4:2:2
[17:16:47] [PASSED] YUV 4:4:4
[17:16:47] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[17:16:47] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[17:16:47] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[17:16:47] ============= drm_damage_helper (21 subtests) ==============
[17:16:47] [PASSED] drm_test_damage_iter_no_damage
[17:16:47] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[17:16:47] [PASSED] drm_test_damage_iter_no_damage_src_moved
[17:16:47] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[17:16:47] [PASSED] drm_test_damage_iter_no_damage_not_visible
[17:16:47] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[17:16:47] [PASSED] drm_test_damage_iter_no_damage_no_fb
[17:16:47] [PASSED] drm_test_damage_iter_simple_damage
[17:16:47] [PASSED] drm_test_damage_iter_single_damage
[17:16:47] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[17:16:47] [PASSED] drm_test_damage_iter_single_damage_outside_src
[17:16:47] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[17:16:47] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[17:16:47] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[17:16:47] [PASSED] drm_test_damage_iter_single_damage_src_moved
[17:16:47] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[17:16:47] [PASSED] drm_test_damage_iter_damage
[17:16:47] [PASSED] drm_test_damage_iter_damage_one_intersect
[17:16:47] [PASSED] drm_test_damage_iter_damage_one_outside
[17:16:47] [PASSED] drm_test_damage_iter_damage_src_moved
[17:16:47] [PASSED] drm_test_damage_iter_damage_not_visible
[17:16:47] ================ [PASSED] drm_damage_helper ================
[17:16:47] ============== drm_dp_mst_helper (3 subtests) ==============
[17:16:47] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[17:16:47] [PASSED] Clock 154000 BPP 30 DSC disabled
[17:16:47] [PASSED] Clock 234000 BPP 30 DSC disabled
[17:16:47] [PASSED] Clock 297000 BPP 24 DSC disabled
[17:16:47] [PASSED] Clock 332880 BPP 24 DSC enabled
[17:16:47] [PASSED] Clock 324540 BPP 24 DSC enabled
[17:16:47] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[17:16:47] ============== drm_test_dp_mst_calc_pbn_div  ===============
[17:16:47] [PASSED] Link rate 2000000 lane count 4
[17:16:47] [PASSED] Link rate 2000000 lane count 2
[17:16:47] [PASSED] Link rate 2000000 lane count 1
[17:16:47] [PASSED] Link rate 1350000 lane count 4
[17:16:47] [PASSED] Link rate 1350000 lane count 2
[17:16:47] [PASSED] Link rate 1350000 lane count 1
[17:16:47] [PASSED] Link rate 1000000 lane count 4
[17:16:47] [PASSED] Link rate 1000000 lane count 2
[17:16:47] [PASSED] Link rate 1000000 lane count 1
[17:16:47] [PASSED] Link rate 810000 lane count 4
[17:16:47] [PASSED] Link rate 810000 lane count 2
[17:16:47] [PASSED] Link rate 810000 lane count 1
[17:16:47] [PASSED] Link rate 540000 lane count 4
[17:16:47] [PASSED] Link rate 540000 lane count 2
[17:16:47] [PASSED] Link rate 540000 lane count 1
[17:16:47] [PASSED] Link rate 270000 lane count 4
[17:16:47] [PASSED] Link rate 270000 lane count 2
[17:16:47] [PASSED] Link rate 270000 lane count 1
[17:16:47] [PASSED] Link rate 162000 lane count 4
[17:16:47] [PASSED] Link rate 162000 lane count 2
[17:16:47] [PASSED] Link rate 162000 lane count 1
[17:16:47] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[17:16:47] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[17:16:47] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[17:16:47] [PASSED] DP_POWER_UP_PHY with port number
[17:16:47] [PASSED] DP_POWER_DOWN_PHY with port number
[17:16:47] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[17:16:47] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[17:16:47] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[17:16:47] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[17:16:47] [PASSED] DP_QUERY_PAYLOAD with port number
[17:16:47] [PASSED] DP_QUERY_PAYLOAD with VCPI
[17:16:47] [PASSED] DP_REMOTE_DPCD_READ with port number
[17:16:47] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[17:16:47] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[17:16:47] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[17:16:47] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[17:16:47] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[17:16:47] [PASSED] DP_REMOTE_I2C_READ with port number
[17:16:47] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[17:16:47] [PASSED] DP_REMOTE_I2C_READ with transactions array
[17:16:47] [PASSED] DP_REMOTE_I2C_WRITE with port number
[17:16:47] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[17:16:47] [PASSED] DP_REMOTE_I2C_WRITE with data array
[17:16:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[17:16:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[17:16:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[17:16:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[17:16:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[17:16:47] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[17:16:47] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[17:16:47] ================ [PASSED] drm_dp_mst_helper ================
[17:16:47] ================== drm_exec (7 subtests) ===================
[17:16:47] [PASSED] sanitycheck
[17:16:47] [PASSED] test_lock
[17:16:47] [PASSED] test_lock_unlock
[17:16:47] [PASSED] test_duplicates
[17:16:47] [PASSED] test_prepare
[17:16:47] [PASSED] test_prepare_array
[17:16:47] [PASSED] test_multiple_loops
[17:16:47] ==================== [PASSED] drm_exec =====================
[17:16:47] =========== drm_format_helper_test (17 subtests) ===========
[17:16:47] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[17:16:47] [PASSED] single_pixel_source_buffer
[17:16:47] [PASSED] single_pixel_clip_rectangle
[17:16:47] [PASSED] well_known_colors
[17:16:47] [PASSED] destination_pitch
[17:16:47] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[17:16:47] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[17:16:47] [PASSED] single_pixel_source_buffer
[17:16:47] [PASSED] single_pixel_clip_rectangle
[17:16:47] [PASSED] well_known_colors
[17:16:47] [PASSED] destination_pitch
[17:16:47] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[17:16:47] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[17:16:47] [PASSED] single_pixel_source_buffer
[17:16:47] [PASSED] single_pixel_clip_rectangle
[17:16:47] [PASSED] well_known_colors
[17:16:47] [PASSED] destination_pitch
[17:16:47] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[17:16:47] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[17:16:47] [PASSED] single_pixel_source_buffer
[17:16:47] [PASSED] single_pixel_clip_rectangle
[17:16:47] [PASSED] well_known_colors
[17:16:47] [PASSED] destination_pitch
[17:16:47] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[17:16:47] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[17:16:47] [PASSED] single_pixel_source_buffer
[17:16:47] [PASSED] single_pixel_clip_rectangle
[17:16:47] [PASSED] well_known_colors
[17:16:47] [PASSED] destination_pitch
[17:16:47] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[17:16:47] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[17:16:47] [PASSED] single_pixel_source_buffer
[17:16:47] [PASSED] single_pixel_clip_rectangle
[17:16:47] [PASSED] well_known_colors
[17:16:47] [PASSED] destination_pitch
[17:16:47] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[17:16:47] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[17:16:47] [PASSED] single_pixel_source_buffer
[17:16:47] [PASSED] single_pixel_clip_rectangle
[17:16:47] [PASSED] well_known_colors
[17:16:47] [PASSED] destination_pitch
[17:16:47] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[17:16:47] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[17:16:47] [PASSED] single_pixel_source_buffer
[17:16:47] [PASSED] single_pixel_clip_rectangle
[17:16:47] [PASSED] well_known_colors
[17:16:47] [PASSED] destination_pitch
[17:16:47] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[17:16:47] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[17:16:47] [PASSED] single_pixel_source_buffer
[17:16:47] [PASSED] single_pixel_clip_rectangle
[17:16:47] [PASSED] well_known_colors
[17:16:47] [PASSED] destination_pitch
[17:16:47] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[17:16:47] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[17:16:47] [PASSED] single_pixel_source_buffer
[17:16:47] [PASSED] single_pixel_clip_rectangle
[17:16:47] [PASSED] well_known_colors
[17:16:47] [PASSED] destination_pitch
[17:16:47] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[17:16:47] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[17:16:47] [PASSED] single_pixel_source_buffer
[17:16:47] [PASSED] single_pixel_clip_rectangle
[17:16:47] [PASSED] well_known_colors
[17:16:47] [PASSED] destination_pitch
[17:16:47] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[17:16:47] ============== drm_test_fb_xrgb8888_to_mono  ===============
[17:16:47] [PASSED] single_pixel_source_buffer
[17:16:47] [PASSED] single_pixel_clip_rectangle
[17:16:47] [PASSED] well_known_colors
[17:16:47] [PASSED] destination_pitch
[17:16:47] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[17:16:47] ==================== drm_test_fb_swab  =====================
[17:16:47] [PASSED] single_pixel_source_buffer
[17:16:47] [PASSED] single_pixel_clip_rectangle
[17:16:47] [PASSED] well_known_colors
[17:16:47] [PASSED] destination_pitch
[17:16:47] ================ [PASSED] drm_test_fb_swab =================
[17:16:47] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[17:16:47] [PASSED] single_pixel_source_buffer
[17:16:47] [PASSED] single_pixel_clip_rectangle
[17:16:47] [PASSED] well_known_colors
[17:16:47] [PASSED] destination_pitch
[17:16:47] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[17:16:47] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[17:16:47] [PASSED] single_pixel_source_buffer
[17:16:47] [PASSED] single_pixel_clip_rectangle
[17:16:47] [PASSED] well_known_colors
[17:16:47] [PASSED] destination_pitch
[17:16:47] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[17:16:47] ================= drm_test_fb_clip_offset  =================
[17:16:47] [PASSED] pass through
[17:16:47] [PASSED] horizontal offset
[17:16:47] [PASSED] vertical offset
[17:16:47] [PASSED] horizontal and vertical offset
[17:16:47] [PASSED] horizontal offset (custom pitch)
[17:16:47] [PASSED] vertical offset (custom pitch)
[17:16:47] [PASSED] horizontal and vertical offset (custom pitch)
[17:16:47] ============= [PASSED] drm_test_fb_clip_offset =============
[17:16:47] =================== drm_test_fb_memcpy  ====================
[17:16:47] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[17:16:47] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[17:16:47] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[17:16:47] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[17:16:47] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[17:16:47] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[17:16:47] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[17:16:47] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[17:16:47] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[17:16:47] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[17:16:47] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[17:16:47] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[17:16:47] =============== [PASSED] drm_test_fb_memcpy ================
[17:16:47] ============= [PASSED] drm_format_helper_test ==============
[17:16:47] ================= drm_format (18 subtests) =================
[17:16:47] [PASSED] drm_test_format_block_width_invalid
[17:16:47] [PASSED] drm_test_format_block_width_one_plane
[17:16:47] [PASSED] drm_test_format_block_width_two_plane
[17:16:47] [PASSED] drm_test_format_block_width_three_plane
[17:16:47] [PASSED] drm_test_format_block_width_tiled
[17:16:47] [PASSED] drm_test_format_block_height_invalid
[17:16:47] [PASSED] drm_test_format_block_height_one_plane
[17:16:47] [PASSED] drm_test_format_block_height_two_plane
[17:16:47] [PASSED] drm_test_format_block_height_three_plane
[17:16:47] [PASSED] drm_test_format_block_height_tiled
[17:16:47] [PASSED] drm_test_format_min_pitch_invalid
[17:16:47] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[17:16:47] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[17:16:47] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[17:16:47] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[17:16:47] [PASSED] drm_test_format_min_pitch_two_plane
[17:16:47] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[17:16:47] [PASSED] drm_test_format_min_pitch_tiled
[17:16:47] =================== [PASSED] drm_format ====================
[17:16:47] ============== drm_framebuffer (10 subtests) ===============
[17:16:47] ========== drm_test_framebuffer_check_src_coords  ==========
[17:16:47] [PASSED] Success: source fits into fb
[17:16:47] [PASSED] Fail: overflowing fb with x-axis coordinate
[17:16:47] [PASSED] Fail: overflowing fb with y-axis coordinate
[17:16:47] [PASSED] Fail: overflowing fb with source width
[17:16:47] [PASSED] Fail: overflowing fb with source height
[17:16:47] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[17:16:47] [PASSED] drm_test_framebuffer_cleanup
[17:16:47] =============== drm_test_framebuffer_create  ===============
[17:16:47] [PASSED] ABGR8888 normal sizes
[17:16:47] [PASSED] ABGR8888 max sizes
[17:16:47] [PASSED] ABGR8888 pitch greater than min required
[17:16:47] [PASSED] ABGR8888 pitch less than min required
[17:16:47] [PASSED] ABGR8888 Invalid width
[17:16:47] [PASSED] ABGR8888 Invalid buffer handle
[17:16:47] [PASSED] No pixel format
[17:16:47] [PASSED] ABGR8888 Width 0
[17:16:47] [PASSED] ABGR8888 Height 0
[17:16:47] [PASSED] ABGR8888 Out of bound height * pitch combination
[17:16:47] [PASSED] ABGR8888 Large buffer offset
[17:16:47] [PASSED] ABGR8888 Buffer offset for inexistent plane
[17:16:47] [PASSED] ABGR8888 Invalid flag
[17:16:47] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[17:16:47] [PASSED] ABGR8888 Valid buffer modifier
[17:16:47] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[17:16:47] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[17:16:47] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[17:16:47] [PASSED] NV12 Normal sizes
[17:16:47] [PASSED] NV12 Max sizes
[17:16:47] [PASSED] NV12 Invalid pitch
[17:16:47] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[17:16:47] [PASSED] NV12 different  modifier per-plane
[17:16:47] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[17:16:47] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[17:16:47] [PASSED] NV12 Modifier for inexistent plane
[17:16:47] [PASSED] NV12 Handle for inexistent plane
[17:16:47] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[17:16:47] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[17:16:47] [PASSED] YVU420 Normal sizes
[17:16:47] [PASSED] YVU420 Max sizes
[17:16:47] [PASSED] YVU420 Invalid pitch
[17:16:47] [PASSED] YVU420 Different pitches
[17:16:47] [PASSED] YVU420 Different buffer offsets/pitches
[17:16:47] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[17:16:47] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[17:16:47] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[17:16:47] [PASSED] YVU420 Valid modifier
[17:16:47] [PASSED] YVU420 Different modifiers per plane
[17:16:47] [PASSED] YVU420 Modifier for inexistent plane
[17:16:47] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[17:16:47] [PASSED] X0L2 Normal sizes
[17:16:47] [PASSED] X0L2 Max sizes
[17:16:47] [PASSED] X0L2 Invalid pitch
[17:16:47] [PASSED] X0L2 Pitch greater than minimum required
[17:16:47] [PASSED] X0L2 Handle for inexistent plane
[17:16:47] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[17:16:47] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[17:16:47] [PASSED] X0L2 Valid modifier
[17:16:47] [PASSED] X0L2 Modifier for inexistent plane
[17:16:47] =========== [PASSED] drm_test_framebuffer_create ===========
[17:16:47] [PASSED] drm_test_framebuffer_free
[17:16:47] [PASSED] drm_test_framebuffer_init
[17:16:47] [PASSED] drm_test_framebuffer_init_bad_format
[17:16:47] [PASSED] drm_test_framebuffer_init_dev_mismatch
[17:16:47] [PASSED] drm_test_framebuffer_lookup
[17:16:47] [PASSED] drm_test_framebuffer_lookup_inexistent
[17:16:47] [PASSED] drm_test_framebuffer_modifiers_not_supported
[17:16:47] ================= [PASSED] drm_framebuffer =================
[17:16:47] ================ drm_gem_shmem (8 subtests) ================
[17:16:47] [PASSED] drm_gem_shmem_test_obj_create
[17:16:47] [PASSED] drm_gem_shmem_test_obj_create_private
[17:16:47] [PASSED] drm_gem_shmem_test_pin_pages
[17:16:47] [PASSED] drm_gem_shmem_test_vmap
[17:16:47] [PASSED] drm_gem_shmem_test_get_sg_table
[17:16:47] [PASSED] drm_gem_shmem_test_get_pages_sgt
[17:16:47] [PASSED] drm_gem_shmem_test_madvise
[17:16:47] [PASSED] drm_gem_shmem_test_purge
[17:16:47] ================== [PASSED] drm_gem_shmem ==================
[17:16:47] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[17:16:47] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[17:16:47] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[17:16:47] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[17:16:47] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[17:16:47] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[17:16:47] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[17:16:47] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[17:16:47] [PASSED] Automatic
[17:16:47] [PASSED] Full
[17:16:47] [PASSED] Limited 16:235
[17:16:47] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[17:16:47] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[17:16:47] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[17:16:47] [PASSED] drm_test_check_disable_connector
[17:16:47] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[17:16:47] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[17:16:47] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[17:16:47] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[17:16:47] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[17:16:47] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[17:16:47] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[17:16:47] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[17:16:47] [PASSED] drm_test_check_output_bpc_dvi
[17:16:47] [PASSED] drm_test_check_output_bpc_format_vic_1
[17:16:47] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[17:16:47] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[17:16:47] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[17:16:47] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[17:16:47] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[17:16:47] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[17:16:47] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[17:16:47] ============ drm_test_check_hdmi_color_format  =============
[17:16:47] [PASSED] AUTO -> RGB
[17:16:47] [PASSED] YCBCR422 -> YUV422
[17:16:47] [PASSED] YCBCR420 -> YUV420
[17:16:47] [PASSED] YCBCR444 -> YUV444
[17:16:47] [PASSED] RGB -> RGB
[17:16:47] ======== [PASSED] drm_test_check_hdmi_color_format =========
[17:16:47] ======== drm_test_check_hdmi_color_format_420_only  ========
[17:16:47] [PASSED] RGB should fail
[17:16:47] [PASSED] YUV444 should fail
[17:16:47] [PASSED] YUV422 should fail
[17:16:47] [PASSED] YUV420 should work
[17:16:47] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[17:16:47] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[17:16:47] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[17:16:47] [PASSED] drm_test_check_broadcast_rgb_value
[17:16:47] [PASSED] drm_test_check_bpc_8_value
[17:16:47] [PASSED] drm_test_check_bpc_10_value
[17:16:47] [PASSED] drm_test_check_bpc_12_value
[17:16:47] [PASSED] drm_test_check_format_value
[17:16:47] [PASSED] drm_test_check_tmds_char_value
[17:16:47] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[17:16:47] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[17:16:47] [PASSED] drm_test_check_mode_valid
[17:16:47] [PASSED] drm_test_check_mode_valid_reject
[17:16:47] [PASSED] drm_test_check_mode_valid_reject_rate
[17:16:47] [PASSED] drm_test_check_mode_valid_reject_max_clock
[17:16:47] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[17:16:47] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[17:16:47] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[17:16:47] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[17:16:47] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[17:16:47] [PASSED] drm_test_check_infoframes
[17:16:47] [PASSED] drm_test_check_reject_avi_infoframe
[17:16:47] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[17:16:47] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[17:16:47] [PASSED] drm_test_check_reject_audio_infoframe
[17:16:47] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[17:16:47] ================= drm_managed (2 subtests) =================
[17:16:47] [PASSED] drm_test_managed_release_action
[17:16:47] [PASSED] drm_test_managed_run_action
[17:16:47] =================== [PASSED] drm_managed ===================
[17:16:47] =================== drm_mm (6 subtests) ====================
[17:16:47] [PASSED] drm_test_mm_init
[17:16:47] [PASSED] drm_test_mm_debug
[17:16:47] [PASSED] drm_test_mm_align32
[17:16:47] [PASSED] drm_test_mm_align64
[17:16:47] [PASSED] drm_test_mm_lowest
[17:16:47] [PASSED] drm_test_mm_highest
[17:16:47] ===================== [PASSED] drm_mm ======================
[17:16:47] ============= drm_modes_analog_tv (5 subtests) =============
[17:16:47] [PASSED] drm_test_modes_analog_tv_mono_576i
[17:16:47] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[17:16:47] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[17:16:47] [PASSED] drm_test_modes_analog_tv_pal_576i
[17:16:47] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[17:16:47] =============== [PASSED] drm_modes_analog_tv ===============
[17:16:47] ============== drm_plane_helper (2 subtests) ===============
[17:16:47] =============== drm_test_check_plane_state  ================
[17:16:47] [PASSED] clipping_simple
[17:16:47] [PASSED] clipping_rotate_reflect
[17:16:47] [PASSED] positioning_simple
[17:16:47] [PASSED] upscaling
[17:16:47] [PASSED] downscaling
[17:16:47] [PASSED] rounding1
[17:16:47] [PASSED] rounding2
[17:16:47] [PASSED] rounding3
[17:16:47] [PASSED] rounding4
[17:16:47] =========== [PASSED] drm_test_check_plane_state ============
[17:16:47] =========== drm_test_check_invalid_plane_state  ============
[17:16:47] [PASSED] positioning_invalid
[17:16:47] [PASSED] upscaling_invalid
[17:16:47] [PASSED] downscaling_invalid
[17:16:47] ======= [PASSED] drm_test_check_invalid_plane_state ========
[17:16:47] ================ [PASSED] drm_plane_helper =================
[17:16:47] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[17:16:47] ====== drm_test_connector_helper_tv_get_modes_check  =======
[17:16:47] [PASSED] None
[17:16:47] [PASSED] PAL
[17:16:47] [PASSED] NTSC
[17:16:47] [PASSED] Both, NTSC Default
[17:16:47] [PASSED] Both, PAL Default
[17:16:47] [PASSED] Both, NTSC Default, with PAL on command-line
[17:16:47] [PASSED] Both, PAL Default, with NTSC on command-line
[17:16:47] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[17:16:47] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[17:16:47] ================== drm_rect (9 subtests) ===================
[17:16:47] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[17:16:47] [PASSED] drm_test_rect_clip_scaled_not_clipped
[17:16:47] [PASSED] drm_test_rect_clip_scaled_clipped
[17:16:47] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[17:16:47] ================= drm_test_rect_intersect  =================
[17:16:47] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[17:16:47] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[17:16:47] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[17:16:47] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[17:16:47] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[17:16:47] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[17:16:47] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[17:16:47] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[17:16:47] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[17:16:47] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[17:16:47] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[17:16:47] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[17:16:47] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[17:16:47] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[17:16:47] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[17:16:47] ============= [PASSED] drm_test_rect_intersect =============
[17:16:47] ================ drm_test_rect_calc_hscale  ================
[17:16:47] [PASSED] normal use
[17:16:47] [PASSED] out of max range
[17:16:47] [PASSED] out of min range
[17:16:47] [PASSED] zero dst
[17:16:47] [PASSED] negative src
[17:16:47] [PASSED] negative dst
[17:16:47] ============ [PASSED] drm_test_rect_calc_hscale ============
[17:16:47] ================ drm_test_rect_calc_vscale  ================
[17:16:47] [PASSED] normal use
[17:16:47] [PASSED] out of max range
[17:16:47] [PASSED] out of min range
[17:16:47] [PASSED] zero dst
[17:16:47] [PASSED] negative src
[17:16:47] [PASSED] negative dst
[17:16:47] ============ [PASSED] drm_test_rect_calc_vscale ============
[17:16:47] ================== drm_test_rect_rotate  ===================
[17:16:47] [PASSED] reflect-x
[17:16:47] [PASSED] reflect-y
[17:16:47] [PASSED] rotate-0
[17:16:47] [PASSED] rotate-90
[17:16:47] [PASSED] rotate-180
[17:16:47] [PASSED] rotate-270
[17:16:47] ============== [PASSED] drm_test_rect_rotate ===============
[17:16:47] ================ drm_test_rect_rotate_inv  =================
[17:16:47] [PASSED] reflect-x
[17:16:47] [PASSED] reflect-y
[17:16:47] [PASSED] rotate-0
[17:16:47] [PASSED] rotate-90
[17:16:47] [PASSED] rotate-180
[17:16:47] [PASSED] rotate-270
[17:16:47] ============ [PASSED] drm_test_rect_rotate_inv =============
[17:16:47] ==================== [PASSED] drm_rect =====================
[17:16:47] ============ drm_sysfb_modeset_test (1 subtest) ============
[17:16:47] ============ drm_test_sysfb_build_fourcc_list  =============
[17:16:47] [PASSED] no native formats
[17:16:47] [PASSED] XRGB8888 as native format
[17:16:47] [PASSED] remove duplicates
[17:16:47] [PASSED] convert alpha formats
[17:16:47] [PASSED] random formats
[17:16:47] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[17:16:47] ============= [PASSED] drm_sysfb_modeset_test ==============
[17:16:47] ================== drm_fixp (2 subtests) ===================
[17:16:47] [PASSED] drm_test_int2fixp
[17:16:47] [PASSED] drm_test_sm2fixp
[17:16:47] ==================== [PASSED] drm_fixp =====================
[17:16:47] ============================================================
[17:16:47] Testing complete. Ran 639 tests: passed: 639
[17:16:47] Elapsed time: 49.992s total, 2.809s configuring, 46.906s building, 0.246s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[17:16:47] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:16:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:17:06] Starting KUnit Kernel (1/1)...
[17:17:06] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:17:06] ================= ttm_device (5 subtests) ==================
[17:17:06] [PASSED] ttm_device_init_basic
[17:17:06] [PASSED] ttm_device_init_multiple
[17:17:06] [PASSED] ttm_device_fini_basic
[17:17:06] [PASSED] ttm_device_init_no_vma_man
[17:17:06] ================== ttm_device_init_pools  ==================
[17:17:06] [PASSED] No DMA allocations, no DMA32 required
[17:17:06] [PASSED] DMA allocations, DMA32 required
[17:17:06] [PASSED] No DMA allocations, DMA32 required
[17:17:06] [PASSED] DMA allocations, no DMA32 required
[17:17:06] ============== [PASSED] ttm_device_init_pools ==============
[17:17:06] =================== [PASSED] ttm_device ====================
[17:17:06] ================== ttm_pool (8 subtests) ===================
[17:17:06] ================== ttm_pool_alloc_basic  ===================
[17:17:06] [PASSED] One page
[17:17:06] [PASSED] More than one page
[17:17:06] [PASSED] Above the allocation limit
[17:17:06] [PASSED] One page, with coherent DMA mappings enabled
[17:17:06] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:17:06] ============== [PASSED] ttm_pool_alloc_basic ===============
[17:17:06] ============== ttm_pool_alloc_basic_dma_addr  ==============
[17:17:06] [PASSED] One page
[17:17:06] [PASSED] More than one page
[17:17:06] [PASSED] Above the allocation limit
[17:17:06] [PASSED] One page, with coherent DMA mappings enabled
[17:17:06] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:17:06] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[17:17:06] [PASSED] ttm_pool_alloc_order_caching_match
[17:17:06] [PASSED] ttm_pool_alloc_caching_mismatch
[17:17:06] [PASSED] ttm_pool_alloc_order_mismatch
[17:17:06] [PASSED] ttm_pool_free_dma_alloc
[17:17:06] [PASSED] ttm_pool_free_no_dma_alloc
[17:17:06] [PASSED] ttm_pool_fini_basic
[17:17:06] ==================== [PASSED] ttm_pool =====================
[17:17:06] ================ ttm_resource (8 subtests) =================
[17:17:06] ================= ttm_resource_init_basic  =================
[17:17:06] [PASSED] Init resource in TTM_PL_SYSTEM
[17:17:06] [PASSED] Init resource in TTM_PL_VRAM
[17:17:06] [PASSED] Init resource in a private placement
[17:17:06] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[17:17:06] ============= [PASSED] ttm_resource_init_basic =============
[17:17:06] [PASSED] ttm_resource_init_pinned
[17:17:06] [PASSED] ttm_resource_fini_basic
[17:17:06] [PASSED] ttm_resource_manager_init_basic
[17:17:06] [PASSED] ttm_resource_manager_usage_basic
[17:17:06] [PASSED] ttm_resource_manager_set_used_basic
[17:17:06] [PASSED] ttm_sys_man_alloc_basic
[17:17:06] [PASSED] ttm_sys_man_free_basic
[17:17:06] ================== [PASSED] ttm_resource ===================
[17:17:06] =================== ttm_tt (15 subtests) ===================
[17:17:06] ==================== ttm_tt_init_basic  ====================
[17:17:06] [PASSED] Page-aligned size
[17:17:06] [PASSED] Extra pages requested
[17:17:06] ================ [PASSED] ttm_tt_init_basic ================
[17:17:06] [PASSED] ttm_tt_init_misaligned
[17:17:06] [PASSED] ttm_tt_fini_basic
[17:17:06] [PASSED] ttm_tt_fini_sg
[17:17:06] [PASSED] ttm_tt_fini_shmem
[17:17:06] [PASSED] ttm_tt_create_basic
[17:17:06] [PASSED] ttm_tt_create_invalid_bo_type
[17:17:06] [PASSED] ttm_tt_create_ttm_exists
[17:17:06] [PASSED] ttm_tt_create_failed
[17:17:06] [PASSED] ttm_tt_destroy_basic
[17:17:06] [PASSED] ttm_tt_populate_null_ttm
[17:17:06] [PASSED] ttm_tt_populate_populated_ttm
[17:17:06] [PASSED] ttm_tt_unpopulate_basic
[17:17:06] [PASSED] ttm_tt_unpopulate_empty_ttm
[17:17:06] [PASSED] ttm_tt_swapin_basic
[17:17:06] ===================== [PASSED] ttm_tt ======================
[17:17:06] =================== ttm_bo (14 subtests) ===================
[17:17:06] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[17:17:06] [PASSED] Cannot be interrupted and sleeps
[17:17:06] [PASSED] Cannot be interrupted, locks straight away
[17:17:06] [PASSED] Can be interrupted, sleeps
[17:17:06] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[17:17:06] [PASSED] ttm_bo_reserve_locked_no_sleep
[17:17:06] [PASSED] ttm_bo_reserve_no_wait_ticket
[17:17:06] [PASSED] ttm_bo_reserve_double_resv
[17:17:06] [PASSED] ttm_bo_reserve_interrupted
[17:17:06] [PASSED] ttm_bo_reserve_deadlock
[17:17:06] [PASSED] ttm_bo_unreserve_basic
[17:17:06] [PASSED] ttm_bo_unreserve_pinned
[17:17:06] [PASSED] ttm_bo_unreserve_bulk
[17:17:06] [PASSED] ttm_bo_fini_basic
[17:17:06] [PASSED] ttm_bo_fini_shared_resv
[17:17:06] [PASSED] ttm_bo_pin_basic
[17:17:06] [PASSED] ttm_bo_pin_unpin_resource
[17:17:06] [PASSED] ttm_bo_multiple_pin_one_unpin
[17:17:06] ===================== [PASSED] ttm_bo ======================
[17:17:06] ============== ttm_bo_validate (22 subtests) ===============
[17:17:06] ============== ttm_bo_init_reserved_sys_man  ===============
[17:17:06] [PASSED] Buffer object for userspace
[17:17:06] [PASSED] Kernel buffer object
[17:17:06] [PASSED] Shared buffer object
[17:17:06] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[17:17:06] ============== ttm_bo_init_reserved_mock_man  ==============
[17:17:06] [PASSED] Buffer object for userspace
[17:17:06] [PASSED] Kernel buffer object
[17:17:06] [PASSED] Shared buffer object
[17:17:06] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[17:17:06] [PASSED] ttm_bo_init_reserved_resv
[17:17:06] ================== ttm_bo_validate_basic  ==================
[17:17:06] [PASSED] Buffer object for userspace
[17:17:06] [PASSED] Kernel buffer object
[17:17:06] [PASSED] Shared buffer object
[17:17:06] ============== [PASSED] ttm_bo_validate_basic ==============
[17:17:06] [PASSED] ttm_bo_validate_invalid_placement
[17:17:06] ============= ttm_bo_validate_same_placement  ==============
[17:17:06] [PASSED] System manager
[17:17:06] [PASSED] VRAM manager
[17:17:06] ========= [PASSED] ttm_bo_validate_same_placement ==========
[17:17:06] [PASSED] ttm_bo_validate_failed_alloc
[17:17:06] [PASSED] ttm_bo_validate_pinned
[17:17:06] [PASSED] ttm_bo_validate_busy_placement
[17:17:06] ================ ttm_bo_validate_multihop  =================
[17:17:06] [PASSED] Buffer object for userspace
[17:17:06] [PASSED] Kernel buffer object
[17:17:06] [PASSED] Shared buffer object
[17:17:06] ============ [PASSED] ttm_bo_validate_multihop =============
[17:17:06] ========== ttm_bo_validate_no_placement_signaled  ==========
[17:17:06] [PASSED] Buffer object in system domain, no page vector
[17:17:06] [PASSED] Buffer object in system domain with an existing page vector
[17:17:06] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[17:17:06] ======== ttm_bo_validate_no_placement_not_signaled  ========
[17:17:06] [PASSED] Buffer object for userspace
[17:17:06] [PASSED] Kernel buffer object
[17:17:06] [PASSED] Shared buffer object
[17:17:06] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[17:17:06] [PASSED] ttm_bo_validate_move_fence_signaled
[17:17:06] ========= ttm_bo_validate_move_fence_not_signaled  =========
[17:17:06] [PASSED] Waits for GPU
[17:17:06] [PASSED] Tries to lock straight away
[17:17:06] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[17:17:06] [PASSED] ttm_bo_validate_swapout
[17:17:06] [PASSED] ttm_bo_validate_happy_evict
[17:17:06] [PASSED] ttm_bo_validate_all_pinned_evict
[17:17:06] [PASSED] ttm_bo_validate_allowed_only_evict
[17:17:06] [PASSED] ttm_bo_validate_deleted_evict
[17:17:06] [PASSED] ttm_bo_validate_busy_domain_evict
[17:17:06] [PASSED] ttm_bo_validate_evict_gutting
[17:17:06] [PASSED] ttm_bo_validate_recrusive_evict
[17:17:06] ================= [PASSED] ttm_bo_validate =================
[17:17:06] ============================================================
[17:17:06] Testing complete. Ran 102 tests: passed: 102
[17:17:06] Elapsed time: 19.055s total, 2.782s configuring, 16.006s building, 0.223s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

Re: [PATCH 02/14] drm/i915/cdclk: Pass CDCLK in MHz to pcode on DG2

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We are currently trying to pass the CDCLK in kHz to the pcode
> on DG2, while the pcode expects a value in MHz units. Adjust
> the units appropriately.

How is it working? :o

Fixes: ?

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 9ca56bab281f..9718062d8d6c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2703,8 +2703,10 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
>  	 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK,
>  	 * which basically means we choose the maximum of old and new CDCLK, if we know both
>  	 */
> -	if (change_cdclk)
> +	if (change_cdclk) {
>  		cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
> +		cdclk = DIV_ROUND_UP(cdclk, 1000);
> +	}

I'd consider s/cdclk/cdclk_mhz/g here and in intel_pcode_notify() to
emphasize it's not kHz.

>  	/*
>  	 * According to "Sequence For Pipe Count Change",
> @@ -2740,8 +2742,10 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
>  	 * According to "Sequence After Frequency Change",
>  	 * set bits 25:16 to current CDCLK
>  	 */
> -	if (update_cdclk)
> +	if (update_cdclk) {
>  		cdclk = new_cdclk_state->actual.cdclk;
> +		cdclk = DIV_ROUND_UP(cdclk, 1000);
> +	}

Ditto.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>  
>  	/*
>  	 * According to "Sequence For Pipe Count Change",

-- 
Jani Nikula, Intel

Re: [PATCH 01/14] drm/i915/cdclk: Don't bail if pcode post nofify fails

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We already changed the actual cdclk frequency by the time we do
> the pcode post notify. So skipping the subsequent readout is plain
> wrong.

Fixes: ?

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 189ae2d3cfc9..9ca56bab281f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2301,12 +2301,10 @@ static void bxt_set_cdclk(struct intel_display *display,
>  						       HSW_PCODE_DE_WRITE_FREQ_REQ,
>  						       cdclk_config->voltage_level, 2);
>  	}
> -	if (ret) {
> +	if (ret)
>  		drm_err(display->drm,
>  			"PCode CDCLK freq set failed, (err %d, freq %d)\n",
>  			ret, cdclk);
> -		return;
> -	}
>  
>  	intel_update_cdclk(display);

-- 
Jani Nikula, Intel

Re: [PATCH 07/14] drm/i915/dg2: s/intel_/dg2_/ for DG2 specific stuff

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_pcode_*notify() are all DG2 specific code. Rename them
> to have a dg2_ namespace.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 31 ++++++++++------------
>  1 file changed, 14 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index bbf3603f889b..659c1c0e3432 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2575,19 +2575,16 @@ void intel_cdclk_dump_config(struct intel_display *display,
>  		    cdclk_config->voltage_level);
>  }
>  
> -static void intel_pcode_notify(struct intel_display *display,
> -			       u8 voltage_level,
> -			       u8 active_pipe_count,
> -			       u16 cdclk,
> -			       bool cdclk_update_valid,
> -			       bool pipe_count_update_valid)
> +static void dg2_cdclk_pcode_notify(struct intel_display *display,
> +				   u8 voltage_level,
> +				   u8 active_pipe_count,
> +				   u16 cdclk,
> +				   bool cdclk_update_valid,
> +				   bool pipe_count_update_valid)
>  {
>  	int ret;
>  	u32 update_mask = 0;
>  
> -	if (!display->platform.dg2)
> -		return;
> -
>  	update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
>  
>  	if (cdclk_update_valid)
> @@ -2672,7 +2669,7 @@ static bool dg2_power_well_count(struct intel_display *display,
>  	return display->platform.dg2 ? hweight8(cdclk_state->active_pipes) : 0;
>  }
>  
> -static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
> +static void dg2_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
>  {
>  	struct intel_display *display = to_intel_display(state);
>  	const struct intel_cdclk_state *old_cdclk_state =
> @@ -2715,11 +2712,11 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
>  	if (update_pipe_count)
>  		num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
>  
> -	intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> -			   change_cdclk, update_pipe_count);
> +	dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> +			       change_cdclk, update_pipe_count);
>  }
>  
> -static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
> +static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state)
>  {
>  	struct intel_display *display = to_intel_display(state);
>  	const struct intel_cdclk_state *new_cdclk_state =
> @@ -2754,8 +2751,8 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
>  	if (update_pipe_count)
>  		num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
>  
> -	intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> -			   update_cdclk, update_pipe_count);
> +	dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> +			       update_cdclk, update_pipe_count);
>  }
>  
>  bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
> @@ -2821,7 +2818,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
>  	drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
>  
>  	if (display->platform.dg2)
> -		intel_cdclk_pcode_pre_notify(state);
> +		dg2_cdclk_pcode_pre_notify(state);
>  
>  	intel_set_cdclk(display, &cdclk_config, pipe,
>  			"Pre changing CDCLK to");
> @@ -2865,7 +2862,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
>  			"Post changing CDCLK to");
>  
>  	if (display->platform.dg2)
> -		intel_cdclk_pcode_post_notify(state);
> +		dg2_cdclk_pcode_post_notify(state);
>  }
>  
>  /* pixels per CDCLK */

-- 
Jani Nikula, Intel

Re: [PATCH 09/14] drm/i915/cdclk: Unify pcode related debugs

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The debug spew for the cdclk pcode per/post notify is very
> inconsistent between different platforms. Unify it all to
> the same form.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 65 ++++++++++++----------
>  1 file changed, 36 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 09981a112db4..542724256d0f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -891,7 +891,7 @@ static void bdw_set_cdclk(struct intel_display *display,
>  	ret = intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
>  	if (ret) {
>  		drm_err(display->drm,
> -			"failed to inform pcode about cdclk change\n");
> +			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
>  		return;
>  	}
>  
> @@ -918,8 +918,11 @@ static void bdw_set_cdclk(struct intel_display *display,
>  	if (ret)
>  		drm_err(display->drm, "Switching back to LCPLL failed\n");
>  
> -	intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
> -				 cdclk_config->voltage_level);
> +	ret = intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
> +				       cdclk_config->voltage_level);
> +	if (ret)
> +		drm_err(display->drm,
> +			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
>  
>  	intel_de_write(display, CDCLK_FREQ,
>  		       DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
> @@ -1181,7 +1184,7 @@ static void skl_set_cdclk(struct intel_display *display,
>  					 SKL_CDCLK_READY_FOR_CHANGE, 3);
>  	if (ret) {
>  		drm_err(display->drm,
> -			"Failed to inform PCU about cdclk change (%d)\n", ret);
> +			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
>  		return;
>  	}
>  
> @@ -1221,8 +1224,11 @@ static void skl_set_cdclk(struct intel_display *display,
>  	intel_de_posting_read(display, CDCLK_CTL);
>  
>  	/* inform PCU of the change */
> -	intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
> -				 cdclk_config->voltage_level);
> +	ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
> +				       cdclk_config->voltage_level);
> +	if (ret)
> +		drm_err(display->drm,
> +			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
>  
>  	intel_update_cdclk(display);
>  }
> @@ -2263,8 +2269,7 @@ static void bxt_set_cdclk(struct intel_display *display,
>  
>  	if (ret) {
>  		drm_err(display->drm,
> -			"Failed to inform PCU about cdclk change (err %d, freq %d)\n",
> -			ret, cdclk);
> +			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
>  		return;
>  	}
>  
> @@ -2299,8 +2304,7 @@ static void bxt_set_cdclk(struct intel_display *display,
>  						       cdclk_config->voltage_level, 2);
>  	if (ret)
>  		drm_err(display->drm,
> -			"PCode CDCLK freq set failed, (err %d, freq %d)\n",
> -			ret, cdclk);
> +			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
>  
>  	intel_update_cdclk(display);
>  
> @@ -2571,14 +2575,13 @@ void intel_cdclk_dump_config(struct intel_display *display,
>  		    cdclk_config->voltage_level);
>  }
>  
> -static void dg2_cdclk_pcode_notify(struct intel_display *display,
> -				   u8 voltage_level,
> -				   u8 active_pipe_count,
> -				   u16 cdclk,
> -				   bool cdclk_update_valid,
> -				   bool pipe_count_update_valid)
> +static int dg2_cdclk_pcode_notify(struct intel_display *display,
> +				  u8 voltage_level,
> +				  u8 active_pipe_count,
> +				  u16 cdclk,
> +				  bool cdclk_update_valid,
> +				  bool pipe_count_update_valid)
>  {
> -	int ret;
>  	u32 update_mask = 0;
>  
>  	update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
> @@ -2589,14 +2592,10 @@ static void dg2_cdclk_pcode_notify(struct intel_display *display,
>  	if (pipe_count_update_valid)
>  		update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
>  
> -	ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
> -					 update_mask,
> -					 SKL_CDCLK_READY_FOR_CHANGE,
> -					 SKL_CDCLK_READY_FOR_CHANGE, 3);
> -	if (ret)
> -		drm_err(display->drm,
> -			"Failed to inform PCU about display config (err %d)\n",
> -			ret);
> +	return intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
> +					  update_mask,
> +					  SKL_CDCLK_READY_FOR_CHANGE,
> +					  SKL_CDCLK_READY_FOR_CHANGE, 3);
>  }
>  
>  static void intel_set_cdclk(struct intel_display *display,
> @@ -2674,6 +2673,7 @@ static void dg2_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
>  		intel_atomic_get_new_cdclk_state(state);
>  	unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
>  	bool change_cdclk, update_pipe_count;
> +	int ret;
>  
>  	if (!intel_cdclk_changed(&old_cdclk_state->actual,
>  				 &new_cdclk_state->actual) &&
> @@ -2708,8 +2708,11 @@ static void dg2_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
>  	if (update_pipe_count)
>  		num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
>  
> -	dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> -			       change_cdclk, update_pipe_count);
> +	ret = dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> +				     change_cdclk, update_pipe_count);
> +	if (ret)
> +		drm_err(display->drm,
> +			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
>  }
>  
>  static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state)
> @@ -2721,6 +2724,7 @@ static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state)
>  		intel_atomic_get_old_cdclk_state(state);
>  	unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
>  	bool update_cdclk, update_pipe_count;
> +	int ret;
>  
>  	/* According to "Sequence After Frequency Change", set voltage to used level */
>  	voltage_level = new_cdclk_state->actual.voltage_level;
> @@ -2747,8 +2751,11 @@ static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state)
>  	if (update_pipe_count)
>  		num_active_pipes = dg2_power_well_count(display, new_cdclk_state);
>  
> -	dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> -			       update_cdclk, update_pipe_count);
> +	ret = dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk,
> +				     update_cdclk, update_pipe_count);
> +	if (ret)
> +		drm_err(display->drm,
> +			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
>  }
>  
>  bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)

-- 
Jani Nikula, Intel

Re: [PATCH 10/14] drm/i915/cdclk: Extract bdw_cdclk_pcode_{pre, post}_notify()

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract the BSW pcode notify stuff to a few small helpers. The
> plan is to unify these between all the platforms and turn them
> into vfuncs.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +++++++++++++++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 542724256d0f..041b1fc8b3ee 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -872,6 +872,19 @@ static u32 bdw_cdclk_freq_sel(int cdclk)
>  	}
>  }
>  
> +static int bdw_cdclk_pcode_pre_notify(struct intel_display *display)
> +{
> +	return intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ,
> +					0x0);
> +}
> +
> +static int bdw_cdclk_pcode_post_notify(struct intel_display *display,
> +				       const struct intel_cdclk_config *cdclk_config)
> +{
> +	return intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
> +					cdclk_config->voltage_level);
> +}
> +
>  static void bdw_set_cdclk(struct intel_display *display,
>  			  const struct intel_cdclk_config *cdclk_config,
>  			  enum pipe pipe)
> @@ -888,7 +901,7 @@ static void bdw_set_cdclk(struct intel_display *display,
>  		     "trying to change cdclk frequency with cdclk not enabled\n"))
>  		return;
>  
> -	ret = intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
> +	ret = bdw_cdclk_pcode_pre_notify(display);
>  	if (ret) {
>  		drm_err(display->drm,
>  			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
> @@ -918,8 +931,7 @@ static void bdw_set_cdclk(struct intel_display *display,
>  	if (ret)
>  		drm_err(display->drm, "Switching back to LCPLL failed\n");
>  
> -	ret = intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
> -				       cdclk_config->voltage_level);
> +	ret = bdw_cdclk_pcode_post_notify(display, cdclk_config);
>  	if (ret)
>  		drm_err(display->drm,
>  			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);

-- 
Jani Nikula, Intel

Re: [PATCH 11/14] drm/i915/cdclk: Extract skl_cdclk_pcode_{pre, post}_notify()

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract the SKL/ICL+ pcode notify stuff to a few small helpers.
> The plan is to unify these between all the platforms and turn
> them into vfuncs.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 32 +++++++++++++---------
>  1 file changed, 19 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 041b1fc8b3ee..bb47fc4c86ee 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1170,6 +1170,21 @@ static u32 skl_cdclk_freq_sel(struct intel_display *display,
>  	}
>  }
>  
> +static int skl_cdclk_pcode_pre_notify(struct intel_display *display)
> +{
> +	return intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
> +					  SKL_CDCLK_PREPARE_FOR_CHANGE,
> +					  SKL_CDCLK_READY_FOR_CHANGE,
> +					  SKL_CDCLK_READY_FOR_CHANGE, 3);
> +}
> +
> +static int skl_cdclk_pcode_post_notify(struct intel_display *display,
> +				       const struct intel_cdclk_config *cdclk_config)
> +{
> +	return intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
> +					cdclk_config->voltage_level);
> +}
> +
>  static void skl_set_cdclk(struct intel_display *display,
>  			  const struct intel_cdclk_config *cdclk_config,
>  			  enum pipe pipe)
> @@ -1190,10 +1205,7 @@ static void skl_set_cdclk(struct intel_display *display,
>  	drm_WARN_ON_ONCE(display->drm,
>  			 display->platform.skylake && vco == 8640000);
>  
> -	ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
> -					 SKL_CDCLK_PREPARE_FOR_CHANGE,
> -					 SKL_CDCLK_READY_FOR_CHANGE,
> -					 SKL_CDCLK_READY_FOR_CHANGE, 3);
> +	ret = skl_cdclk_pcode_pre_notify(display);
>  	if (ret) {
>  		drm_err(display->drm,
>  			"Failed to inform PCODE about start of CDCLK change (%d)\n", ret);
> @@ -1235,9 +1247,7 @@ static void skl_set_cdclk(struct intel_display *display,
>  	intel_de_write(display, CDCLK_CTL, cdclk_ctl);
>  	intel_de_posting_read(display, CDCLK_CTL);
>  
> -	/* inform PCU of the change */
> -	ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
> -				       cdclk_config->voltage_level);
> +	ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
>  	if (ret)
>  		drm_err(display->drm,
>  			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);
> @@ -2266,10 +2276,7 @@ static void bxt_set_cdclk(struct intel_display *display,
>  	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
>  		ret = 0; /* NOOP */
>  	else if (DISPLAY_VER(display) >= 11)
> -		ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
> -						 SKL_CDCLK_PREPARE_FOR_CHANGE,
> -						 SKL_CDCLK_READY_FOR_CHANGE,
> -						 SKL_CDCLK_READY_FOR_CHANGE, 3);
> +		ret = skl_cdclk_pcode_pre_notify(display);
>  	else
>  		/*
>  		 * BSpec requires us to wait up to 150usec, but that leads to
> @@ -2302,8 +2309,7 @@ static void bxt_set_cdclk(struct intel_display *display,
>  	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
>  		ret = 0; /* NOOP */
>  	else if (DISPLAY_VER(display) >= 11)
> -		ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
> -					       cdclk_config->voltage_level);
> +		ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
>  	else
>  		/*
>  		 * The timeout isn't specified, the 2ms used here is based on

-- 
Jani Nikula, Intel

Re: [PATCH 12/14] drm/i915/cdclk: Extract bxt_cdclk_pcode_{pre, post}_notify()

[Jani Nikula]

On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract the BXT/GLK pcode notify stuff to a few small helpers.
> The plan is to unify these between all the platforms and turn
> them into vfuncs.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 42 +++++++++++++---------
>  1 file changed, 26 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index bb47fc4c86ee..749e366e60ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2226,6 +2226,29 @@ static u32 bxt_cdclk_ctl(struct intel_display *display,
>  	return val;
>  }
>  
> +static int bxt_cdclk_pcode_pre_notify(struct intel_display *display)
> +{
> +	/*
> +	 * BSpec requires us to wait up to 150usec, but that leads to
> +	 * timeouts; the 2ms used here is based on experiment.
> +	 */
> +	return intel_parent_pcode_write_timeout(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
> +						0x80000000, 2);
> +}
> +
> +static int bxt_cdclk_pcode_post_notify(struct intel_display *display,
> +				       const struct intel_cdclk_config *cdclk_config)
> +{
> +	/*
> +	 * The timeout isn't specified, the 2ms used here is based on
> +	 * experiment.
> +	 * FIXME: Waiting for the request completion could be delayed
> +	 * until the next PCODE request based on BSpec.
> +	 */
> +	return intel_parent_pcode_write_timeout(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
> +						cdclk_config->voltage_level, 2);
> +}
> +
>  static void _bxt_set_cdclk(struct intel_display *display,
>  			   const struct intel_cdclk_config *cdclk_config,
>  			   enum pipe pipe)
> @@ -2278,13 +2301,7 @@ static void bxt_set_cdclk(struct intel_display *display,
>  	else if (DISPLAY_VER(display) >= 11)
>  		ret = skl_cdclk_pcode_pre_notify(display);
>  	else
> -		/*
> -		 * BSpec requires us to wait up to 150usec, but that leads to
> -		 * timeouts; the 2ms used here is based on experiment.
> -		 */
> -		ret = intel_parent_pcode_write_timeout(display,
> -						       HSW_PCODE_DE_WRITE_FREQ_REQ,
> -						       0x80000000, 2);
> +		ret = bxt_cdclk_pcode_pre_notify(display);
>  
>  	if (ret) {
>  		drm_err(display->drm,
> @@ -2311,15 +2328,8 @@ static void bxt_set_cdclk(struct intel_display *display,
>  	else if (DISPLAY_VER(display) >= 11)
>  		ret = skl_cdclk_pcode_post_notify(display, cdclk_config);
>  	else
> -		/*
> -		 * The timeout isn't specified, the 2ms used here is based on
> -		 * experiment.
> -		 * FIXME: Waiting for the request completion could be delayed
> -		 * until the next PCODE request based on BSpec.
> -		 */
> -		ret = intel_parent_pcode_write_timeout(display,
> -						       HSW_PCODE_DE_WRITE_FREQ_REQ,
> -						       cdclk_config->voltage_level, 2);
> +		ret = bxt_cdclk_pcode_post_notify(display, cdclk_config);
> +
>  	if (ret)
>  		drm_err(display->drm,
>  			"Failed to inform PCODE about end of CDCLK change (%d)\n", ret);

-- 
Jani Nikula, Intel

✓ Xe.CI.BAT: success for drm/i915/cdclk: cdclk pcode related fixes and refactoring

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 880 bytes --]

== Series Details ==

Series: drm/i915/cdclk: cdclk pcode related fixes and refactoring
URL   : https://patchwork.freedesktop.org/series/168273/
State : success

== Summary ==

CI Bug Log - changes from xe-5231-fc59f76558703febba8056be87d1c97d14f7485e_BAT -> xe-pw-168273v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5231-fc59f76558703febba8056be87d1c97d14f7485e -> xe-pw-168273v1

  IGT_8956: 8956
  xe-5231-fc59f76558703febba8056be87d1c97d14f7485e: fc59f76558703febba8056be87d1c97d14f7485e
  xe-pw-168273v1: 168273v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/index.html

[-- Attachment #2: Type: text/html, Size: 1428 bytes --]

Re: [PATCH 02/14] drm/i915/cdclk: Pass CDCLK in MHz to pcode on DG2

[Ville Syrjälä]

On Wed, Jun 10, 2026 at 08:31:48PM +0300, Jani Nikula wrote:
> On Wed, 10 Jun 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We are currently trying to pass the CDCLK in kHz to the pcode
> > on DG2, while the pcode expects a value in MHz units. Adjust
> > the units appropriately.
> 
> How is it working? :o

I don't think DG2 pcode does all that much a with the information.
Eg. AFAIK it doesn't actually adjust any voltages due to this stuff.
I think it's more for some internal power usage estimates or something,
but dunno what that really means in practice.

> 
> Fixes: ?
> 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++++++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 9ca56bab281f..9718062d8d6c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -2703,8 +2703,10 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
> >  	 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK,
> >  	 * which basically means we choose the maximum of old and new CDCLK, if we know both
> >  	 */
> > -	if (change_cdclk)
> > +	if (change_cdclk) {
> >  		cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
> > +		cdclk = DIV_ROUND_UP(cdclk, 1000);
> > +	}
> 
> I'd consider s/cdclk/cdclk_mhz/g here and in intel_pcode_notify() to
> emphasize it's not kHz.
> 
> >  	/*
> >  	 * According to "Sequence For Pipe Count Change",
> > @@ -2740,8 +2742,10 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
> >  	 * According to "Sequence After Frequency Change",
> >  	 * set bits 25:16 to current CDCLK
> >  	 */
> > -	if (update_cdclk)
> > +	if (update_cdclk) {
> >  		cdclk = new_cdclk_state->actual.cdclk;
> > +		cdclk = DIV_ROUND_UP(cdclk, 1000);
> > +	}
> 
> Ditto.
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> >  
> >  	/*
> >  	 * According to "Sequence For Pipe Count Change",
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

✓ i915.CI.BAT: success for drm/i915/cdclk: cdclk pcode related fixes and refactoring

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1016 bytes --]

== Series Details ==

Series: drm/i915/cdclk: cdclk pcode related fixes and refactoring
URL   : https://patchwork.freedesktop.org/series/168274/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_18656 -> Patchwork_168274v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/index.html

Participating hosts (42 -> 40)
------------------------------

  Missing    (2): bat-dg2-13 fi-snb-2520m 


Changes
-------

  No changes found


Build changes
-------------

  * Linux: CI_DRM_18656 -> Patchwork_168274v1

  CI-20190529: 20190529
  CI_DRM_18656: 2bfaac2290b880c462bf89fae4fdb1559567af92 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8956: 8956
  Patchwork_168274v1: 2bfaac2290b880c462bf89fae4fdb1559567af92 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_168274v1/index.html

[-- Attachment #2: Type: text/html, Size: 1581 bytes --]

✗ Xe.CI.FULL: failure for drm/i915/cdclk: cdclk pcode related fixes and refactoring

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 13224 bytes --]

== Series Details ==

Series: drm/i915/cdclk: cdclk pcode related fixes and refactoring
URL   : https://patchwork.freedesktop.org/series/168273/
State : failure

== Summary ==

CI Bug Log - changes from xe-5231-fc59f76558703febba8056be87d1c97d14f7485e_FULL -> xe-pw-168273v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-168273v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-168273v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-168273v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_vblank@ts-continuation-suspend:
    - shard-bmg:          [PASS][1] -> [INCOMPLETE][2] +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5231-fc59f76558703febba8056be87d1c97d14f7485e/shard-bmg-10/igt@kms_vblank@ts-continuation-suspend.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-1/igt@kms_vblank@ts-continuation-suspend.html

  
Known issues
------------

  Here are the changes found in xe-pw-168273v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2327])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-3/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#2887])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-3/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [PASS][5] -> [INCOMPLETE][6] ([Intel XE#7084] / [Intel XE#8150]) +1 other test incomplete
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5231-fc59f76558703febba8056be87d1c97d14f7485e/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_chamelium_hpd@dp-hpd-storm:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2252]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-3/igt@kms_chamelium_hpd@dp-hpd-storm.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-lnl:          [PASS][8] -> [FAIL][9] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5231-fc59f76558703febba8056be87d1c97d14f7485e/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [PASS][10] -> [FAIL][11] ([Intel XE#301]) +1 other test fail
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5231-fc59f76558703febba8056be87d1c97d14f7485e/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2311])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#4141]) +2 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2313]) +4 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render.html

  * igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010:
    - shard-bmg:          [PASS][16] -> [SKIP][17] ([Intel XE#7915]) +5 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5231-fc59f76558703febba8056be87d1c97d14f7485e/shard-bmg-1/igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-7/igt@kms_hdr@static-toggle-dpms@pipe-a-hdmi-a-3-xrgb2101010.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#1489])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-3/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr@psr2-sprite-render:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2234] / [Intel XE#2850])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-3/igt@kms_psr@psr2-sprite-render.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#3904] / [Intel XE#7342])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-3/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@xe_eudebug@discovery-race:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#7636])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-3/igt@xe_eudebug@discovery-race.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][22] -> [INCOMPLETE][23] ([Intel XE#6321])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5231-fc59f76558703febba8056be87d1c97d14f7485e/shard-bmg-10/igt@xe_evict@evict-mixed-many-threads-small.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-4/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#7136]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-3/igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-dyn-priority:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#6874]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-3/igt@xe_exec_multi_queue@few-execs-preempt-mode-fault-dyn-priority.html

  * igt@xe_exec_reset@long-spin-many-preempt-threads:
    - shard-bmg:          [PASS][26] -> [FAIL][27] ([Intel XE#7956])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5231-fc59f76558703febba8056be87d1c97d14f7485e/shard-bmg-9/igt@xe_exec_reset@long-spin-many-preempt-threads.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-6/igt@xe_exec_reset@long-spin-many-preempt-threads.html

  * igt@xe_exec_reset@long-spin-sys-reuse-many-preempt-threads:
    - shard-bmg:          [PASS][28] -> [FAIL][29] ([Intel XE#7850])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5231-fc59f76558703febba8056be87d1c97d14f7485e/shard-bmg-10/igt@xe_exec_reset@long-spin-sys-reuse-many-preempt-threads.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-4/igt@xe_exec_reset@long-spin-sys-reuse-many-preempt-threads.html

  * igt@xe_pxp@pxp-termination-key-update-post-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#4733] / [Intel XE#7417])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-3/igt@xe_pxp@pxp-termination-key-update-post-suspend.html

  
#### Possible fixes ####

  * igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-bmg:          [SKIP][31] ([Intel XE#7915]) -> [PASS][32] +1 other test pass
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5231-fc59f76558703febba8056be87d1c97d14f7485e/shard-bmg-7/igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-3-xrgb16161616f.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-1/igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@xe_exec_system_allocator@process-many-large-execqueues-new-bo-map:
    - shard-bmg:          [ABORT][33] ([Intel XE#7893]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5231-fc59f76558703febba8056be87d1c97d14f7485e/shard-bmg-1/igt@xe_exec_system_allocator@process-many-large-execqueues-new-bo-map.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-3/igt@xe_exec_system_allocator@process-many-large-execqueues-new-bo-map.html

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][35] ([Intel XE#4141]) -> [ABORT][36] ([Intel XE#7814] / [Intel XE#7893])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5231-fc59f76558703febba8056be87d1c97d14f7485e/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][37] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][38] ([Intel XE#2426] / [Intel XE#5848])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5231-fc59f76558703febba8056be87d1c97d14f7485e/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/shard-bmg-9/igt@kms_tiled_display@basic-test-pattern.html

  
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#7814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7814
  [Intel XE#7850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7850
  [Intel XE#7893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7893
  [Intel XE#7915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7915
  [Intel XE#7956]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7956
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150


Build changes
-------------

  * Linux: xe-5231-fc59f76558703febba8056be87d1c97d14f7485e -> xe-pw-168273v1

  IGT_8956: 8956
  xe-5231-fc59f76558703febba8056be87d1c97d14f7485e: fc59f76558703febba8056be87d1c97d14f7485e
  xe-pw-168273v1: 168273v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168273v1/index.html

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